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Architecture updater (auto-sync) - Updating AArch64 (#2026)

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* Update sysop inc file

* Fix missing  braces warning

* Handle new system operands

* Fix build errors by renaming.

* Fix segfault

* Fix segfault

* Add custom MCOperand valiadtors

* Add AArch64 case for getFeatureBits

* Fix infinite loop

* Fix braces warning.

* Implement loopuo by name for sys operands

* Fix incorrect translation which remove else if statements.

* Fix several segfaults

* Rename GetRegFromClass patch

* Fix segfaults and asserts

* Fix segfault

* Move MRI setting to Mapping

* Remove unused code

* Add add_op_X functinos for AArch64.

* Add fill detail functins

* Handle RegWithShiftExtend operands

* Handle TypedVectorList operands.

* Handle ComplexRoatation operands

* Handle MemExtend operands

* Handle ImmRangeScale operands

* Handle ExactFPImm operands

* Handle GPRSeqPairsClass operands

* Handle Imm8OptLsl operands

* Handle ImmScale operands

* Handle LogicalImm operands

* Handle Matrix operands

* Handle SME Matrix tiles and vectors.

* Handle normal operands.

* Fix segfault.

* Handle PostInc operands.

* Reorder VecLayout enum to have no duplicate enum value.

* Handle PredicateAsCounter operands

* Handle ZPRasFPR operands

* Handle VectorIndex operands

* Handle UImm12Offset operands.

* Move reg suffix to enum val to single function.

* Handle SVERegOp operands

* Handle SVELogicalImm operands

* Handle SImm operand

* Handle PrefetchOp operands

* Handle Imm and ImmHex operands

* Handle GPR64as32 and GPR64x8 operands

* Add missing break

* Handle FPImm operand

* Handle ExtendedRegister opreand

* Handle CondCode operands

* Handle BTIHintOp operands

* Handle BarrierOption operands

* Handle BarrierXSOption

* Add not implemeted case again

* Handle ArithExtend operands

* Handle AdrpLabel and AlignedLabel operands

* Handle AMNoIndex operands

* Handle AddSubImm operands

* Handle MSRSystemRegisters and MRSSystemRegister operands

* Handle PSBHntOp and RPRFMOperand operands

* Remove unused variables

* Handle InverseCondCode operands

* Handle ImplicityTypedVectorList operands

* Handle ShiftedRegister operands

* Handle Shifter operands

* Handle SIMDType10Operand operands

* Handle SVCROp operands

* Handle SVEPattern operands

* Handle SVEVecLenSpecifier operands

* Handle SysCROperands

* Handle SysXzrPair operands

* Handle PState operands

* Handle VRegOperands

* Primt SME oeprands.

* Fix cs_operand.h include

* Rename arm64 -> aarch64 in python bindings.

* Add Python bindings for SH

* Fix ARM Python bindings (#2127)

* Restructure auto-sync update scripts.

* Move Helper functions to Updater dir

* Move requirements.txt

* Add basic ASUpdater.py

* Run black.

* Add inc file generater to updater

* Add option to select certain inc files fore generation.

* Enable clean build and implement patcher for inc files.

* Format config

* Patch main header files after inc generation.

* Implement clang-format function (unused yet, because it takes forever.)

* Copy generated inc files to arch dir

* Invert clean option (noramlly we need to clean the build dir.)

* Clearify arg doc

* Rename SystemRegister file for AArch64

* Centralize handling of path variables.

* Check if SystemOperands had to be generated before renaming on of its files.

* Replace class parameters by calling get_path

* Remove updater config which only contained paths.

* Add refactor option.

* Remove more path handling in the Configurator.

* Add translation step to updater.

* Fix includes after CppTranslator was moved into the Updater

* Remove updater config

* Fix several issue in the Configurator

* Fix file operations

* Remove addition argument from translator.

* Add Differ step to updater.

* Add path variable for arch_config

* Add diff step.

* Fix typo

* Introduce .clang-format path variable.

* Remove duplicate functions

* Add option to select update steps to execute.

* Check in write functions for write flag.

* Rename PatchMainHeader -> HeaderPatcher

* Move .gitignore

* Add README to vendor dir.

* Add all system operands to cstool output

* Update cstest with aarch64 changes

* Remove wb flag of aarch64 detail struct

* Set updates_flag after decoding

* Set writeback after decoding.

* Rename ARM64 -> AArch64

* Update printer and op mapping

* Exit normally

* Add AArch64 alias

* Fix some tmeplate function calls

* Fix flag check after rebase.

* Fix build by commentig unnused code.

* Add memory operand flag

* Handle memory operands printed via generic printOperand function.

* Handle UImm memory offsets

* Introduce MEM_REG and MEM_IMM op types

* Handle scaled memory immediates

* Check for op_count before checking for mem op at -1 index.

* Update memory operand flags.

* Pass imm/reg memory ops in set_imm/reg to set_mem.

* Add missing set_sme_operand call and fix assert.

* Remove CS_OP_MEM flag before entering switch.

* Preidcates are registers.

* Add shift info always to the previous operand

* Check for generic system regs

* Handle NumLanes = 0 LaneKind = q case

* Replace printImm call with normal print logic. Otherwise ops get added twice to detail.

* Handle FP operands in printOperand.

* Add access information to float operands.

* Rewrite SME matrix handling.

* Set correct SME layouts and allow for immediate range sme offsets.

* Handle cases of unknown system alias by setting their raw values

* Update cstool and header file with new SME offset handling

* Handle SME Tile lists.

* Fix build error in cstest

* Update MC tests for AArch64

* Handle TLBI operands and fix printing bug.

* Fix: Print signed value as signed.

* Add more system alias to detail.

* Remove duplicate hex prefix

* Set correct values for the register info

* Replace tabs with white spaces

* Move string append logic to own function.

* Set DecodeComplete = true before decoding (as originally in the LLVM code).

* Change type of feature argument, since only LLVM features are passed, not CS groups.

* Imitate lower_bound for the index table binary search.

* Remove trailing comments from test files.

* Print shift amount in decimal

* Save detail of shift alias instructions.

* Add extension details fot ext instruction alias

* Print LSB and width in decimal

* Fix LLVM bug. The feature check for V8_2a doesn't check if all features are enabled.

* Fix lower_bounds check.
For m == 0 we wrap around 0 of cause.

* Fix feature check. Add check for FeatureAll since it includes XS

* Operate on temporary MCInst when trying decoding.

* Add lower_bound behavior to IndexTypeStr binsearch.

* Fix MC tests which were incorrect because of missing FeatureAll check

* Add Alias handling for AArch64

* Update system operands with SYSIMM types and add additional sysop category.

* Add macros for meta programming (ARM64 <-> AArch64 selection).

* Fix union/struct confusion and add raw_value member to uninions.

* Allow to set Syntax and mode options for AArch64

* Fix build warning by using correct type

* Print shift value in decimal

* Add missing call to add_cs_detail.

* Update name map files with normalized names.

* Remove unused function

* Add check if detail should be filled.

* Fill detail for real instructions if only real detail is requested.

* Add always the extension.

* Make dir creation log message debug level

* Implement ADR immediate operand printer.

See: c3484b1fdc

* Check for flag registers beeing written and update flag.

* Move multiple CondCode helpers to aarch64.h because they are so freaking useful.

+ Print CC if it is EQ

* Fix incorrectly initialized CC and VectorLayout.

* Add LSL shift type for extensions.

* Fix case when shift amount is 0

* Fix post-index memory instructions.

* Pass raw immediate through getShiftValue to extract actual shift amount

* Setup AArch64 detail ops.

* Add flag for operands part of a list.

* Set vector indices for all relevant registers.

* Add missing call to add_cs_detail for postIncOperands

* Add ugly yet reliable way to determine post-index addressing mode

* Add support for old Capstone register alias.

* Remove leading space before some alias mnemonics.

* add AARCH64 to `cmake.sh`

* add HAS_AARCH64 to `cs.c`

* should probably just reference `cs_operand.h` in `aarch64.h`

* hint compiler at `AArch64_SYSREG` enum type for casting purposes

* update `Makefile` for AARCH64

leaves `CAPSTONE_HAS_ARM64` supported

* `testFeatureBits` platform function check

`testFeatureBits` should check if the platform function is visible first

* update tests to use AARCH64 convention

* hack: avoid enum casts for `MCInst` Values

Apple compiler really hates typecasting a enum, even if bounded from a unsigned. Lets set the raw_value directly

is a hack and needs proper review

* Check for present detail before accessing it.

* Add CS only groups

* Use general map ins_op type

* Fix build warning about str size computation.

* Disable warning about unitialized value for GCC 11.

Imm is initialized and the warning does not appear
in later versions.

* Use correct include guard for PPC

* Add missing requirements

* Update SystemOperand enums.

* Fix overlapping comparison warning

* Fix reachable assert where OpNum is not of type IMM

* Handle 0.0 operand for fcmp

* Fix incorrect variable passed.

* Fix for MacOS which doesn't know the warning and throws another one.

* Make getExtendEncoding static to fix build warning on MSVC.

* Fix build error: 'missing binary operator before token' by checking __GNUC__

* Add string search to add vector layout info.

* Add missing mem disponents of several ldr and str instructions.

* Add 0 immediates to several instructions.

* Rename v regs to q and d variant.

The cs_regname API can not pass the variant name of the register requested.
So we simply emit the default variant name.

* Fix incorrect enum value.

* Fix tests for system operands.

* Fix syntax issues in tests.

* Rename Arm64 -> AArch64 Python bindings.

* Fix Python bindings C structs.

* Fix generation of constants (ARMCC skipped because it starts with ARM)

* Update const files

* Remove -Wmaybe-uninitialized warning since it fails fuzz build

* Add missing comma

* Fix case

* Fix AArch64 Python bindings:

- Do not generate constants automatically (dscript is way too buggy).
- Update printing of details.

* Rename ARM64 -> AArch64 in test_corpus.py

* Rename test_arm64 -> test_aarch64

* Rename ARM-64 -> AArch64

* Fix diff CI test by disassembling AArch64 at former ARM64 place

* Fix several wrong types and remove unnecessary memebers from Python binding

* Fix: Same printing format of detail for cstool, test_ and test_*.py

* Fix: pass correct op index for mov alias with op[1] == reg wzr.

* Set prfm op manuall in case of unnown sysop. set_imm would add it to an memory operand wihtout base.

* Fix: If barrier ops are not set an assert is reached.

We fix it here by simply getting the immediate as the printing code does.

---------

Co-authored-by: Peace-Maker <peace-maker@wcfan.de>
Co-authored-by: Dayton <5340801+watbulb@users.noreply.github.com>
This commit is contained in:
Rot127 2023-11-15 04:12:14 +00:00 committed by GitHub
parent b87cf06209
commit ef89b18a88
420 changed files with 224007 additions and 145474 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
.gitignore vendored
View File

@ -37,7 +37,7 @@ bindings/ocaml/*.cmxa
bindings/ocaml/*.mli
bindings/ocaml/test
bindings/ocaml/test_arm
bindings/ocaml/test_arm64
bindings/ocaml/test_aarch64
bindings/ocaml/test_basic
bindings/ocaml/test_mips
bindings/ocaml/test_x86
@ -54,7 +54,7 @@ tests/test_basic
tests/test_detail
tests/test_iter
tests/test_arm
tests/test_arm64
tests/test_aarch64
tests/test_mips
tests/test_x86
tests/test_ppc

36
CMakeLists.txt
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@ -45,8 +45,8 @@ option(CAPSTONE_ARCHITECTURE_DEFAULT "Whether architectures are enabled by defau
option(CAPSTONE_DEBUG "Whether to enable extra debug assertions" OFF)
option(CAPSTONE_INSTALL "Generate install target" ${PROJECT_IS_TOP_LEVEL})
set(SUPPORTED_ARCHITECTURES ARM ARM64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV SH TRICORE)
set(SUPPORTED_ARCHITECTURE_LABELS ARM ARM64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF RISCV SH TriCore)
set(SUPPORTED_ARCHITECTURES ARM AARCH64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV SH TRICORE)
set(SUPPORTED_ARCHITECTURE_LABELS ARM AARCH64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF RISCV SH TriCore)
list(LENGTH SUPPORTED_ARCHITECTURES count)
math(EXPR count "${count}-1")
@ -123,7 +123,7 @@ set(HEADERS_ENGINE
)
set(HEADERS_COMMON
include/capstone/arm64.h
include/capstone/aarch64.h
include/capstone/arm.h
include/capstone/capstone.h
include/capstone/cs_operand.h
@ -181,35 +181,35 @@ if(CAPSTONE_ARM_SUPPORT)
set(TEST_SOURCES ${TEST_SOURCES} test_arm.c)
endif()
if(CAPSTONE_ARM64_SUPPORT)
add_definitions(-DCAPSTONE_HAS_ARM64)
set(SOURCES_ARM64
if(CAPSTONE_AARCH64_SUPPORT)
add_definitions(-DCAPSTONE_HAS_AARCH64)
set(SOURCES_AARCH64
arch/AArch64/AArch64BaseInfo.c
arch/AArch64/AArch64Disassembler.c
arch/AArch64/AArch64DisassemblerExtension.c
arch/AArch64/AArch64InstPrinter.c
arch/AArch64/AArch64Mapping.c
arch/AArch64/AArch64Module.c
)
set(HEADERS_ARM64
set(HEADERS_AARCH64
arch/AArch64/AArch64AddressingModes.h
arch/AArch64/AArch64BaseInfo.h
arch/AArch64/AArch64Disassembler.h
arch/AArch64/AArch64DisassemblerExtension.h
arch/AArch64/AArch64InstPrinter.h
arch/AArch64/AArch64Linkage.h
arch/AArch64/AArch64Mapping.h
arch/AArch64/AArch64GenAsmWriter.inc
arch/AArch64/AArch64GenDisassemblerTables.inc
arch/AArch64/AArch64GenInstrInfo.inc
arch/AArch64/AArch64GenRegisterInfo.inc
arch/AArch64/AArch64GenRegisterName.inc
arch/AArch64/AArch64GenRegisterV.inc
arch/AArch64/AArch64GenSubtargetInfo.inc
arch/AArch64/AArch64GenSystemOperands.inc
arch/AArch64/AArch64GenSystemOperands_enum.inc
arch/AArch64/AArch64MappingInsn.inc
arch/AArch64/AArch64MappingInsnName.inc
arch/AArch64/AArch64MappingInsnOp.inc
arch/AArch64/AArch64GenCSMappingInsn.inc
arch/AArch64/AArch64GenCSMappingInsnName.inc
arch/AArch64/AArch64GenCSMappingInsnOp.inc
)
set(TEST_SOURCES ${TEST_SOURCES} test_arm64.c)
set(TEST_SOURCES ${TEST_SOURCES} test_aarch64.c)
endif()
if(CAPSTONE_MIPS_SUPPORT)
@ -576,7 +576,7 @@ endif()
set(ALL_SOURCES
${SOURCES_ENGINE}
${SOURCES_ARM}
${SOURCES_ARM64}
${SOURCES_AARCH64}
${SOURCES_MIPS}
${SOURCES_PPC}
${SOURCES_X86}
@ -599,7 +599,7 @@ set(ALL_HEADERS
${HEADERS_COMMON}
${HEADERS_ENGINE}
${HEADERS_ARM}
${HEADERS_ARM64}
${HEADERS_AARCH64}
${HEADERS_MIPS}
${HEADERS_PPC}
${HEADERS_X86}
@ -662,7 +662,7 @@ endif()
source_group("Source\\Engine" FILES ${SOURCES_ENGINE})
source_group("Source\\ARM" FILES ${SOURCES_ARM})
source_group("Source\\ARM64" FILES ${SOURCES_ARM64})
source_group("Source\\AARCH64" FILES ${SOURCES_AARCH64})
source_group("Source\\Mips" FILES ${SOURCES_MIPS})
source_group("Source\\PowerPC" FILES ${SOURCES_PPC})
source_group("Source\\Sparc" FILES ${SOURCES_SPARC})
@ -683,7 +683,7 @@ source_group("Source\\TriCore" FILES ${SOURCES_TRICORE})
source_group("Include\\Common" FILES ${HEADERS_COMMON})
source_group("Include\\Engine" FILES ${HEADERS_ENGINE})
source_group("Include\\ARM" FILES ${HEADERS_ARM})
source_group("Include\\ARM64" FILES ${HEADERS_ARM64})
source_group("Include\\AARCH64" FILES ${HEADERS_AARCH64})
source_group("Include\\Mips" FILES ${HEADERS_MIPS})
source_group("Include\\PowerPC" FILES ${HEADERS_PPC})
source_group("Include\\Sparc" FILES ${HEADERS_SPARC})

2
COMPILE.TXT
View File

@ -148,7 +148,7 @@ Capstone requires no prerequisite packages, so it is easy to compile & install.
(5) Cross-compile for Android
To cross-compile for Android (smartphone/tablet), Android NDK is required.
NOTE: Only ARM and ARM64 are currently supported.
NOTE: Only ARM and AARCH64 are currently supported.
$ NDK=/android/android-ndk-r10e ./make.sh cross-android arm
or

4
COMPILE_CMAKE.TXT
View File

@ -20,7 +20,7 @@ Get CMake for free from http://www.cmake.org.
run "cmake" with the unwanted archs disabled (set to 0) as followings.
- CAPSTONE_ARM_SUPPORT: support ARM. Run cmake with -DCAPSTONE_ARM_SUPPORT=0 to remove ARM.
- CAPSTONE_ARM64_SUPPORT: support ARM64. Run cmake with -DCAPSTONE_ARM64_SUPPORT=0 to remove ARM64.
- CAPSTONE_AARCH64_SUPPORT: support AARCH64. Run cmake with -DCAPSTONE_AARCH64_SUPPORT=0 to remove AARCH64.
- CAPSTONE_M680X_SUPPORT: support M680X. Run cmake with -DCAPSTONE_M680X_SUPPORT=0 to remove M680X.
- CAPSTONE_M68K_SUPPORT: support M68K. Run cmake with -DCAPSTONE_M68K_SUPPORT=0 to remove M68K.
- CAPSTONE_MIPS_SUPPORT: support Mips. Run cmake with -DCAPSTONE_MIPS_SUPPORT=0 to remove Mips.
@ -112,7 +112,7 @@ Get CMake for free from http://www.cmake.org.
../cmake.sh x86
Will just target the x86 architecture. The list of available architectures is: ARM,
ARM64, M68K, MIPS, PowerPC, Sparc, SystemZ, XCore, x86, TMS320C64x, M680x, EVM, MOS65XX,
AARCH64, M68K, MIPS, PowerPC, Sparc, SystemZ, XCore, x86, TMS320C64x, M680x, EVM, MOS65XX,
WASM, BPF, RISCV.
(4) You can also create an installation image with cmake, by using the 'install' target.

2
COMPILE_MSVC.TXT
View File

@ -31,7 +31,7 @@ versions, and Windows Driver Kit 8.1 Update 1 or newer versions are required.
to customize Capstone library, as followings.
- CAPSTONE_HAS_ARM: support ARM. Delete this to remove ARM support.
- CAPSTONE_HAS_ARM64: support ARM64. Delete this to remove ARM64 support.
- CAPSTONE_HAS_AARCH64: support AARCH64. Delete this to remove AARCH64 support.
- CAPSTONE_HAS_M68K: support M68K. Delete this to remove M68K support.
- CAPSTONE_HAS_MIPS: support Mips. Delete this to remove Mips support.
- CAPSTONE_HAS_POWERPC: support PPC. Delete this to remove PPC support.

2
HACK.TXT
View File

@ -5,7 +5,7 @@ Capstone source is organized as followings.
. <- core engine + README + COMPILE.TXT etc
├── arch <- code handling disasm engine for each arch
│   ├── AArch64 <- ARM64 (aka ARMv8) engine
│   ├── AArch64 <- AArch64 engine
│   ├── ARM <- ARM engine
│   ├── BPF <- Berkeley Packet Filter engine
│   ├── EVM <- Ethereum engine

15
MCInst.c
View File

@ -144,7 +144,7 @@ void MCOperand_setReg(MCOperand *op, unsigned Reg)
op->RegVal = Reg;
}
int64_t MCOperand_getImm(MCOperand *op)
int64_t MCOperand_getImm(const MCOperand *op)
{
return op->ImmVal;
}
@ -281,7 +281,7 @@ uint64_t MCInst_getOpVal(MCInst *MI, unsigned OpNum)
return MCOperand_getImm(op);
else
assert(0 && "Operand type not handled in this getter.");
return false;
return MCOperand_getImm(op);
}
void MCInst_setIsAlias(MCInst *MI, bool Flag) {
@ -289,3 +289,14 @@ void MCInst_setIsAlias(MCInst *MI, bool Flag) {
MI->isAliasInstr = Flag;
MI->flat_insn->is_alias = Flag;
}
/// @brief Copies the relevant members of a temporary MCInst to
/// the main MCInst. This is used if TryDecode was run on a temporary MCInst.
/// @param MI The main MCInst
/// @param TmpMI The temporary MCInst.
void MCInst_updateWithTmpMI(MCInst *MI, MCInst *TmpMI) {
MI->size = TmpMI->size;
MI->Opcode = TmpMI->Opcode;
assert(MI->size < MAX_MC_OPS);
memcpy(MI->Operands, TmpMI->Operands, sizeof(MI->Operands[0]) * MI->size);
}

4
MCInst.h
View File

@ -68,7 +68,7 @@ unsigned MCOperand_getReg(const MCOperand *op);
/// setReg - Set the register number.
void MCOperand_setReg(MCOperand *op, unsigned Reg);
int64_t MCOperand_getImm(MCOperand *op);
int64_t MCOperand_getImm(const MCOperand *op);
void MCOperand_setImm(MCOperand *op, int64_t Val);
@ -171,4 +171,6 @@ static inline bool MCInst_isAlias(const MCInst *MI) {
return MI->isAliasInstr;
}
void MCInst_updateWithTmpMI(MCInst *MI, MCInst *TmpMI);
#endif

20
MCInstPrinter.c
View File

@ -7,6 +7,7 @@
extern bool ARM_getFeatureBits(unsigned int mode, unsigned int feature);
extern bool PPC_getFeatureBits(unsigned int mode, unsigned int feature);
extern bool AArch64_getFeatureBits(unsigned int mode, unsigned int feature);
static bool testFeatureBits(const MCInst *MI, uint32_t Value)
{
@ -14,10 +15,19 @@ static bool testFeatureBits(const MCInst *MI, uint32_t Value)
switch (MI->csh->arch) {
default:
assert(0 && "Not implemented for current arch.");
return false;
#ifdef CAPSTONE_HAS_ARM
case CS_ARCH_ARM:
return ARM_getFeatureBits(MI->csh->mode, Value);
#endif
#ifdef CAPSTONE_HAS_POWERPC
case CS_ARCH_PPC:
return PPC_getFeatureBits(MI->csh->mode, Value);
#endif
#ifdef CAPSTONE_HAS_AARCH64
case CS_ARCH_AARCH64:
return AArch64_getFeatureBits(MI->csh->mode, Value);
#endif
}
}
@ -185,6 +195,11 @@ unsigned int binsearch_IndexTypeEncoding(const struct IndexType *index, size_t s
while(left <= right) {
m = (left + right) / 2;
if (encoding == index[m].encoding) {
// LLVM actually uses lower_bound for the index table search
// Here we need to check if a previous entry is of the same encoding
// and return the first one.
while (m > 0 && encoding == index[m - 1].encoding)
--m;
return m;
}
@ -218,6 +233,11 @@ unsigned int binsearch_IndexTypeStrEncoding(const struct IndexTypeStr *index, si
while(left <= right) {
m = (left + right) / 2;
if (strcmp(name, index[m].name) == 0) {
// LLVM actually uses lower_bound for the index table search
// Here we need to check if a previous entry is of the same encoding
// and return the first one.
while (m > 0 && (strcmp(name, index[m - 1].name) == 0))
--m;
return m;
}

19
Makefile
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@ -126,14 +126,15 @@ ifneq (,$(findstring arm,$(CAPSTONE_ARCHS)))
LIBOBJ_ARM += $(LIBSRC_ARM:%.c=$(OBJDIR)/%.o)
endif
DEP_ARM64 =
DEP_ARM64 += $(wildcard arch/AArch64/AArch64*.inc)
DEP_AARCH64 =
DEP_AARCH64 += $(wildcard arch/AArch64/AArch64*.inc)
LIBOBJ_ARM64 =
LIBOBJ_AARCH64 =
ifneq (,$(findstring aarch64,$(CAPSTONE_ARCHS)))
CFLAGS += -DCAPSTONE_HAS_ARM64
LIBSRC_ARM64 += $(wildcard arch/AArch64/AArch64*.c)
LIBOBJ_ARM64 += $(LIBSRC_ARM64:%.c=$(OBJDIR)/%.o)
CFLAGS += -DCAPSTONE_HAS_AARCH64
LIBSRC_AARCH64 += $(wildcard arch/AArch64/AArch64*.c)
LIBOBJ_AARCH64 += $(LIBSRC_AARCH64:%.c=$(OBJDIR)/%.o)
endif
@ -327,7 +328,7 @@ endif
LIBOBJ =
LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o $(OBJDIR)/MCInst.o $(OBJDIR)/MCInstPrinter.o $(OBJDIR)/Mapping.o
LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_ARM64) $(LIBOBJ_M68K) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_RISCV) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) $(LIBOBJ_SH)
LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_AARCH64) $(LIBOBJ_M68K) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_RISCV) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) $(LIBOBJ_SH)
LIBOBJ += $(LIBOBJ_X86) $(LIBOBJ_XCORE) $(LIBOBJ_TMS320C64X) $(LIBOBJ_M680X) $(LIBOBJ_EVM) $(LIBOBJ_MOS65XX) $(LIBOBJ_WASM) $(LIBOBJ_BPF)
LIBOBJ += $(LIBOBJ_TRICORE)
@ -448,7 +449,7 @@ endif
$(LIBOBJ): config.mk
$(LIBOBJ_ARM): $(DEP_ARM)
$(LIBOBJ_ARM64): $(DEP_ARM64)
$(LIBOBJ_AARCH64): $(DEP_AARCH64)
$(LIBOBJ_M68K): $(DEP_M68K)
$(LIBOBJ_MIPS): $(DEP_MIPS)
$(LIBOBJ_PPC): $(DEP_PPC)
@ -550,9 +551,9 @@ dist:
git archive --format=tar.gz --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).tgz
git archive --format=zip --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).zip
TESTS = test_basic test_detail test_arm test_arm64 test_m68k test_mips test_ppc test_sparc test_tricore
TESTS = test_basic test_detail test_arm test_aarch64 test_m68k test_mips test_ppc test_sparc test_tricore
TESTS += test_systemz test_x86 test_xcore test_iter test_evm test_riscv test_mos65xx test_wasm test_bpf
TESTS += test_basic.static test_detail.static test_arm.static test_arm64.static
TESTS += test_basic.static test_detail.static test_arm.static test_aarch64.static
TESTS += test_m68k.static test_mips.static test_ppc.static test_sparc.static
TESTS += test_systemz.static test_x86.static test_xcore.static test_m680x.static
TESTS += test_skipdata test_skipdata.static test_iter.static test_evm.static test_riscv.static

3
Mapping.c
View File

@ -312,6 +312,7 @@ const cs_ac_type mapping_get_op_access(MCInst *MI, unsigned OpNum,
DEFINE_get_detail_op(arm, ARM);
DEFINE_get_detail_op(ppc, PPC);
DEFINE_get_detail_op(tricore, TriCore);
DEFINE_get_detail_op(aarch64, AArch64);
/// Returns true if for this architecture the
/// alias operands should be filled.
@ -363,7 +364,7 @@ void map_set_alias_id(MCInst *MI, const SStream *O, const name_map *alias_mnem_i
for (; j < sizeof(alias_mnem) - 1; ++j, ++i) {
if (!asm_str_buf[i] || asm_str_buf[i] == ' ' || asm_str_buf[i] == '\t')
break;
alias_mnem[j] = O->buffer[i];
alias_mnem[j] = asm_str_buf[i];
}
MI->flat_insn->alias_id = name2id(alias_mnem_id_map, map_size, alias_mnem);

12
Mapping.h
View File

@ -42,7 +42,7 @@ unsigned short insn_find(const insn_map *m, unsigned int max, unsigned int id,
unsigned int find_cs_id(unsigned MC_Opcode, const insn_map *imap,
unsigned imap_size);
#define MAX_NO_DATA_TYPES 10
#define MAX_NO_DATA_TYPES 16
///< A LLVM<->CS Mapping entry of an MCOperand.
typedef struct {
@ -120,6 +120,7 @@ void map_cs_id(MCInst *MI, const insn_map *imap, unsigned int imap_size);
DECL_get_detail_op(arm, ARM);
DECL_get_detail_op(ppc, PPC);
DECL_get_detail_op(tricore, TriCore);
DECL_get_detail_op(aarch64, AArch64);
/// Increments the detail->arch.op_count by one.
#define DEFINE_inc_detail_op_count(arch, ARCH) \
@ -141,6 +142,8 @@ DEFINE_inc_detail_op_count(ppc, PPC);
DEFINE_dec_detail_op_count(ppc, PPC);
DEFINE_inc_detail_op_count(tricore, TriCore);
DEFINE_dec_detail_op_count(tricore, TriCore);
DEFINE_inc_detail_op_count(aarch64, AArch64);
DEFINE_dec_detail_op_count(aarch64, AArch64);
/// Returns true if a memory operand is currently edited.
static inline bool doing_mem(const MCInst *MI)
@ -165,6 +168,7 @@ static inline void set_doing_mem(const MCInst *MI, bool status)
DEFINE_get_arch_detail(arm, ARM);
DEFINE_get_arch_detail(ppc, PPC);
DEFINE_get_arch_detail(tricore, TriCore);
DEFINE_get_arch_detail(aarch64, AArch64);
static inline bool detail_is_set(const MCInst *MI)
{
@ -178,12 +182,6 @@ static inline cs_detail *get_detail(const MCInst *MI)
return MI->flat_insn->detail;
}
static inline bool set_detail_ops(const MCInst *MI)
{
assert(MI && MI->flat_insn);
return MI->fillDetailOps;
}
/// Returns if the given instruction is an alias instruction.
#define RETURN_IF_INSN_IS_ALIAS(MI) \
do { \

2
README.md
View File

@ -12,7 +12,7 @@ disasm engine for binary analysis and reversing in the security community.
Created by Nguyen Anh Quynh, then developed and maintained by a small community,
Capstone offers some unparalleled features:
- Support multiple hardware architectures: ARM, ARM64 (ARMv8), BPF, Ethereum VM,
- Support multiple hardware architectures: ARM, AArch64, BPF, Ethereum VM,
M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ,
TMS320C64X, TriCore, Webassembly, XCore and X86 (16, 32, 64).

573
arch/AArch64/AArch64AddressingModes.h
View File

@ -1,9 +1,22 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===- AArch64AddressingModes.h - AArch64 Addressing Modes ------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@ -11,20 +24,25 @@
//
//===----------------------------------------------------------------------===//
#ifndef CS_AARCH64_ADDRESSINGMODES_H
#define CS_AARCH64_ADDRESSINGMODES_H
#ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64ADDRESSINGMODES_H
#define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64ADDRESSINGMODES_H
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
#include <capstone/platform.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "../../MathExtras.h"
#include <assert.h>
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
/// AArch64_AM - AArch64 Addressing Mode Stuff
//===----------------------------------------------------------------------===//
// Shifts
//
typedef enum AArch64_AM_ShiftExtendType {
typedef enum {
AArch64_AM_InvalidShiftExtend = -1,
AArch64_AM_LSL = 0,
AArch64_AM_LSR,
@ -41,39 +59,61 @@ typedef enum AArch64_AM_ShiftExtendType {
AArch64_AM_SXTH,
AArch64_AM_SXTW,
AArch64_AM_SXTX,
} AArch64_AM_ShiftExtendType;
} AArch64_AM_ShiftExtendType ;
/// getShiftName - Get the string encoding for the shift type.
static inline const char *AArch64_AM_getShiftExtendName(AArch64_AM_ShiftExtendType ST)
static inline const char *
AArch64_AM_getShiftExtendName(AArch64_AM_ShiftExtendType ST)
{
switch (ST) {
default: return NULL; // never reach
case AArch64_AM_LSL: return "lsl";
case AArch64_AM_LSR: return "lsr";
case AArch64_AM_ASR: return "asr";
case AArch64_AM_ROR: return "ror";
case AArch64_AM_MSL: return "msl";
case AArch64_AM_UXTB: return "uxtb";
case AArch64_AM_UXTH: return "uxth";
case AArch64_AM_UXTW: return "uxtw";
case AArch64_AM_UXTX: return "uxtx";
case AArch64_AM_SXTB: return "sxtb";
case AArch64_AM_SXTH: return "sxth";
case AArch64_AM_SXTW: return "sxtw";
case AArch64_AM_SXTX: return "sxtx";
default:
assert(0 && "unhandled shift type!");
case AArch64_AM_LSL:
return "lsl";
case AArch64_AM_LSR:
return "lsr";
case AArch64_AM_ASR:
return "asr";
case AArch64_AM_ROR:
return "ror";
case AArch64_AM_MSL:
return "msl";
case AArch64_AM_UXTB:
return "uxtb";
case AArch64_AM_UXTH:
return "uxth";
case AArch64_AM_UXTW:
return "uxtw";
case AArch64_AM_UXTX:
return "uxtx";
case AArch64_AM_SXTB:
return "sxtb";
case AArch64_AM_SXTH:
return "sxth";
case AArch64_AM_SXTW:
return "sxtw";
case AArch64_AM_SXTX:
return "sxtx";
}
return NULL;
}
/// getShiftType - Extract the shift type.
static inline AArch64_AM_ShiftExtendType AArch64_AM_getShiftType(unsigned Imm)
{
switch ((Imm >> 6) & 0x7) {
default: return AArch64_AM_InvalidShiftExtend;
case 0: return AArch64_AM_LSL;
case 1: return AArch64_AM_LSR;
case 2: return AArch64_AM_ASR;
case 3: return AArch64_AM_ROR;
case 4: return AArch64_AM_MSL;
default:
return AArch64_AM_InvalidShiftExtend;
case 0:
return AArch64_AM_LSL;
case 1:
return AArch64_AM_LSR;
case 2:
return AArch64_AM_ASR;
case 3:
return AArch64_AM_ROR;
case 4:
return AArch64_AM_MSL;
}
}
@ -83,27 +123,45 @@ static inline unsigned AArch64_AM_getShiftValue(unsigned Imm)
return Imm & 0x3f;
}
static inline unsigned AArch64_AM_getShifterImm(AArch64_AM_ShiftExtendType ST, unsigned Imm)
/// getShifterImm - Encode the shift type and amount:
/// imm: 6-bit shift amount
/// shifter: 000 ==> lsl
/// 001 ==> lsr
/// 010 ==> asr
/// 011 ==> ror
/// 100 ==> msl
/// {8-6} = shifter
/// {5-0} = imm
static inline unsigned AArch64_AM_getShifterImm(AArch64_AM_ShiftExtendType ST,
unsigned Imm)
{
// assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!");
unsigned STEnc = 0;
switch (ST) {
default: // llvm_unreachable("Invalid shift requested");
case AArch64_AM_LSL: STEnc = 0; break;
case AArch64_AM_LSR: STEnc = 1; break;
case AArch64_AM_ASR: STEnc = 2; break;
case AArch64_AM_ROR: STEnc = 3; break;
case AArch64_AM_MSL: STEnc = 4; break;
default:
assert(0 && "Invalid shift requested");
case AArch64_AM_LSL:
STEnc = 0;
break;
case AArch64_AM_LSR:
STEnc = 1;
break;
case AArch64_AM_ASR:
STEnc = 2;
break;
case AArch64_AM_ROR:
STEnc = 3;
break;
case AArch64_AM_MSL:
STEnc = 4;
break;
}
return (STEnc << 6) | (Imm & 0x3f);
}
//===----------------------------------------------------------------------===//
// Extends
//
/// getArithShiftValue - get the arithmetic shift value.
static inline unsigned AArch64_AM_getArithShiftValue(unsigned Imm)
{
@ -113,21 +171,31 @@ static inline unsigned AArch64_AM_getArithShiftValue(unsigned Imm)
/// getExtendType - Extract the extend type for operands of arithmetic ops.
static inline AArch64_AM_ShiftExtendType AArch64_AM_getExtendType(unsigned Imm)
{
// assert((Imm & 0x7) == Imm && "invalid immediate!");
switch (Imm) {
default: // llvm_unreachable("Compiler bug!");
case 0: return AArch64_AM_UXTB;
case 1: return AArch64_AM_UXTH;
case 2: return AArch64_AM_UXTW;
case 3: return AArch64_AM_UXTX;
case 4: return AArch64_AM_SXTB;
case 5: return AArch64_AM_SXTH;
case 6: return AArch64_AM_SXTW;
case 7: return AArch64_AM_SXTX;
default:
assert(0 && "Compiler bug!");
case 0:
return AArch64_AM_UXTB;
case 1:
return AArch64_AM_UXTH;
case 2:
return AArch64_AM_UXTW;
case 3:
return AArch64_AM_UXTX;
case 4:
return AArch64_AM_SXTB;
case 5:
return AArch64_AM_SXTH;
case 6:
return AArch64_AM_SXTW;
case 7:
return AArch64_AM_SXTX;
}
}
static inline AArch64_AM_ShiftExtendType AArch64_AM_getArithExtendType(unsigned Imm)
static inline AArch64_AM_ShiftExtendType
AArch64_AM_getArithExtendType(unsigned Imm)
{
return AArch64_AM_getExtendType((Imm >> 3) & 0x7);
}
@ -144,15 +212,32 @@ static inline AArch64_AM_ShiftExtendType AArch64_AM_getArithExtendType(unsigned
static inline unsigned AArch64_AM_getExtendEncoding(AArch64_AM_ShiftExtendType ET)
{
switch (ET) {
default: // llvm_unreachable("Invalid extend type requested");
case AArch64_AM_UXTB: return 0; break;
case AArch64_AM_UXTH: return 1; break;
case AArch64_AM_UXTW: return 2; break;
case AArch64_AM_UXTX: return 3; break;
case AArch64_AM_SXTB: return 4; break;
case AArch64_AM_SXTH: return 5; break;
case AArch64_AM_SXTW: return 6; break;
case AArch64_AM_SXTX: return 7; break;
default:
assert(0 && "Invalid extend type requested");
case AArch64_AM_UXTB:
return 0;
break;
case AArch64_AM_UXTH:
return 1;
break;
case AArch64_AM_UXTW:
return 2;
break;
case AArch64_AM_UXTX:
return 3;
break;
case AArch64_AM_SXTB:
return 4;
break;
case AArch64_AM_SXTH:
return 5;
break;
case AArch64_AM_SXTW:
return 6;
break;
case AArch64_AM_SXTX:
return 7;
break;
}
}
@ -161,9 +246,10 @@ static inline unsigned AArch64_AM_getExtendEncoding(AArch64_AM_ShiftExtendType E
/// imm: 3-bit extend amount
/// {5-3} = shifter
/// {2-0} = imm3
static inline unsigned AArch64_AM_getArithExtendImm(AArch64_AM_ShiftExtendType ET, unsigned Imm)
static inline unsigned
AArch64_AM_getArithExtendImm(AArch64_AM_ShiftExtendType ET, unsigned Imm)
{
// assert((Imm & 0x7) == Imm && "Illegal shifted immedate value!");
return (AArch64_AM_getExtendEncoding(ET) << 3) | (Imm & 0x7);
}
@ -176,38 +262,55 @@ static inline bool AArch64_AM_getMemDoShift(unsigned Imm)
/// getExtendType - Extract the extend type for the offset operand of
/// loads/stores.
static inline AArch64_AM_ShiftExtendType AArch64_AM_getMemExtendType(unsigned Imm)
static inline AArch64_AM_ShiftExtendType
AArch64_AM_getMemExtendType(unsigned Imm)
{
return AArch64_AM_getExtendType((Imm >> 1) & 0x7);
}
static inline uint64_t ror(uint64_t elt, unsigned size)
/// getExtendImm - Encode the extend type and amount for a load/store inst:
/// doshift: should the offset be scaled by the access size
/// shifter: 000 ==> uxtb
/// 001 ==> uxth
/// 010 ==> uxtw
/// 011 ==> uxtx
/// 100 ==> sxtb
/// 101 ==> sxth
/// 110 ==> sxtw
/// 111 ==> sxtx
/// {3-1} = shifter
/// {0} = doshift
static inline unsigned AArch64_AM_getMemExtendImm(AArch64_AM_ShiftExtendType ET,
bool DoShift)
{
return ((elt & 1) << (size-1)) | (elt >> 1);
return (AArch64_AM_getExtendEncoding(ET) << 1) | (unsigned)DoShift;
}
static inline uint64_t AArch64_AM_ror(uint64_t elt, unsigned size)
{
return ((elt & 1) << (size - 1)) | (elt >> 1);
}
/// processLogicalImmediate - Determine if an immediate value can be encoded
/// as the immediate operand of a logical instruction for the given register
/// size. If so, return true with "encoding" set to the encoded value in
/// the form N:immr:imms.
static inline bool AArch64_AM_processLogicalImmediate(uint64_t Imm, unsigned RegSize, uint64_t *Encoding)
static inline bool AArch64_AM_processLogicalImmediate(uint64_t Imm,
unsigned RegSize,
uint64_t *Encoding)
{
unsigned Size, Immr, N;
uint32_t CTO, I;
uint64_t Mask, NImms;
if (Imm == 0ULL || Imm == ~0ULL ||
(RegSize != 64 && (Imm >> RegSize != 0 || Imm == (~0ULL >> (64 - RegSize))))) {
(RegSize != 64 &&
(Imm >> RegSize != 0 || Imm == (~0ULL >> (64 - RegSize)))))
return false;
}
// First, determine the element size.
Size = RegSize;
do {
uint64_t Mask;
unsigned Size = RegSize;
do {
Size /= 2;
Mask = (1ULL << Size) - 1;
uint64_t Mask = (1ULL << Size) - 1;
if ((Imm & Mask) != ((Imm >> Size) & Mask)) {
Size *= 2;
break;
@ -215,121 +318,111 @@ static inline bool AArch64_AM_processLogicalImmediate(uint64_t Imm, unsigned Reg
} while (Size > 2);
// Second, determine the rotation to make the element be: 0^m 1^n.
Mask = ((uint64_t)-1LL) >> (64 - Size);
uint32_t CTO, I;
uint64_t Mask = ((uint64_t)-1LL) >> (64 - Size);
Imm &= Mask;
if (isShiftedMask_64(Imm)) {
I = CountTrailingZeros_32(Imm);
// assert(I < 64 && "undefined behavior");
CTO = CountTrailingOnes_32(Imm >> I);
} else {
unsigned CLO;
I = CountTrailingZeros_64(Imm);
CTO = CountTrailingOnes_64(Imm >> I);
} else {
Imm |= ~Mask;
if (!isShiftedMask_64(~Imm))
return false;
CLO = CountLeadingOnes_32(Imm);
unsigned CLO = CountLeadingOnes_64(Imm);
I = 64 - CLO;
CTO = CLO + CountTrailingOnes_32(Imm) - (64 - Size);
CTO = CLO + CountTrailingOnes_64(Imm) - (64 - Size);
}
// Encode in Immr the number of RORs it would take to get *from* 0^m 1^n
// to our target value, where I is the number of RORs to go the opposite
// direction.
// assert(Size > I && "I should be smaller than element size");
Immr = (Size - I) & (Size - 1);
unsigned Immr = (Size - I) & (Size - 1);
// If size has a 1 in the n'th bit, create a value that has zeroes in
// bits [0, n] and ones above that.
NImms = ~(Size-1) << 1;
uint64_t NImms = ~(Size - 1) << 1;
// Or the CTO value into the low bits, which must be below the Nth bit
// bit mentioned above.
NImms |= (CTO-1);
NImms |= (CTO - 1);
// Extract the seventh bit and toggle it to create the N field.
N = ((NImms >> 6) & 1) ^ 1;
unsigned N = ((NImms >> 6) & 1) ^ 1;
*Encoding = (N << 12) | (Immr << 6) | (NImms & 0x3f);
return true;
}
/// isLogicalImmediate - Return true if the immediate is valid for a logical
/// immediate instruction of the given register size. Return false otherwise.
static inline bool isLogicalImmediate(uint64_t imm, unsigned regSize)
static inline bool AArch64_AM_isLogicalImmediate(uint64_t imm, unsigned regSize)
{
uint64_t encoding;
uint64_t encoding = 0;
return AArch64_AM_processLogicalImmediate(imm, regSize, &encoding);
}
/// encodeLogicalImmediate - Return the encoded immediate value for a logical
/// immediate instruction of the given register size.
static inline uint64_t AArch64_AM_encodeLogicalImmediate(uint64_t imm, unsigned regSize)
static inline uint64_t AArch64_AM_encodeLogicalImmediate(uint64_t imm,
unsigned regSize)
{
uint64_t encoding = 0;
bool res = AArch64_AM_processLogicalImmediate(imm, regSize, &encoding);
// assert(res && "invalid logical immediate");
(void)res;
(void)res;
return encoding;
}
/// decodeLogicalImmediate - Decode a logical immediate value in the form
/// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the
/// integer value it represents with regSize bits.
static inline uint64_t AArch64_AM_decodeLogicalImmediate(uint64_t val, unsigned regSize)
static inline uint64_t AArch64_AM_decodeLogicalImmediate(uint64_t val,
unsigned regSize)
{
// Extract the N, imms, and immr fields.
unsigned N = (val >> 12) & 1;
unsigned immr = (val >> 6) & 0x3f;
unsigned imms = val & 0x3f;
unsigned i, size, R, S;
uint64_t pattern;
// assert((regSize == 64 || N == 0) && "undefined logical immediate encoding");
int len = 31 - CountLeadingZeros_32((N << 6) | (~imms & 0x3f));
int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
// assert(len >= 0 && "undefined logical immediate encoding");
size = (1 << len);
R = immr & (size - 1);
S = imms & (size - 1);
unsigned size = (1 << len);
unsigned R = immr & (size - 1);
unsigned S = imms & (size - 1);
// assert(S != size - 1 && "undefined logical immediate encoding");
pattern = (1ULL << (S + 1)) - 1;
for (i = 0; i < R; ++i)
pattern = ror(pattern, size);
uint64_t pattern = (1ULL << (S + 1)) - 1;
for (unsigned i = 0; i < R; ++i)
pattern = AArch64_AM_ror(pattern, size);
// Replicate the pattern to fill the regSize.
while (size != regSize) {
pattern |= (pattern << size);
size *= 2;
}
return pattern;
}
/// isValidDecodeLogicalImmediate - Check to see if the logical immediate value
/// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits)
/// is a valid encoding for an integer value with regSize bits.
static inline bool AArch64_AM_isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)
static inline bool AArch64_AM_isValidDecodeLogicalImmediate(uint64_t val,
unsigned regSize)
{
unsigned size, S;
int len;
// Extract the N and imms fields needed for checking.
unsigned N = (val >> 12) & 1;
unsigned imms = val & 0x3f;
if (regSize == 32 && N != 0) // undefined logical immediate encoding
return false;
len = 31 - CountLeadingZeros_32((N << 6) | (~imms & 0x3f));
if (len < 0) // undefined logical immediate encoding
int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
if (len < 0) // undefined logical immediate encoding
return false;
size = (1 << len);
S = imms & (size - 1);
unsigned size = (1 << len);
unsigned S = imms & (size - 1);
if (S == size - 1) // undefined logical immediate encoding
return false;
@ -342,39 +435,33 @@ static inline bool AArch64_AM_isValidDecodeLogicalImmediate(uint64_t val, unsign
static inline float AArch64_AM_getFPImmFloat(unsigned Imm)
{
// We expect an 8-bit binary encoding of a floating-point number here.
union {
uint32_t I;
float F;
} FPUnion;
uint8_t Sign = (Imm >> 7) & 0x1;
uint8_t Exp = (Imm >> 4) & 0x7;
uint8_t Mantissa = Imm & 0xf;
// 8-bit FP iEEEE Float Encoding
// 8-bit FP IEEE Float Encoding
// abcd efgh aBbbbbbc defgh000 00000000 00000000
//
// where B = NOT(b);
FPUnion.I = 0;
FPUnion.I |= ((uint32_t)Sign) << 31;
FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
FPUnion.I |= (Exp & 0x3) << 23;
FPUnion.I |= Mantissa << 19;
return FPUnion.F;
uint32_t I = 0;
I |= Sign << 31;
I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
I |= (Exp & 0x3) << 23;
I |= Mantissa << 19;
return BitsToFloat(I);
}
//===--------------------------------------------------------------------===//
// AdvSIMD Modified Immediates
//===--------------------------------------------------------------------===//
// 0x00 0x00 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh
static inline bool AArch64_AM_isAdvSIMDModImmType1(uint64_t Imm)
{
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
((Imm & 0xffffff00ffffff00ULL) == 0);
((Imm & 0xffffff00ffffff00ULL) == 0);
}
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType1(uint64_t Imm)
@ -385,7 +472,6 @@ static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType1(uint64_t Imm)
static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType1(uint8_t Imm)
{
uint64_t EncVal = Imm;
return (EncVal << 32) | EncVal;
}
@ -393,7 +479,7 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType1(uint8_t Imm)
static inline bool AArch64_AM_isAdvSIMDModImmType2(uint64_t Imm)
{
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
((Imm & 0xffff00ffffff00ffULL) == 0);
((Imm & 0xffff00ffffff00ffULL) == 0);
}
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType2(uint64_t Imm)
@ -411,7 +497,7 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType2(uint8_t Imm)
static inline bool AArch64_AM_isAdvSIMDModImmType3(uint64_t Imm)
{
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
((Imm & 0xff00ffffff00ffffULL) == 0);
((Imm & 0xff00ffffff00ffffULL) == 0);
}
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType3(uint64_t Imm)
@ -429,7 +515,7 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType3(uint8_t Imm)
static inline bool AArch64_AM_isAdvSIMDModImmType4(uint64_t Imm)
{
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
((Imm & 0x00ffffff00ffffffULL) == 0);
((Imm & 0x00ffffff00ffffffULL) == 0);
}
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType4(uint64_t Imm)
@ -447,8 +533,8 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType4(uint8_t Imm)
static inline bool AArch64_AM_isAdvSIMDModImmType5(uint64_t Imm)
{
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
(((Imm & 0x00ff0000ULL) >> 16) == (Imm & 0x000000ffULL)) &&
((Imm & 0xff00ff00ff00ff00ULL) == 0);
(((Imm & 0x00ff0000ULL) >> 16) == (Imm & 0x000000ffULL)) &&
((Imm & 0xff00ff00ff00ff00ULL) == 0);
}
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType5(uint64_t Imm)
@ -466,8 +552,8 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType5(uint8_t Imm)
static inline bool AArch64_AM_isAdvSIMDModImmType6(uint64_t Imm)
{
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
(((Imm & 0xff000000ULL) >> 16) == (Imm & 0x0000ff00ULL)) &&
((Imm & 0x00ff00ff00ff00ffULL) == 0);
(((Imm & 0xff000000ULL) >> 16) == (Imm & 0x0000ff00ULL)) &&
((Imm & 0x00ff00ff00ff00ffULL) == 0);
}
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType6(uint64_t Imm)
@ -485,7 +571,7 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType6(uint8_t Imm)
static inline bool AArch64_AM_isAdvSIMDModImmType7(uint64_t Imm)
{
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
((Imm & 0xffff00ffffff00ffULL) == 0x000000ff000000ffULL);
((Imm & 0xffff00ffffff00ffULL) == 0x000000ff000000ffULL);
}
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType7(uint64_t Imm)
@ -503,7 +589,7 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType7(uint8_t Imm)
static inline bool AArch64_AM_isAdvSIMDModImmType8(uint64_t Imm)
{
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
((Imm & 0xff00ffffff00ffffULL) == 0x0000ffff0000ffffULL);
((Imm & 0xff00ffffff00ffffULL) == 0x0000ffff0000ffffULL);
}
static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType8(uint8_t Imm)
@ -521,8 +607,8 @@ static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType8(uint64_t Imm)
static inline bool AArch64_AM_isAdvSIMDModImmType9(uint64_t Imm)
{
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
((Imm >> 48) == (Imm & 0x0000ffffULL)) &&
((Imm >> 56) == (Imm & 0x000000ffULL));
((Imm >> 48) == (Imm & 0x0000ffffULL)) &&
((Imm >> 56) == (Imm & 0x000000ffULL));
}
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType9(uint64_t Imm)
@ -536,7 +622,6 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType9(uint8_t Imm)
EncVal |= (EncVal << 8);
EncVal |= (EncVal << 16);
EncVal |= (EncVal << 32);
return EncVal;
}
@ -554,13 +639,13 @@ static inline bool AArch64_AM_isAdvSIMDModImmType10(uint64_t Imm)
uint64_t ByteH = Imm & 0x00000000000000ffULL;
return (ByteA == 0ULL || ByteA == 0xff00000000000000ULL) &&
(ByteB == 0ULL || ByteB == 0x00ff000000000000ULL) &&
(ByteC == 0ULL || ByteC == 0x0000ff0000000000ULL) &&
(ByteD == 0ULL || ByteD == 0x000000ff00000000ULL) &&
(ByteE == 0ULL || ByteE == 0x00000000ff000000ULL) &&
(ByteF == 0ULL || ByteF == 0x0000000000ff0000ULL) &&
(ByteG == 0ULL || ByteG == 0x000000000000ff00ULL) &&
(ByteH == 0ULL || ByteH == 0x00000000000000ffULL);
(ByteB == 0ULL || ByteB == 0x00ff000000000000ULL) &&
(ByteC == 0ULL || ByteC == 0x0000ff0000000000ULL) &&
(ByteD == 0ULL || ByteD == 0x000000ff00000000ULL) &&
(ByteE == 0ULL || ByteE == 0x00000000ff000000ULL) &&
(ByteF == 0ULL || ByteF == 0x0000000000ff0000ULL) &&
(ByteG == 0ULL || ByteG == 0x000000000000ff00ULL) &&
(ByteH == 0ULL || ByteH == 0x00000000000000ffULL);
}
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType10(uint64_t Imm)
@ -575,7 +660,6 @@ static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType10(uint64_t Imm)
uint8_t BitH = (Imm & 0x00000000000000ffULL) != 0;
uint8_t EncVal = BitA;
EncVal <<= 1;
EncVal |= BitB;
EncVal <<= 1;
@ -590,38 +674,28 @@ static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType10(uint64_t Imm)
EncVal |= BitG;
EncVal <<= 1;
EncVal |= BitH;
return EncVal;
}
static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType10(uint8_t Imm)
{
uint64_t EncVal = 0;
if (Imm & 0x80)
EncVal |= 0xff00000000000000ULL;
if (Imm & 0x40)
EncVal |= 0x00ff000000000000ULL;
if (Imm & 0x20)
EncVal |= 0x0000ff0000000000ULL;
if (Imm & 0x10)
EncVal |= 0x000000ff00000000ULL;
if (Imm & 0x08)
EncVal |= 0x00000000ff000000ULL;
if (Imm & 0x04)
EncVal |= 0x0000000000ff0000ULL;
if (Imm & 0x02)
EncVal |= 0x000000000000ff00ULL;
if (Imm & 0x01)
EncVal |= 0x00000000000000ffULL;
return EncVal;
}
@ -629,10 +703,9 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType10(uint8_t Imm)
static inline bool AArch64_AM_isAdvSIMDModImmType11(uint64_t Imm)
{
uint64_t BString = (Imm & 0x7E000000ULL) >> 25;
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
(BString == 0x1f || BString == 0x20) &&
((Imm & 0x0007ffff0007ffffULL) == 0);
(BString == 0x1f || BString == 0x20) &&
((Imm & 0x0007ffff0007ffffULL) == 0);
}
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType11(uint64_t Imm)
@ -661,40 +734,30 @@ static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType11(uint64_t Imm)
EncVal |= BitG;
EncVal <<= 1;
EncVal |= BitH;
return EncVal;
}
static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType11(uint8_t Imm)
{
uint64_t EncVal = 0;
if (Imm & 0x80)
EncVal |= 0x80000000ULL;
if (Imm & 0x40)
EncVal |= 0x3e000000ULL;
else
EncVal |= 0x40000000ULL;
if (Imm & 0x20)
EncVal |= 0x01000000ULL;
if (Imm & 0x10)
EncVal |= 0x00800000ULL;
if (Imm & 0x08)
EncVal |= 0x00400000ULL;
if (Imm & 0x04)
EncVal |= 0x00200000ULL;
if (Imm & 0x02)
EncVal |= 0x00100000ULL;
if (Imm & 0x01)
EncVal |= 0x00080000ULL;
return (EncVal << 32) | EncVal;
}
@ -703,7 +766,7 @@ static inline bool AArch64_AM_isAdvSIMDModImmType12(uint64_t Imm)
{
uint64_t BString = (Imm & 0x7fc0000000000000ULL) >> 54;
return ((BString == 0xff || BString == 0x100) &&
((Imm & 0x0000ffffffffffffULL) == 0));
((Imm & 0x0000ffffffffffffULL) == 0));
}
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType12(uint64_t Imm)
@ -732,7 +795,6 @@ static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType12(uint64_t Imm)
EncVal |= BitG;
EncVal <<= 1;
EncVal |= BitH;
return EncVal;
}
@ -741,93 +803,53 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType12(uint8_t Imm)
uint64_t EncVal = 0;
if (Imm & 0x80)
EncVal |= 0x8000000000000000ULL;
if (Imm & 0x40)
EncVal |= 0x3fc0000000000000ULL;
else
EncVal |= 0x4000000000000000ULL;
if (Imm & 0x20)
EncVal |= 0x0020000000000000ULL;
if (Imm & 0x10)
EncVal |= 0x0010000000000000ULL;
if (Imm & 0x08)
EncVal |= 0x0008000000000000ULL;
if (Imm & 0x04)
EncVal |= 0x0004000000000000ULL;
if (Imm & 0x02)
EncVal |= 0x0002000000000000ULL;
if (Imm & 0x01)
EncVal |= 0x0001000000000000ULL;
return (EncVal << 32) | EncVal;
}
#if __GNUC__ && defined( __has_warning )
# if __has_warning( "-Wmaybe-uninitialized" )
# define WARNING_SUPRESSED
# pragma GCC diagnostic push
# pragma GCC diagnostic ignored "-Wmaybe-uninitialized"
# endif
#endif
/// Returns true if Imm is the concatenation of a repeating pattern of type T.
static inline bool AArch64_AM_isSVEMaskOfIdenticalElements8(int64_t Imm)
{
#define _VECSIZE (sizeof(int64_t)/sizeof(int8_t))
unsigned int i;
union {
int64_t Whole;
int8_t Parts[_VECSIZE];
} Vec;
Vec.Whole = Imm;
for(i = 1; i < _VECSIZE; i++) {
if (Vec.Parts[i] != Vec.Parts[0])
return false;
#define DEFINE_isSVEMaskOfIdenticalElements(T) \
static inline bool CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, T)(int64_t Imm) \
{ \
T *Parts = (T *)(&(Imm)); \
for (int i = 0; i < (sizeof(int64_t) / sizeof(T)); i++) { \
if (Parts[i] != Parts[0]) \
return false; \
} \
return true; \
}
#undef _VECSIZE
DEFINE_isSVEMaskOfIdenticalElements(int8_t);
DEFINE_isSVEMaskOfIdenticalElements(int16_t);
DEFINE_isSVEMaskOfIdenticalElements(int32_t);
DEFINE_isSVEMaskOfIdenticalElements(int64_t);
return true;
}
static inline bool AArch64_AM_isSVEMaskOfIdenticalElements16(int64_t Imm)
{
#define _VECSIZE (sizeof(int64_t)/sizeof(int16_t))
unsigned int i;
union {
int64_t Whole;
int16_t Parts[_VECSIZE];
} Vec;
Vec.Whole = Imm;
for(i = 1; i < _VECSIZE; i++) {
if (Vec.Parts[i] != Vec.Parts[0])
return false;
}
#undef _VECSIZE
return true;
}
static inline bool AArch64_AM_isSVEMaskOfIdenticalElements32(int64_t Imm)
{
#define _VECSIZE (sizeof(int64_t)/sizeof(int32_t))
unsigned int i;
union {
int64_t Whole;
int32_t Parts[_VECSIZE];
} Vec;
Vec.Whole = Imm;
for(i = 1; i < _VECSIZE; i++) {
if (Vec.Parts[i] != Vec.Parts[0])
return false;
}
#undef _VECSIZE
return true;
}
#ifdef WARNING_SUPRESSED
#pragma GCC diagnostic pop
#endif
static inline bool AArch64_AM_isSVEMaskOfIdenticalElements64(int64_t Imm)
{
@ -866,45 +888,39 @@ static inline bool isSVECpyImm64(int64_t Imm)
}
/// Return true if Imm is valid for DUPM and has no single CPY/DUP equivalent.
static inline bool AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(int64_t Imm)
static inline bool
AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(int64_t Imm)
{
union {
int64_t D;
int32_t S[2];
int16_t H[4];
int8_t B[8];
} Vec = {Imm};
if (isSVECpyImm64(Vec.D))
if (isSVECpyImm64(Imm))
return false;
if (AArch64_AM_isSVEMaskOfIdenticalElements32(Imm) &&
isSVECpyImm32(Vec.S[0]))
return false;
int32_t *S = (int32_t *)(&(Imm)); // arr len = 2
int16_t *H = (int16_t *)(&(Imm)); // arr len = 4
int8_t *B = (int8_t *)(&(Imm)); // arr len = 8
if (AArch64_AM_isSVEMaskOfIdenticalElements16(Imm) &&
isSVECpyImm16(Vec.H[0]))
if (CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, int32_t)(Imm) &&
isSVECpyImm32(S[0]))
return false;
if (AArch64_AM_isSVEMaskOfIdenticalElements8(Imm) &&
isSVECpyImm8(Vec.B[0]))
if (CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, int16_t)(Imm) &&
isSVECpyImm16(H[0]))
return false;
return isLogicalImmediate(Vec.D, 64);
if (CONCAT(AArch64_AM_isSVEMaskOfIdenticalElements, int8_t)(Imm) &&
isSVECpyImm8(B[0]))
return false;
return AArch64_AM_isLogicalImmediate(Imm, 64);
}
inline static bool isAnyMOVZMovAlias(uint64_t Value, int RegWidth)
inline static bool AArch64_AM_isAnyMOVZMovAlias(uint64_t Value, int RegWidth)
{
int Shift;
for (Shift = 0; Shift <= RegWidth - 16; Shift += 16)
for (int Shift = 0; Shift <= RegWidth - 16; Shift += 16)
if ((Value & ~(0xffffULL << Shift)) == 0)
return true;
return false;
}
inline static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth)
inline static bool AArch64_AM_isMOVZMovAlias(uint64_t Value, int Shift,
int RegWidth)
{
if (RegWidth == 32)
Value &= 0xffffffffULL;
@ -916,22 +932,23 @@ inline static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth)
return (Value & ~(0xffffULL << Shift)) == 0;
}
inline static bool AArch64_AM_isMOVNMovAlias(uint64_t Value, int Shift, int RegWidth)
inline static bool AArch64_AM_isMOVNMovAlias(uint64_t Value, int Shift,
int RegWidth)
{
// MOVZ takes precedence over MOVN.
if (isAnyMOVZMovAlias(Value, RegWidth))
if (AArch64_AM_isAnyMOVZMovAlias(Value, RegWidth))
return false;
Value = ~Value;
if (RegWidth == 32)
Value &= 0xffffffffULL;
return isMOVZMovAlias(Value, Shift, RegWidth);
return AArch64_AM_isMOVZMovAlias(Value, Shift, RegWidth);
}
inline static bool AArch64_AM_isAnyMOVWMovAlias(uint64_t Value, int RegWidth)
{
if (isAnyMOVZMovAlias(Value, RegWidth))
if (AArch64_AM_isAnyMOVZMovAlias(Value, RegWidth))
return true;
// It's not a MOVZ, but it might be a MOVN.
@ -939,7 +956,11 @@ inline static bool AArch64_AM_isAnyMOVWMovAlias(uint64_t Value, int RegWidth)
if (RegWidth == 32)
Value &= 0xffffffffULL;
return isAnyMOVZMovAlias(Value, RegWidth);
return AArch64_AM_isAnyMOVZMovAlias(Value, RegWidth);
}
// end namespace AArch64_AM
// end namespace llvm
#endif

132
arch/AArch64/AArch64BaseInfo.c
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@ -1,34 +1,122 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file provides basic encoding and assembly information for AArch64.
//
//===----------------------------------------------------------------------===//
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
#ifdef CAPSTONE_HAS_ARM64
#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)
#pragma warning(disable:4996) // disable MSVC's warning on strcpy()
#pragma warning(disable:28719) // disable MSVC's warning on strcpy()
#endif
#include "../../utils.h"
#include <capstone/platform.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "AArch64BaseInfo.h"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
#define GET_AT_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_AT_IMPL
#define GET_DBNXS_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_DBNXS_IMPL
#define GET_DB_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_DB_IMPL
#define GET_DC_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_DC_IMPL
#define GET_IC_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_IC_IMPL
#define GET_ISB_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_ISB_IMPL
#define GET_TSB_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_TSB_IMPL
#define GET_PRCTX_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_PRCTX_IMPL
#define GET_PRFM_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_PRFM_IMPL
#define GET_SVEPRFM_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_SVEPRFM_IMPL
#define GET_RPRFM_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_RPRFM_IMPL
// namespace AArch64RPRFM
// namespace llvm
#define GET_SVEPREDPAT_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_SVEPREDPAT_IMPL
#define GET_SVEVECLENSPECIFIER_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_SVEVECLENSPECIFIER_IMPL
// namespace AArch64SVEVecLenSpecifier
// namespace llvm
#define GET_EXACTFPIMM_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_EXACTFPIMM_IMPL
#define GET_PSTATEIMM0_15_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_PSTATEIMM0_15_IMPL
#define GET_PSTATEIMM0_1_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_PSTATEIMM0_1_IMPL
#define GET_PSB_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_PSB_IMPL
#define GET_BTI_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_BTI_IMPL
#define SysReg AArch64SysReg_SysReg
#define GET_SYSREG_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_SYSREG_IMPL
#undef SysReg
// return a string representing the number X
// NOTE: result must be big enough to contain the data
@ -69,9 +157,15 @@ void AArch64SysReg_genericRegisterString(uint32_t Bits, char *result)
utostr(CRn, false, CRnStr);
utostr(CRm, false, CRmStr);
dummy = cs_snprintf(result, 128, "s%s_%s_c%s_c%s_%s",
dummy = cs_snprintf(result, AARCH64_GRS_LEN, "s%s_%s_c%s_c%s_%s",
Op0Str, Op1Str, CRnStr, CRmStr, Op2Str);
(void)dummy;
}
#endif
#define GET_TLBITable_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_TLBITable_IMPL
#define GET_SVCR_IMPL
#include "AArch64GenSystemOperands.inc"
#undef GET_SVCR_IMPL

1303
arch/AArch64/AArch64BaseInfo.h
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2965
arch/AArch64/AArch64Disassembler.c
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18
arch/AArch64/AArch64Disassembler.h
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@ -1,18 +0,0 @@
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
#ifndef CS_AARCH64_DISASSEMBLER_H
#define CS_AARCH64_DISASSEMBLER_H
#include "capstone/capstone.h"
#include "../../MCRegisterInfo.h"
#include "../../MCInst.h"
void AArch64_init(MCRegisterInfo *MRI);
bool AArch64_getInstruction(csh ud, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address, void *info);
uint64_t AArch64_getFeatureBits(int feature);
#endif

24
arch/AArch64/AArch64DisassemblerExtension.c Normal file
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@ -0,0 +1,24 @@
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
/* Rot127 <unisono@quyllur.org>, 2022-2023 */
#include "AArch64DisassemblerExtension.h"
#include "AArch64BaseInfo.h"
bool AArch64_getFeatureBits(unsigned int mode, unsigned int feature)
{
// we support everything
return true;
}
/// Tests a NULL terminated array of features if they are enabled.
bool AArch64_testFeatureList(unsigned int mode, const unsigned int *features)
{
int i = 0;
while (features[i]) {
if (!AArch64_getFeatureBits(mode, features[i]))
return false;
++i;
}
return true;
}

19
arch/AArch64/AArch64DisassemblerExtension.h Normal file
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@ -0,0 +1,19 @@
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
/* Rot127 <unisono@quyllur.org>, 2022-2023 */
#ifndef CS_AARCH64_DISASSEMBLER_EXTENSION_H
#define CS_AARCH64_DISASSEMBLER_EXTENSION_H
#include "../../MCDisassembler.h"
#include "../../MCRegisterInfo.h"
#include "../../MathExtras.h"
#include "../../cs_priv.h"
#include "AArch64AddressingModes.h"
#include "capstone/aarch64.h"
#include "capstone/capstone.h"
bool AArch64_getFeatureBits(unsigned int mode, unsigned int feature);
bool AArch64_testFeatureList(unsigned int mode, const unsigned int *features);
#endif // CS_AARCH64_DISASSEMBLER_EXTENSION_H

40719
arch/AArch64/AArch64GenAsmWriter.inc
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368
arch/AArch64/AArch64GenCSAliasMnemMap.inc Normal file
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@ -0,0 +1,368 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
{ AArch64_INS_ALIAS_LDAPUR, "ldapur" },
{ AArch64_INS_ALIAS_STLLRB, "stllrb" },
{ AArch64_INS_ALIAS_STLLRH, "stllrh" },
{ AArch64_INS_ALIAS_STLLR, "stllr" },
{ AArch64_INS_ALIAS_STLRB, "stlrb" },
{ AArch64_INS_ALIAS_STLRH, "stlrh" },
{ AArch64_INS_ALIAS_STLR, "stlr" },
{ AArch64_INS_ALIAS_STLUR, "stlur" },
{ AArch64_INS_ALIAS_EOR, "eor" },
{ AArch64_INS_ALIAS_AND, "and" },
{ AArch64_INS_ALIAS_MOV, "mov" },
{ AArch64_INS_ALIAS_LD1B, "ld1b" },
{ AArch64_INS_ALIAS_LD1SW, "ld1sw" },
{ AArch64_INS_ALIAS_LD1H, "ld1h" },
{ AArch64_INS_ALIAS_LD1SH, "ld1sh" },
{ AArch64_INS_ALIAS_LD1W, "ld1w" },
{ AArch64_INS_ALIAS_LD1SB, "ld1sb" },
{ AArch64_INS_ALIAS_LD1D, "ld1d" },
{ AArch64_INS_ALIAS_LD1RB, "ld1rb" },
{ AArch64_INS_ALIAS_LD1RSW, "ld1rsw" },
{ AArch64_INS_ALIAS_LD1RH, "ld1rh" },
{ AArch64_INS_ALIAS_LD1RSH, "ld1rsh" },
{ AArch64_INS_ALIAS_LD1RW, "ld1rw" },
{ AArch64_INS_ALIAS_LD1RSB, "ld1rsb" },
{ AArch64_INS_ALIAS_LD1RD, "ld1rd" },
{ AArch64_INS_ALIAS_LD1RQH, "ld1rqh" },
{ AArch64_INS_ALIAS_LD1RQW, "ld1rqw" },
{ AArch64_INS_ALIAS_LD1RQD, "ld1rqd" },
{ AArch64_INS_ALIAS_LDNF1B, "ldnf1b" },
{ AArch64_INS_ALIAS_LDNF1SW, "ldnf1sw" },
{ AArch64_INS_ALIAS_LDNF1H, "ldnf1h" },
{ AArch64_INS_ALIAS_LDNF1SH, "ldnf1sh" },
{ AArch64_INS_ALIAS_LDNF1W, "ldnf1w" },
{ AArch64_INS_ALIAS_LDNF1SB, "ldnf1sb" },
{ AArch64_INS_ALIAS_LDNF1D, "ldnf1d" },
{ AArch64_INS_ALIAS_LDFF1B, "ldff1b" },
{ AArch64_INS_ALIAS_LDFF1SW, "ldff1sw" },
{ AArch64_INS_ALIAS_LDFF1H, "ldff1h" },
{ AArch64_INS_ALIAS_LDFF1SH, "ldff1sh" },
{ AArch64_INS_ALIAS_LDFF1W, "ldff1w" },
{ AArch64_INS_ALIAS_LDFF1SB, "ldff1sb" },
{ AArch64_INS_ALIAS_LDFF1D, "ldff1d" },
{ AArch64_INS_ALIAS_LD3B, "ld3b" },
{ AArch64_INS_ALIAS_LD4B, "ld4b" },
{ AArch64_INS_ALIAS_LD2H, "ld2h" },
{ AArch64_INS_ALIAS_LD3H, "ld3h" },
{ AArch64_INS_ALIAS_LD4H, "ld4h" },
{ AArch64_INS_ALIAS_LD2W, "ld2w" },
{ AArch64_INS_ALIAS_LD3W, "ld3w" },
{ AArch64_INS_ALIAS_LD4W, "ld4w" },
{ AArch64_INS_ALIAS_LD2D, "ld2d" },
{ AArch64_INS_ALIAS_LD3D, "ld3d" },
{ AArch64_INS_ALIAS_LD4D, "ld4d" },
{ AArch64_INS_ALIAS_LD2Q, "ld2q" },
{ AArch64_INS_ALIAS_LD3Q, "ld3q" },
{ AArch64_INS_ALIAS_LD4Q, "ld4q" },
{ AArch64_INS_ALIAS_LDNT1H, "ldnt1h" },
{ AArch64_INS_ALIAS_LDNT1W, "ldnt1w" },
{ AArch64_INS_ALIAS_LDNT1D, "ldnt1d" },
{ AArch64_INS_ALIAS_ST1B, "st1b" },
{ AArch64_INS_ALIAS_ST1H, "st1h" },
{ AArch64_INS_ALIAS_ST1W, "st1w" },
{ AArch64_INS_ALIAS_ST1D, "st1d" },
{ AArch64_INS_ALIAS_ST3B, "st3b" },
{ AArch64_INS_ALIAS_ST4B, "st4b" },
{ AArch64_INS_ALIAS_ST2H, "st2h" },
{ AArch64_INS_ALIAS_ST3H, "st3h" },
{ AArch64_INS_ALIAS_ST4H, "st4h" },
{ AArch64_INS_ALIAS_ST2W, "st2w" },
{ AArch64_INS_ALIAS_ST3W, "st3w" },
{ AArch64_INS_ALIAS_ST4W, "st4w" },
{ AArch64_INS_ALIAS_ST2D, "st2d" },
{ AArch64_INS_ALIAS_ST3D, "st3d" },
{ AArch64_INS_ALIAS_ST4D, "st4d" },
{ AArch64_INS_ALIAS_ST3Q, "st3q" },
{ AArch64_INS_ALIAS_ST4Q, "st4q" },
{ AArch64_INS_ALIAS_STNT1H, "stnt1h" },
{ AArch64_INS_ALIAS_STNT1W, "stnt1w" },
{ AArch64_INS_ALIAS_STNT1D, "stnt1d" },
{ AArch64_INS_ALIAS_PRFH, "prfh" },
{ AArch64_INS_ALIAS_PRFW, "prfw" },
{ AArch64_INS_ALIAS_PRFD, "prfd" },
{ AArch64_INS_ALIAS_CNTH, "cnth" },
{ AArch64_INS_ALIAS_CNTW, "cntw" },
{ AArch64_INS_ALIAS_CNTD, "cntd" },
{ AArch64_INS_ALIAS_DECB, "decb" },
{ AArch64_INS_ALIAS_INCH, "inch" },
{ AArch64_INS_ALIAS_DECH, "dech" },
{ AArch64_INS_ALIAS_INCW, "incw" },
{ AArch64_INS_ALIAS_DECW, "decw" },
{ AArch64_INS_ALIAS_INCD, "incd" },
{ AArch64_INS_ALIAS_DECD, "decd" },
{ AArch64_INS_ALIAS_SQDECB, "sqdecb" },
{ AArch64_INS_ALIAS_UQDECB, "uqdecb" },
{ AArch64_INS_ALIAS_UQINCB, "uqincb" },
{ AArch64_INS_ALIAS_SQINCH, "sqinch" },
{ AArch64_INS_ALIAS_UQINCH, "uqinch" },
{ AArch64_INS_ALIAS_SQDECH, "sqdech" },
{ AArch64_INS_ALIAS_UQDECH, "uqdech" },
{ AArch64_INS_ALIAS_SQINCW, "sqincw" },
{ AArch64_INS_ALIAS_UQINCW, "uqincw" },
{ AArch64_INS_ALIAS_SQDECW, "sqdecw" },
{ AArch64_INS_ALIAS_UQDECW, "uqdecw" },
{ AArch64_INS_ALIAS_SQINCD, "sqincd" },
{ AArch64_INS_ALIAS_UQINCD, "uqincd" },
{ AArch64_INS_ALIAS_SQDECD, "sqdecd" },
{ AArch64_INS_ALIAS_UQDECD, "uqdecd" },
{ AArch64_INS_ALIAS_MOVS, "movs" },
{ AArch64_INS_ALIAS_NOT, "not" },
{ AArch64_INS_ALIAS_NOTS, "nots" },
{ AArch64_INS_ALIAS_LD1ROH, "ld1roh" },
{ AArch64_INS_ALIAS_LD1ROW, "ld1row" },
{ AArch64_INS_ALIAS_LD1ROD, "ld1rod" },
{ AArch64_INS_ALIAS_BCAX, "bcax" },
{ AArch64_INS_ALIAS_BSL, "bsl" },
{ AArch64_INS_ALIAS_BSL1N, "bsl1n" },
{ AArch64_INS_ALIAS_BSL2N, "bsl2n" },
{ AArch64_INS_ALIAS_NBSL, "nbsl" },
{ AArch64_INS_ALIAS_LDNT1B, "ldnt1b" },
{ AArch64_INS_ALIAS_LDNT1SH, "ldnt1sh" },
{ AArch64_INS_ALIAS_LDNT1SW, "ldnt1sw" },
{ AArch64_INS_ALIAS_STNT1B, "stnt1b" },
{ AArch64_INS_ALIAS_LD1Q, "ld1q" },
{ AArch64_INS_ALIAS_ST1Q, "st1q" },
{ AArch64_INS_ALIAS_SMSTART, "smstart" },
{ AArch64_INS_ALIAS_SMSTOP, "smstop" },
{ AArch64_INS_ALIAS_LDRAA, "ldraa" },
{ AArch64_INS_ALIAS_ADD, "add" },
{ AArch64_INS_ALIAS_CMN, "cmn" },
{ AArch64_INS_ALIAS_ADDS, "adds" },
{ AArch64_INS_ALIAS_ANDS, "ands" },
{ AArch64_INS_ALIAS_LDR, "ldr" },
{ AArch64_INS_ALIAS_STR, "str" },
{ AArch64_INS_ALIAS_LDRB, "ldrb" },
{ AArch64_INS_ALIAS_STRB, "strb" },
{ AArch64_INS_ALIAS_LDRH, "ldrh" },
{ AArch64_INS_ALIAS_STRH, "strh" },
{ AArch64_INS_ALIAS_PRFM, "prfm" },
{ AArch64_INS_ALIAS_LDAPURB, "ldapurb" },
{ AArch64_INS_ALIAS_STLURB, "stlurb" },
{ AArch64_INS_ALIAS_LDUR, "ldur" },
{ AArch64_INS_ALIAS_STUR, "stur" },
{ AArch64_INS_ALIAS_PRFUM, "prfum" },
{ AArch64_INS_ALIAS_LDTR, "ldtr" },
{ AArch64_INS_ALIAS_STTR, "sttr" },
{ AArch64_INS_ALIAS_LDP, "ldp" },
{ AArch64_INS_ALIAS_STGP, "stgp" },
{ AArch64_INS_ALIAS_LDNP, "ldnp" },
{ AArch64_INS_ALIAS_STNP, "stnp" },
{ AArch64_INS_ALIAS_STG, "stg" },
{ AArch64_INS_ALIAS_LD1, "ld1" },
{ AArch64_INS_ALIAS_LD1R, "ld1r" },
{ AArch64_INS_ALIAS_STADDLB, "staddlb" },
{ AArch64_INS_ALIAS_STADDLH, "staddlh" },
{ AArch64_INS_ALIAS_STADDL, "staddl" },
{ AArch64_INS_ALIAS_STADDB, "staddb" },
{ AArch64_INS_ALIAS_STADDH, "staddh" },
{ AArch64_INS_ALIAS_STADD, "stadd" },
{ AArch64_INS_ALIAS_PTRUE, "ptrue" },
{ AArch64_INS_ALIAS_PTRUES, "ptrues" },
{ AArch64_INS_ALIAS_CNTB, "cntb" },
{ AArch64_INS_ALIAS_INCB, "incb" },
{ AArch64_INS_ALIAS_SQINCB, "sqincb" },
{ AArch64_INS_ALIAS_ORR, "orr" },
{ AArch64_INS_ALIAS_DUPM, "dupm" },
{ AArch64_INS_ALIAS_FMOV, "fmov" },
{ AArch64_INS_ALIAS_EOR3, "eor3" },
{ AArch64_INS_ALIAS_ST2B, "st2b" },
{ AArch64_INS_ALIAS_ST2Q, "st2q" },
{ AArch64_INS_ALIAS_LD1RQB, "ld1rqb" },
{ AArch64_INS_ALIAS_LD2B, "ld2b" },
{ AArch64_INS_ALIAS_PRFB, "prfb" },
{ AArch64_INS_ALIAS_LDNT1SB, "ldnt1sb" },
{ AArch64_INS_ALIAS_LD1ROB, "ld1rob" },
{ AArch64_INS_ALIAS_PMOV, "pmov" },
{ AArch64_INS_ALIAS_ZERO, "zero" },
{ AArch64_INS_ALIAS_NOP, "nop" },
{ AArch64_INS_ALIAS_YIELD, "yield" },
{ AArch64_INS_ALIAS_WFE, "wfe" },
{ AArch64_INS_ALIAS_WFI, "wfi" },
{ AArch64_INS_ALIAS_SEV, "sev" },
{ AArch64_INS_ALIAS_SEVL, "sevl" },
{ AArch64_INS_ALIAS_DGH, "dgh" },
{ AArch64_INS_ALIAS_ESB, "esb" },
{ AArch64_INS_ALIAS_CSDB, "csdb" },
{ AArch64_INS_ALIAS_BTI, "bti" },
{ AArch64_INS_ALIAS_PSB, "psb" },
{ AArch64_INS_ALIAS_PACIAZ, "paciaz" },
{ AArch64_INS_ALIAS_PACIBZ, "pacibz" },
{ AArch64_INS_ALIAS_AUTIAZ, "autiaz" },
{ AArch64_INS_ALIAS_AUTIBZ, "autibz" },
{ AArch64_INS_ALIAS_PACIASP, "paciasp" },
{ AArch64_INS_ALIAS_PACIBSP, "pacibsp" },
{ AArch64_INS_ALIAS_AUTIASP, "autiasp" },
{ AArch64_INS_ALIAS_AUTIBSP, "autibsp" },
{ AArch64_INS_ALIAS_PACIA1716, "pacia1716" },
{ AArch64_INS_ALIAS_PACIB1716, "pacib1716" },
{ AArch64_INS_ALIAS_AUTIA1716, "autia1716" },
{ AArch64_INS_ALIAS_AUTIB1716, "autib1716" },
{ AArch64_INS_ALIAS_XPACLRI, "xpaclri" },
{ AArch64_INS_ALIAS_LDRAB, "ldrab" },
{ AArch64_INS_ALIAS_CLREX, "clrex" },
{ AArch64_INS_ALIAS_ISB, "isb" },
{ AArch64_INS_ALIAS_SSBB, "ssbb" },
{ AArch64_INS_ALIAS_PSSBB, "pssbb" },
{ AArch64_INS_ALIAS_DFB, "dfb" },
{ AArch64_INS_ALIAS_SYS, "sys" },
{ AArch64_INS_ALIAS_MOVN, "movn" },
{ AArch64_INS_ALIAS_MOVZ, "movz" },
{ AArch64_INS_ALIAS_NGC, "ngc" },
{ AArch64_INS_ALIAS_NGCS, "ngcs" },
{ AArch64_INS_ALIAS_SUB, "sub" },
{ AArch64_INS_ALIAS_CMP, "cmp" },
{ AArch64_INS_ALIAS_SUBS, "subs" },
{ AArch64_INS_ALIAS_NEG, "neg" },
{ AArch64_INS_ALIAS_NEGS, "negs" },
{ AArch64_INS_ALIAS_MUL, "mul" },
{ AArch64_INS_ALIAS_MNEG, "mneg" },
{ AArch64_INS_ALIAS_SMULL, "smull" },
{ AArch64_INS_ALIAS_SMNEGL, "smnegl" },
{ AArch64_INS_ALIAS_UMULL, "umull" },
{ AArch64_INS_ALIAS_UMNEGL, "umnegl" },
{ AArch64_INS_ALIAS_STCLRLB, "stclrlb" },
{ AArch64_INS_ALIAS_STCLRLH, "stclrlh" },
{ AArch64_INS_ALIAS_STCLRL, "stclrl" },
{ AArch64_INS_ALIAS_STCLRB, "stclrb" },
{ AArch64_INS_ALIAS_STCLRH, "stclrh" },
{ AArch64_INS_ALIAS_STCLR, "stclr" },
{ AArch64_INS_ALIAS_STEORLB, "steorlb" },
{ AArch64_INS_ALIAS_STEORLH, "steorlh" },
{ AArch64_INS_ALIAS_STEORL, "steorl" },
{ AArch64_INS_ALIAS_STEORB, "steorb" },
{ AArch64_INS_ALIAS_STEORH, "steorh" },
{ AArch64_INS_ALIAS_STEOR, "steor" },
{ AArch64_INS_ALIAS_STSETLB, "stsetlb" },
{ AArch64_INS_ALIAS_STSETLH, "stsetlh" },
{ AArch64_INS_ALIAS_STSETL, "stsetl" },
{ AArch64_INS_ALIAS_STSETB, "stsetb" },
{ AArch64_INS_ALIAS_STSETH, "stseth" },
{ AArch64_INS_ALIAS_STSET, "stset" },
{ AArch64_INS_ALIAS_STSMAXLB, "stsmaxlb" },
{ AArch64_INS_ALIAS_STSMAXLH, "stsmaxlh" },
{ AArch64_INS_ALIAS_STSMAXL, "stsmaxl" },
{ AArch64_INS_ALIAS_STSMAXB, "stsmaxb" },
{ AArch64_INS_ALIAS_STSMAXH, "stsmaxh" },
{ AArch64_INS_ALIAS_STSMAX, "stsmax" },
{ AArch64_INS_ALIAS_STSMINLB, "stsminlb" },
{ AArch64_INS_ALIAS_STSMINLH, "stsminlh" },
{ AArch64_INS_ALIAS_STSMINL, "stsminl" },
{ AArch64_INS_ALIAS_STSMINB, "stsminb" },
{ AArch64_INS_ALIAS_STSMINH, "stsminh" },
{ AArch64_INS_ALIAS_STSMIN, "stsmin" },
{ AArch64_INS_ALIAS_STUMAXLB, "stumaxlb" },
{ AArch64_INS_ALIAS_STUMAXLH, "stumaxlh" },
{ AArch64_INS_ALIAS_STUMAXL, "stumaxl" },
{ AArch64_INS_ALIAS_STUMAXB, "stumaxb" },
{ AArch64_INS_ALIAS_STUMAXH, "stumaxh" },
{ AArch64_INS_ALIAS_STUMAX, "stumax" },
{ AArch64_INS_ALIAS_STUMINLB, "stuminlb" },
{ AArch64_INS_ALIAS_STUMINLH, "stuminlh" },
{ AArch64_INS_ALIAS_STUMINL, "stuminl" },
{ AArch64_INS_ALIAS_STUMINB, "stuminb" },
{ AArch64_INS_ALIAS_STUMINH, "stuminh" },
{ AArch64_INS_ALIAS_STUMIN, "stumin" },
{ AArch64_INS_ALIAS_IRG, "irg" },
{ AArch64_INS_ALIAS_LDG, "ldg" },
{ AArch64_INS_ALIAS_STZG, "stzg" },
{ AArch64_INS_ALIAS_ST2G, "st2g" },
{ AArch64_INS_ALIAS_STZ2G, "stz2g" },
{ AArch64_INS_ALIAS_BICS, "bics" },
{ AArch64_INS_ALIAS_BIC, "bic" },
{ AArch64_INS_ALIAS_EON, "eon" },
{ AArch64_INS_ALIAS_ORN, "orn" },
{ AArch64_INS_ALIAS_MVN, "mvn" },
{ AArch64_INS_ALIAS_TST, "tst" },
{ AArch64_INS_ALIAS_ROR, "ror" },
{ AArch64_INS_ALIAS_ASR, "asr" },
{ AArch64_INS_ALIAS_SXTB, "sxtb" },
{ AArch64_INS_ALIAS_SXTH, "sxth" },
{ AArch64_INS_ALIAS_SXTW, "sxtw" },
{ AArch64_INS_ALIAS_LSR, "lsr" },
{ AArch64_INS_ALIAS_UXTB, "uxtb" },
{ AArch64_INS_ALIAS_UXTH, "uxth" },
{ AArch64_INS_ALIAS_UXTW, "uxtw" },
{ AArch64_INS_ALIAS_CSET, "cset" },
{ AArch64_INS_ALIAS_CSETM, "csetm" },
{ AArch64_INS_ALIAS_CINC, "cinc" },
{ AArch64_INS_ALIAS_CINV, "cinv" },
{ AArch64_INS_ALIAS_CNEG, "cneg" },
{ AArch64_INS_ALIAS_RET, "ret" },
{ AArch64_INS_ALIAS_DCPS1, "dcps1" },
{ AArch64_INS_ALIAS_DCPS2, "dcps2" },
{ AArch64_INS_ALIAS_DCPS3, "dcps3" },
{ AArch64_INS_ALIAS_LDPSW, "ldpsw" },
{ AArch64_INS_ALIAS_LDRSH, "ldrsh" },
{ AArch64_INS_ALIAS_LDRSB, "ldrsb" },
{ AArch64_INS_ALIAS_LDRSW, "ldrsw" },
{ AArch64_INS_ALIAS_LDURH, "ldurh" },
{ AArch64_INS_ALIAS_LDURB, "ldurb" },
{ AArch64_INS_ALIAS_LDURSH, "ldursh" },
{ AArch64_INS_ALIAS_LDURSB, "ldursb" },
{ AArch64_INS_ALIAS_LDURSW, "ldursw" },
{ AArch64_INS_ALIAS_LDTRH, "ldtrh" },
{ AArch64_INS_ALIAS_LDTRB, "ldtrb" },
{ AArch64_INS_ALIAS_LDTRSH, "ldtrsh" },
{ AArch64_INS_ALIAS_LDTRSB, "ldtrsb" },
{ AArch64_INS_ALIAS_LDTRSW, "ldtrsw" },
{ AArch64_INS_ALIAS_STP, "stp" },
{ AArch64_INS_ALIAS_STURH, "sturh" },
{ AArch64_INS_ALIAS_STURB, "sturb" },
{ AArch64_INS_ALIAS_STLURH, "stlurh" },
{ AArch64_INS_ALIAS_LDAPURSB, "ldapursb" },
{ AArch64_INS_ALIAS_LDAPURH, "ldapurh" },
{ AArch64_INS_ALIAS_LDAPURSH, "ldapursh" },
{ AArch64_INS_ALIAS_LDAPURSW, "ldapursw" },
{ AArch64_INS_ALIAS_STTRH, "sttrh" },
{ AArch64_INS_ALIAS_STTRB, "sttrb" },
{ AArch64_INS_ALIAS_BIC_4H, "bic_4h" },
{ AArch64_INS_ALIAS_BIC_8H, "bic_8h" },
{ AArch64_INS_ALIAS_BIC_2S, "bic_2s" },
{ AArch64_INS_ALIAS_BIC_4S, "bic_4s" },
{ AArch64_INS_ALIAS_ORR_4H, "orr_4h" },
{ AArch64_INS_ALIAS_ORR_8H, "orr_8h" },
{ AArch64_INS_ALIAS_ORR_2S, "orr_2s" },
{ AArch64_INS_ALIAS_ORR_4S, "orr_4s" },
{ AArch64_INS_ALIAS_SXTL_8H, "sxtl_8h" },
{ AArch64_INS_ALIAS_SXTL, "sxtl" },
{ AArch64_INS_ALIAS_SXTL_4S, "sxtl_4s" },
{ AArch64_INS_ALIAS_SXTL_2D, "sxtl_2d" },
{ AArch64_INS_ALIAS_SXTL2_8H, "sxtl2_8h" },
{ AArch64_INS_ALIAS_SXTL2, "sxtl2" },
{ AArch64_INS_ALIAS_SXTL2_4S, "sxtl2_4s" },
{ AArch64_INS_ALIAS_SXTL2_2D, "sxtl2_2d" },
{ AArch64_INS_ALIAS_UXTL_8H, "uxtl_8h" },
{ AArch64_INS_ALIAS_UXTL, "uxtl" },
{ AArch64_INS_ALIAS_UXTL_4S, "uxtl_4s" },
{ AArch64_INS_ALIAS_UXTL_2D, "uxtl_2d" },
{ AArch64_INS_ALIAS_UXTL2_8H, "uxtl2_8h" },
{ AArch64_INS_ALIAS_UXTL2, "uxtl2" },
{ AArch64_INS_ALIAS_UXTL2_4S, "uxtl2_4s" },
{ AArch64_INS_ALIAS_UXTL2_2D, "uxtl2_2d" },
{ AArch64_INS_ALIAS_LD2, "ld2" },
{ AArch64_INS_ALIAS_LD3, "ld3" },
{ AArch64_INS_ALIAS_LD4, "ld4" },
{ AArch64_INS_ALIAS_ST1, "st1" },
{ AArch64_INS_ALIAS_ST2, "st2" },
{ AArch64_INS_ALIAS_ST3, "st3" },
{ AArch64_INS_ALIAS_ST4, "st4" },
{ AArch64_INS_ALIAS_LD2R, "ld2r" },
{ AArch64_INS_ALIAS_LD3R, "ld3r" },
{ AArch64_INS_ALIAS_LD4R, "ld4r" },
{ AArch64_INS_ALIAS_CLRBHB, "clrbhb" },
{ AArch64_INS_ALIAS_STILP, "stilp" },
{ AArch64_INS_ALIAS_STL1, "stl1" },
{ AArch64_INS_ALIAS_SYSP, "sysp" },

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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
{ AArch64_FEATURE_HasV8_0a, "HasV8_0a" },
{ AArch64_FEATURE_HasV8_1a, "HasV8_1a" },
{ AArch64_FEATURE_HasV8_2a, "HasV8_2a" },
{ AArch64_FEATURE_HasV8_3a, "HasV8_3a" },
{ AArch64_FEATURE_HasV8_4a, "HasV8_4a" },
{ AArch64_FEATURE_HasV8_5a, "HasV8_5a" },
{ AArch64_FEATURE_HasV8_6a, "HasV8_6a" },
{ AArch64_FEATURE_HasV8_7a, "HasV8_7a" },
{ AArch64_FEATURE_HasV8_8a, "HasV8_8a" },
{ AArch64_FEATURE_HasV8_9a, "HasV8_9a" },
{ AArch64_FEATURE_HasV9_0a, "HasV9_0a" },
{ AArch64_FEATURE_HasV9_1a, "HasV9_1a" },
{ AArch64_FEATURE_HasV9_2a, "HasV9_2a" },
{ AArch64_FEATURE_HasV9_3a, "HasV9_3a" },
{ AArch64_FEATURE_HasV9_4a, "HasV9_4a" },
{ AArch64_FEATURE_HasV8_0r, "HasV8_0r" },
{ AArch64_FEATURE_HasEL2VMSA, "HasEL2VMSA" },
{ AArch64_FEATURE_HasEL3, "HasEL3" },
{ AArch64_FEATURE_HasVH, "HasVH" },
{ AArch64_FEATURE_HasLOR, "HasLOR" },
{ AArch64_FEATURE_HasPAuth, "HasPAuth" },
{ AArch64_FEATURE_HasJS, "HasJS" },
{ AArch64_FEATURE_HasCCIDX, "HasCCIDX" },
{ AArch64_FEATURE_HasComplxNum, "HasComplxNum" },
{ AArch64_FEATURE_HasNV, "HasNV" },
{ AArch64_FEATURE_HasMPAM, "HasMPAM" },
{ AArch64_FEATURE_HasDIT, "HasDIT" },
{ AArch64_FEATURE_HasTRACEV8_4, "HasTRACEV8_4" },
{ AArch64_FEATURE_HasAM, "HasAM" },
{ AArch64_FEATURE_HasSEL2, "HasSEL2" },
{ AArch64_FEATURE_HasTLB_RMI, "HasTLB_RMI" },
{ AArch64_FEATURE_HasFlagM, "HasFlagM" },
{ AArch64_FEATURE_HasRCPC_IMMO, "HasRCPC_IMMO" },
{ AArch64_FEATURE_HasFPARMv8, "HasFPARMv8" },
{ AArch64_FEATURE_HasNEON, "HasNEON" },
{ AArch64_FEATURE_HasCrypto, "HasCrypto" },
{ AArch64_FEATURE_HasSM4, "HasSM4" },
{ AArch64_FEATURE_HasSHA3, "HasSHA3" },
{ AArch64_FEATURE_HasSHA2, "HasSHA2" },
{ AArch64_FEATURE_HasAES, "HasAES" },
{ AArch64_FEATURE_HasDotProd, "HasDotProd" },
{ AArch64_FEATURE_HasCRC, "HasCRC" },
{ AArch64_FEATURE_HasCSSC, "HasCSSC" },
{ AArch64_FEATURE_HasLSE, "HasLSE" },
{ AArch64_FEATURE_HasRAS, "HasRAS" },
{ AArch64_FEATURE_HasRDM, "HasRDM" },
{ AArch64_FEATURE_HasFullFP16, "HasFullFP16" },
{ AArch64_FEATURE_HasFP16FML, "HasFP16FML" },
{ AArch64_FEATURE_HasSPE, "HasSPE" },
{ AArch64_FEATURE_HasFuseAES, "HasFuseAES" },
{ AArch64_FEATURE_HasSVE, "HasSVE" },
{ AArch64_FEATURE_HasSVE2, "HasSVE2" },
{ AArch64_FEATURE_HasSVE2p1, "HasSVE2p1" },
{ AArch64_FEATURE_HasSVE2AES, "HasSVE2AES" },
{ AArch64_FEATURE_HasSVE2SM4, "HasSVE2SM4" },
{ AArch64_FEATURE_HasSVE2SHA3, "HasSVE2SHA3" },
{ AArch64_FEATURE_HasSVE2BitPerm, "HasSVE2BitPerm" },
{ AArch64_FEATURE_HasB16B16, "HasB16B16" },
{ AArch64_FEATURE_HasSME, "HasSME" },
{ AArch64_FEATURE_HasSMEF64F64, "HasSMEF64F64" },
{ AArch64_FEATURE_HasSMEF16F16, "HasSMEF16F16" },
{ AArch64_FEATURE_HasSMEI16I64, "HasSMEI16I64" },
{ AArch64_FEATURE_HasSME2, "HasSME2" },
{ AArch64_FEATURE_HasSME2p1, "HasSME2p1" },
{ AArch64_FEATURE_HasSVEorSME, "HasSVEorSME" },
{ AArch64_FEATURE_HasSVE2orSME, "HasSVE2orSME" },
{ AArch64_FEATURE_HasSVE2p1_or_HasSME, "HasSVE2p1_or_HasSME" },
{ AArch64_FEATURE_HasSVE2p1_or_HasSME2, "HasSVE2p1_or_HasSME2" },
{ AArch64_FEATURE_HasSVE2p1_or_HasSME2p1, "HasSVE2p1_or_HasSME2p1" },
{ AArch64_FEATURE_HasNEONorSME, "HasNEONorSME" },
{ AArch64_FEATURE_HasRCPC, "HasRCPC" },
{ AArch64_FEATURE_HasAltNZCV, "HasAltNZCV" },
{ AArch64_FEATURE_HasFRInt3264, "HasFRInt3264" },
{ AArch64_FEATURE_HasSB, "HasSB" },
{ AArch64_FEATURE_HasPredRes, "HasPredRes" },
{ AArch64_FEATURE_HasCCDP, "HasCCDP" },
{ AArch64_FEATURE_HasBTI, "HasBTI" },
{ AArch64_FEATURE_HasMTE, "HasMTE" },
{ AArch64_FEATURE_HasTME, "HasTME" },
{ AArch64_FEATURE_HasETE, "HasETE" },
{ AArch64_FEATURE_HasTRBE, "HasTRBE" },
{ AArch64_FEATURE_HasBF16, "HasBF16" },
{ AArch64_FEATURE_HasMatMulInt8, "HasMatMulInt8" },
{ AArch64_FEATURE_HasMatMulFP32, "HasMatMulFP32" },
{ AArch64_FEATURE_HasMatMulFP64, "HasMatMulFP64" },
{ AArch64_FEATURE_HasXS, "HasXS" },
{ AArch64_FEATURE_HasWFxT, "HasWFxT" },
{ AArch64_FEATURE_HasLS64, "HasLS64" },
{ AArch64_FEATURE_HasBRBE, "HasBRBE" },
{ AArch64_FEATURE_HasSPE_EEF, "HasSPE_EEF" },
{ AArch64_FEATURE_HasHBC, "HasHBC" },
{ AArch64_FEATURE_HasMOPS, "HasMOPS" },
{ AArch64_FEATURE_HasCLRBHB, "HasCLRBHB" },
{ AArch64_FEATURE_HasSPECRES2, "HasSPECRES2" },
{ AArch64_FEATURE_HasITE, "HasITE" },
{ AArch64_FEATURE_HasTHE, "HasTHE" },
{ AArch64_FEATURE_HasRCPC3, "HasRCPC3" },
{ AArch64_FEATURE_HasLSE128, "HasLSE128" },
{ AArch64_FEATURE_HasD128, "HasD128" },
{ AArch64_FEATURE_UseNegativeImmediates, "UseNegativeImmediates" },
{ AArch64_FEATURE_HasCCPP, "HasCCPP" },
{ AArch64_FEATURE_HasPAN, "HasPAN" },
{ AArch64_FEATURE_HasPsUAO, "HasPsUAO" },
{ AArch64_FEATURE_HasPAN_RWV, "HasPAN_RWV" },
{ AArch64_FEATURE_HasCONTEXTIDREL2, "HasCONTEXTIDREL2" },

54382
arch/AArch64/AArch64GenCSMappingInsn.inc Normal file
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arch/AArch64/AArch64GenCSMappingInsnName.inc Normal file
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arch/AArch64/AArch64GenCSMappingInsnOp.inc Normal file
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arch/AArch64/AArch64GenCSOpGroup.inc Normal file
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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
AArch64_OP_GROUP_AMNoIndex = 0,
AArch64_OP_GROUP_BTIHintOp = 1,
AArch64_OP_GROUP_ImplicitlyTypedVectorList = 2,
AArch64_OP_GROUP_InverseCondCode = 3,
AArch64_OP_GROUP_LogicalImm_int16_t = 4,
AArch64_OP_GROUP_LogicalImm_int8_t = 5,
AArch64_OP_GROUP_PSBHintOp = 6,
AArch64_OP_GROUP_PrefetchOp_1 = 7,
AArch64_OP_GROUP_SVELogicalImm_int16_t = 8,
AArch64_OP_GROUP_SVELogicalImm_int32_t = 9,
AArch64_OP_GROUP_SVELogicalImm_int64_t = 10,
AArch64_OP_GROUP_SVERegOp_0 = 11,
AArch64_OP_GROUP_VectorIndex_8 = 12,
AArch64_OP_GROUP_ZPRasFPR_128 = 13,
AArch64_OP_GROUP_Operand = 14,
AArch64_OP_GROUP_SVERegOp_b = 15,
AArch64_OP_GROUP_SVERegOp_d = 16,
AArch64_OP_GROUP_SVERegOp_h = 17,
AArch64_OP_GROUP_SVERegOp_s = 18,
AArch64_OP_GROUP_MatrixIndex = 19,
AArch64_OP_GROUP_TypedVectorList_0_d = 20,
AArch64_OP_GROUP_TypedVectorList_0_s = 21,
AArch64_OP_GROUP_VRegOperand = 22,
AArch64_OP_GROUP_TypedVectorList_0_h = 23,
AArch64_OP_GROUP_VectorIndex_1 = 24,
AArch64_OP_GROUP_ImmRangeScale_2_1 = 25,
AArch64_OP_GROUP_AlignedLabel = 26,
AArch64_OP_GROUP_CondCode = 27,
AArch64_OP_GROUP_ExactFPImm_AArch64ExactFPImm_half_AArch64ExactFPImm_one = 28,
AArch64_OP_GROUP_ExactFPImm_AArch64ExactFPImm_zero_AArch64ExactFPImm_one = 29,
AArch64_OP_GROUP_ExactFPImm_AArch64ExactFPImm_half_AArch64ExactFPImm_two = 30,
AArch64_OP_GROUP_RegWithShiftExtend_0_8_x_d = 31,
AArch64_OP_GROUP_RegWithShiftExtend_1_8_w_d = 32,
AArch64_OP_GROUP_RegWithShiftExtend_0_8_w_d = 33,
AArch64_OP_GROUP_RegWithShiftExtend_1_8_w_s = 34,
AArch64_OP_GROUP_RegWithShiftExtend_0_8_w_s = 35,
AArch64_OP_GROUP_ImmScale_8 = 36,
AArch64_OP_GROUP_RegWithShiftExtend_0_64_x_d = 37,
AArch64_OP_GROUP_RegWithShiftExtend_1_64_w_d = 38,
AArch64_OP_GROUP_RegWithShiftExtend_0_64_w_d = 39,
AArch64_OP_GROUP_ImmScale_2 = 40,
AArch64_OP_GROUP_RegWithShiftExtend_0_16_x_d = 41,
AArch64_OP_GROUP_RegWithShiftExtend_1_16_w_d = 42,
AArch64_OP_GROUP_RegWithShiftExtend_0_16_w_d = 43,
AArch64_OP_GROUP_RegWithShiftExtend_1_16_w_s = 44,
AArch64_OP_GROUP_RegWithShiftExtend_0_16_w_s = 45,
AArch64_OP_GROUP_ImmScale_4 = 46,
AArch64_OP_GROUP_RegWithShiftExtend_0_32_x_d = 47,
AArch64_OP_GROUP_RegWithShiftExtend_1_32_w_d = 48,
AArch64_OP_GROUP_RegWithShiftExtend_0_32_w_d = 49,
AArch64_OP_GROUP_RegWithShiftExtend_1_32_w_s = 50,
AArch64_OP_GROUP_RegWithShiftExtend_0_32_w_s = 51,
AArch64_OP_GROUP_TypedVectorList_0_b = 52,
AArch64_OP_GROUP_RegWithShiftExtend_0_8_x_0 = 53,
AArch64_OP_GROUP_RegWithShiftExtend_0_64_x_0 = 54,
AArch64_OP_GROUP_RegWithShiftExtend_0_16_x_0 = 55,
AArch64_OP_GROUP_RegWithShiftExtend_0_32_x_0 = 56,
AArch64_OP_GROUP_SVCROp = 57,
AArch64_OP_GROUP_ImmScale_16 = 58,
AArch64_OP_GROUP_MatrixTile = 59,
AArch64_OP_GROUP_AddSubImm = 60,
AArch64_OP_GROUP_ShiftedRegister = 61,
AArch64_OP_GROUP_ExtendedRegister = 62,
AArch64_OP_GROUP_ArithExtend = 63,
AArch64_OP_GROUP_Matrix_64 = 64,
AArch64_OP_GROUP_Matrix_32 = 65,
AArch64_OP_GROUP_Imm8OptLsl_uint8_t = 66,
AArch64_OP_GROUP_Imm8OptLsl_uint64_t = 67,
AArch64_OP_GROUP_Imm8OptLsl_uint16_t = 68,
AArch64_OP_GROUP_Imm8OptLsl_uint32_t = 69,
AArch64_OP_GROUP_AdrLabel = 70,
AArch64_OP_GROUP_AdrpLabel = 71,
AArch64_OP_GROUP_RegWithShiftExtend_0_8_x_s = 72,
AArch64_OP_GROUP_RegWithShiftExtend_0_16_x_s = 73,
AArch64_OP_GROUP_RegWithShiftExtend_0_32_x_s = 74,
AArch64_OP_GROUP_RegWithShiftExtend_0_64_x_s = 75,
AArch64_OP_GROUP_LogicalImm_int32_t = 76,
AArch64_OP_GROUP_LogicalImm_int64_t = 77,
AArch64_OP_GROUP_ZPRasFPR_8 = 78,
AArch64_OP_GROUP_ZPRasFPR_64 = 79,
AArch64_OP_GROUP_ZPRasFPR_16 = 80,
AArch64_OP_GROUP_ZPRasFPR_32 = 81,
AArch64_OP_GROUP_Matrix_16 = 82,
AArch64_OP_GROUP_Imm = 83,
AArch64_OP_GROUP_Shifter = 84,
AArch64_OP_GROUP_ImmHex = 85,
AArch64_OP_GROUP_ComplexRotationOp_180_90 = 86,
AArch64_OP_GROUP_GPRSeqPairsClassOperand_32 = 87,
AArch64_OP_GROUP_GPRSeqPairsClassOperand_64 = 88,
AArch64_OP_GROUP_ComplexRotationOp_90_0 = 89,
AArch64_OP_GROUP_SVEPattern = 90,
AArch64_OP_GROUP_PredicateAsCounter_8 = 91,
AArch64_OP_GROUP_SVEVecLenSpecifier = 92,
AArch64_OP_GROUP_PredicateAsCounter_64 = 93,
AArch64_OP_GROUP_PredicateAsCounter_16 = 94,
AArch64_OP_GROUP_PredicateAsCounter_32 = 95,
AArch64_OP_GROUP_Imm8OptLsl_int8_t = 96,
AArch64_OP_GROUP_Imm8OptLsl_int64_t = 97,
AArch64_OP_GROUP_Imm8OptLsl_int16_t = 98,
AArch64_OP_GROUP_Imm8OptLsl_int32_t = 99,
AArch64_OP_GROUP_BarrierOption = 100,
AArch64_OP_GROUP_BarriernXSOption = 101,
AArch64_OP_GROUP_SVERegOp_q = 102,
AArch64_OP_GROUP_MatrixTileVector_0 = 103,
AArch64_OP_GROUP_MatrixTileVector_1 = 104,
AArch64_OP_GROUP_FPImmOperand = 105,
AArch64_OP_GROUP_TypedVectorList_0_q = 106,
AArch64_OP_GROUP_SImm_8 = 107,
AArch64_OP_GROUP_SImm_16 = 108,
AArch64_OP_GROUP_PredicateAsCounter_0 = 109,
AArch64_OP_GROUP_TypedVectorList_16_b = 110,
AArch64_OP_GROUP_PostIncOperand_64 = 111,
AArch64_OP_GROUP_TypedVectorList_1_d = 112,
AArch64_OP_GROUP_PostIncOperand_32 = 113,
AArch64_OP_GROUP_TypedVectorList_2_d = 114,
AArch64_OP_GROUP_TypedVectorList_2_s = 115,
AArch64_OP_GROUP_TypedVectorList_4_h = 116,
AArch64_OP_GROUP_TypedVectorList_4_s = 117,
AArch64_OP_GROUP_TypedVectorList_8_b = 118,
AArch64_OP_GROUP_TypedVectorList_8_h = 119,
AArch64_OP_GROUP_PostIncOperand_16 = 120,
AArch64_OP_GROUP_PostIncOperand_8 = 121,
AArch64_OP_GROUP_ImmScale_32 = 122,
AArch64_OP_GROUP_PostIncOperand_1 = 123,
AArch64_OP_GROUP_PostIncOperand_4 = 124,
AArch64_OP_GROUP_PostIncOperand_2 = 125,
AArch64_OP_GROUP_PostIncOperand_48 = 126,
AArch64_OP_GROUP_PostIncOperand_24 = 127,
AArch64_OP_GROUP_RegWithShiftExtend_0_128_x_0 = 128,
AArch64_OP_GROUP_ImmScale_3 = 129,
AArch64_OP_GROUP_PostIncOperand_3 = 130,
AArch64_OP_GROUP_PostIncOperand_12 = 131,
AArch64_OP_GROUP_PostIncOperand_6 = 132,
AArch64_OP_GROUP_GPR64x8 = 133,
AArch64_OP_GROUP_MemExtend_w_8 = 134,
AArch64_OP_GROUP_MemExtend_x_8 = 135,
AArch64_OP_GROUP_UImm12Offset_1 = 136,
AArch64_OP_GROUP_MemExtend_w_64 = 137,
AArch64_OP_GROUP_MemExtend_x_64 = 138,
AArch64_OP_GROUP_UImm12Offset_8 = 139,
AArch64_OP_GROUP_MemExtend_w_16 = 140,
AArch64_OP_GROUP_MemExtend_x_16 = 141,
AArch64_OP_GROUP_UImm12Offset_2 = 142,
AArch64_OP_GROUP_MemExtend_w_128 = 143,
AArch64_OP_GROUP_MemExtend_x_128 = 144,
AArch64_OP_GROUP_UImm12Offset_16 = 145,
AArch64_OP_GROUP_MemExtend_w_32 = 146,
AArch64_OP_GROUP_MemExtend_x_32 = 147,
AArch64_OP_GROUP_UImm12Offset_4 = 148,
AArch64_OP_GROUP_Matrix_0 = 149,
AArch64_OP_GROUP_ImmRangeScale_4_3 = 150,
AArch64_OP_GROUP_SIMDType10Operand = 151,
AArch64_OP_GROUP_MRSSystemRegister = 152,
AArch64_OP_GROUP_MSRSystemRegister = 153,
AArch64_OP_GROUP_SystemPStateField = 154,
AArch64_OP_GROUP_RegWithShiftExtend_1_64_w_s = 155,
AArch64_OP_GROUP_RegWithShiftExtend_0_64_w_s = 156,
AArch64_OP_GROUP_PrefetchOp_0 = 157,
AArch64_OP_GROUP_RPRFMOperand = 158,
AArch64_OP_GROUP_GPR64as32 = 159,
AArch64_OP_GROUP_SysCROperand = 160,
AArch64_OP_GROUP_SyspXzrPair = 161,
AArch64_OP_GROUP_MatrixTileList = 162,

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arch/AArch64/AArch64GenDisassemblerTables.inc
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arch/AArch64/AArch64GenInstrInfo.inc
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arch/AArch64/AArch64GenRegisterInfo.inc
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arch/AArch64/AArch64GenRegisterV.inc
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@ -1,673 +0,0 @@
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ARM64_REG_V0,
ARM64_REG_V1,
ARM64_REG_V2,
ARM64_REG_V3,
ARM64_REG_V4,
ARM64_REG_V5,
ARM64_REG_V6,
ARM64_REG_V7,
ARM64_REG_V8,
ARM64_REG_V9,
ARM64_REG_V10,
ARM64_REG_V11,
ARM64_REG_V12,
ARM64_REG_V13,
ARM64_REG_V14,
ARM64_REG_V15,
ARM64_REG_V16,
ARM64_REG_V17,
ARM64_REG_V18,
ARM64_REG_V19,
ARM64_REG_V20,
ARM64_REG_V21,
ARM64_REG_V22,
ARM64_REG_V23,
ARM64_REG_V24,
ARM64_REG_V25,
ARM64_REG_V26,
ARM64_REG_V27,
ARM64_REG_V28,
ARM64_REG_V29,
ARM64_REG_V30,
ARM64_REG_V31,
ARM64_REG_V0,
ARM64_REG_V1,
ARM64_REG_V2,
ARM64_REG_V3,
ARM64_REG_V4,
ARM64_REG_V5,
ARM64_REG_V6,
ARM64_REG_V7,
ARM64_REG_V8,
ARM64_REG_V9,
ARM64_REG_V10,
ARM64_REG_V11,
ARM64_REG_V12,
ARM64_REG_V13,
ARM64_REG_V14,
ARM64_REG_V15,
ARM64_REG_V16,
ARM64_REG_V17,
ARM64_REG_V18,
ARM64_REG_V19,
ARM64_REG_V20,
ARM64_REG_V21,
ARM64_REG_V22,
ARM64_REG_V23,
ARM64_REG_V24,
ARM64_REG_V25,
ARM64_REG_V26,
ARM64_REG_V27,
ARM64_REG_V28,
ARM64_REG_V29,
ARM64_REG_V30,
ARM64_REG_V31,
ARM64_REG_V0,
ARM64_REG_V1,
ARM64_REG_V2,
ARM64_REG_V3,
ARM64_REG_V4,
ARM64_REG_V5,
ARM64_REG_V6,
ARM64_REG_V7,
ARM64_REG_V8,
ARM64_REG_V9,
ARM64_REG_V10,
ARM64_REG_V11,
ARM64_REG_V12,
ARM64_REG_V13,
ARM64_REG_V14,
ARM64_REG_V15,
ARM64_REG_V16,
ARM64_REG_V17,
ARM64_REG_V18,
ARM64_REG_V19,
ARM64_REG_V20,
ARM64_REG_V21,
ARM64_REG_V22,
ARM64_REG_V23,
ARM64_REG_V24,
ARM64_REG_V25,
ARM64_REG_V26,
ARM64_REG_V27,
ARM64_REG_V28,
ARM64_REG_V29,
ARM64_REG_V30,
ARM64_REG_V31,
ARM64_REG_V0,
ARM64_REG_V1,
ARM64_REG_V2,
ARM64_REG_V3,
ARM64_REG_V4,
ARM64_REG_V5,
ARM64_REG_V6,
ARM64_REG_V7,
ARM64_REG_V8,
ARM64_REG_V9,
ARM64_REG_V10,
ARM64_REG_V11,
ARM64_REG_V12,
ARM64_REG_V13,
ARM64_REG_V14,
ARM64_REG_V15,
ARM64_REG_V16,
ARM64_REG_V17,
ARM64_REG_V18,
ARM64_REG_V19,
ARM64_REG_V20,
ARM64_REG_V21,
ARM64_REG_V22,
ARM64_REG_V23,
ARM64_REG_V24,
ARM64_REG_V25,
ARM64_REG_V26,
ARM64_REG_V27,
ARM64_REG_V28,
ARM64_REG_V29,
ARM64_REG_V30,
ARM64_REG_V31,
ARM64_REG_V0,
ARM64_REG_V1,
ARM64_REG_V2,
ARM64_REG_V3,
ARM64_REG_V4,
ARM64_REG_V5,
ARM64_REG_V6,
ARM64_REG_V7,
ARM64_REG_V8,
ARM64_REG_V9,
ARM64_REG_V10,
ARM64_REG_V11,
ARM64_REG_V12,
ARM64_REG_V13,
ARM64_REG_V14,
ARM64_REG_V15,
ARM64_REG_V16,
ARM64_REG_V17,
ARM64_REG_V18,
ARM64_REG_V19,
ARM64_REG_V20,
ARM64_REG_V21,
ARM64_REG_V22,
ARM64_REG_V23,
ARM64_REG_V24,
ARM64_REG_V25,
ARM64_REG_V26,
ARM64_REG_V27,
ARM64_REG_V28,
ARM64_REG_V29,
ARM64_REG_V30,
ARM64_REG_V31,
ARM64_REG_V0,
ARM64_REG_V1,
ARM64_REG_V2,
ARM64_REG_V3,
ARM64_REG_V4,
ARM64_REG_V5,
ARM64_REG_V6,
ARM64_REG_V7,
ARM64_REG_V8,
ARM64_REG_V9,
ARM64_REG_V10,
ARM64_REG_V11,
ARM64_REG_V12,
ARM64_REG_V13,
ARM64_REG_V14,
ARM64_REG_V15,
ARM64_REG_V16,
ARM64_REG_V17,
ARM64_REG_V18,
ARM64_REG_V19,
ARM64_REG_V20,
ARM64_REG_V21,
ARM64_REG_V22,
ARM64_REG_V23,
ARM64_REG_V24,
ARM64_REG_V25,
ARM64_REG_V26,
ARM64_REG_V27,
ARM64_REG_V28,
ARM64_REG_V29,
ARM64_REG_V30,
ARM64_REG_V31,
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472
arch/AArch64/AArch64GenSubtargetInfo.inc
View File

@ -1,229 +1,265 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *|
|* Subtarget Enumeration Source Fragment *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
#ifdef GET_SUBTARGETINFO_ENUM
#undef GET_SUBTARGETINFO_ENUM
enum {
AArch64_FeatureAES = 0,
AArch64_FeatureAM = 1,
AArch64_FeatureAMVS = 2,
AArch64_FeatureAggressiveFMA = 3,
AArch64_FeatureAltFPCmp = 4,
AArch64_FeatureAlternateSExtLoadCVTF32Pattern = 5,
AArch64_FeatureAppleA7SysReg = 6,
AArch64_FeatureArithmeticBccFusion = 7,
AArch64_FeatureArithmeticCbzFusion = 8,
AArch64_FeatureBF16 = 9,
AArch64_FeatureBRBE = 10,
AArch64_FeatureBalanceFPOps = 11,
AArch64_FeatureBranchTargetId = 12,
AArch64_FeatureCCIDX = 13,
AArch64_FeatureCCPP = 14,
AArch64_FeatureCONTEXTIDREL2 = 15,
AArch64_FeatureCRC = 16,
AArch64_FeatureCacheDeepPersist = 17,
AArch64_FeatureCallSavedX8 = 18,
AArch64_FeatureCallSavedX9 = 19,
AArch64_FeatureCallSavedX10 = 20,
AArch64_FeatureCallSavedX11 = 21,
AArch64_FeatureCallSavedX12 = 22,
AArch64_FeatureCallSavedX13 = 23,
AArch64_FeatureCallSavedX14 = 24,
AArch64_FeatureCallSavedX15 = 25,
AArch64_FeatureCallSavedX18 = 26,
AArch64_FeatureCmpBccFusion = 27,
AArch64_FeatureComplxNum = 28,
AArch64_FeatureCrypto = 29,
AArch64_FeatureCustomCheapAsMoveHandling = 30,
AArch64_FeatureDIT = 31,
AArch64_FeatureDisableLatencySchedHeuristic = 32,
AArch64_FeatureDotProd = 33,
AArch64_FeatureEL2VMSA = 34,
AArch64_FeatureEL3 = 35,
AArch64_FeatureETE = 36,
AArch64_FeatureEnhancedCounterVirtualization = 37,
AArch64_FeatureExperimentalZeroingPseudos = 38,
AArch64_FeatureExynosCheapAsMoveHandling = 39,
AArch64_FeatureFP16FML = 40,
AArch64_FeatureFPARMv8 = 41,
AArch64_FeatureFRInt3264 = 42,
AArch64_FeatureFineGrainedTraps = 43,
AArch64_FeatureFixCortexA53_835769 = 44,
AArch64_FeatureFlagM = 45,
AArch64_FeatureForce32BitJumpTables = 46,
AArch64_FeatureFullFP16 = 47,
AArch64_FeatureFuseAES = 48,
AArch64_FeatureFuseAddress = 49,
AArch64_FeatureFuseArithmeticLogic = 50,
AArch64_FeatureFuseCCSelect = 51,
AArch64_FeatureFuseCryptoEOR = 52,
AArch64_FeatureFuseLiterals = 53,
AArch64_FeatureHBC = 54,
AArch64_FeatureHCX = 55,
AArch64_FeatureHardenSlsBlr = 56,
AArch64_FeatureHardenSlsNoComdat = 57,
AArch64_FeatureHardenSlsRetBr = 58,
AArch64_FeatureJS = 59,
AArch64_FeatureLOR = 60,
AArch64_FeatureLS64 = 61,
AArch64_FeatureLSE = 62,
AArch64_FeatureLSE2 = 63,
AArch64_FeatureLSLFast = 64,
AArch64_FeatureMOPS = 65,
AArch64_FeatureMPAM = 66,
AArch64_FeatureMTE = 67,
AArch64_FeatureMatMulFP32 = 68,
AArch64_FeatureMatMulFP64 = 69,
AArch64_FeatureMatMulInt8 = 70,
AArch64_FeatureNEON = 71,
AArch64_FeatureNV = 72,
AArch64_FeatureNoBTIAtReturnTwice = 73,
AArch64_FeatureNoNegativeImmediates = 74,
AArch64_FeatureNoZCZeroingFP = 75,
AArch64_FeatureOutlineAtomics = 76,
AArch64_FeaturePAN = 77,
AArch64_FeaturePAN_RWV = 78,
AArch64_FeaturePAuth = 79,
AArch64_FeaturePerfMon = 80,
AArch64_FeaturePostRAScheduler = 81,
AArch64_FeaturePredRes = 82,
AArch64_FeaturePredictableSelectIsExpensive = 83,
AArch64_FeaturePsUAO = 84,
AArch64_FeatureRAS = 85,
AArch64_FeatureRCPC = 86,
AArch64_FeatureRCPC_IMMO = 87,
AArch64_FeatureRDM = 88,
AArch64_FeatureRME = 89,
AArch64_FeatureRandGen = 90,
AArch64_FeatureReserveX1 = 91,
AArch64_FeatureReserveX2 = 92,
AArch64_FeatureReserveX3 = 93,
AArch64_FeatureReserveX4 = 94,
AArch64_FeatureReserveX5 = 95,
AArch64_FeatureReserveX6 = 96,
AArch64_FeatureReserveX7 = 97,
AArch64_FeatureReserveX9 = 98,
AArch64_FeatureReserveX10 = 99,
AArch64_FeatureReserveX11 = 100,
AArch64_FeatureReserveX12 = 101,
AArch64_FeatureReserveX13 = 102,
AArch64_FeatureReserveX14 = 103,
AArch64_FeatureReserveX15 = 104,
AArch64_FeatureReserveX18 = 105,
AArch64_FeatureReserveX20 = 106,
AArch64_FeatureReserveX21 = 107,
AArch64_FeatureReserveX22 = 108,
AArch64_FeatureReserveX23 = 109,
AArch64_FeatureReserveX24 = 110,
AArch64_FeatureReserveX25 = 111,
AArch64_FeatureReserveX26 = 112,
AArch64_FeatureReserveX27 = 113,
AArch64_FeatureReserveX28 = 114,
AArch64_FeatureReserveX30 = 115,
AArch64_FeatureSB = 116,
AArch64_FeatureSEL2 = 117,
AArch64_FeatureSHA2 = 118,
AArch64_FeatureSHA3 = 119,
AArch64_FeatureSM4 = 120,
AArch64_FeatureSME = 121,
AArch64_FeatureSMEF64 = 122,
AArch64_FeatureSMEI64 = 123,
AArch64_FeatureSPE = 124,
AArch64_FeatureSPE_EEF = 125,
AArch64_FeatureSSBS = 126,
AArch64_FeatureSVE = 127,
AArch64_FeatureSVE2 = 128,
AArch64_FeatureSVE2AES = 129,
AArch64_FeatureSVE2BitPerm = 130,
AArch64_FeatureSVE2SHA3 = 131,
AArch64_FeatureSVE2SM4 = 132,
AArch64_FeatureSlowMisaligned128Store = 133,
AArch64_FeatureSlowPaired128 = 134,
AArch64_FeatureSlowSTRQro = 135,
AArch64_FeatureSpecRestrict = 136,
AArch64_FeatureStreamingSVE = 137,
AArch64_FeatureStrictAlign = 138,
AArch64_FeatureTLB_RMI = 139,
AArch64_FeatureTME = 140,
AArch64_FeatureTRACEV8_4 = 141,
AArch64_FeatureTRBE = 142,
AArch64_FeatureTaggedGlobals = 143,
AArch64_FeatureUseEL1ForTP = 144,
AArch64_FeatureUseEL2ForTP = 145,
AArch64_FeatureUseEL3ForTP = 146,
AArch64_FeatureUseRSqrt = 147,
AArch64_FeatureUseScalarIncVL = 148,
AArch64_FeatureVH = 149,
AArch64_FeatureWFxT = 150,
AArch64_FeatureXS = 151,
AArch64_FeatureZCRegMove = 152,
AArch64_FeatureZCZeroing = 153,
AArch64_FeatureZCZeroingFPWorkaround = 154,
AArch64_FeatureZCZeroingGP = 155,
AArch64_HasV8_0aOps = 156,
AArch64_HasV8_0rOps = 157,
AArch64_HasV8_1aOps = 158,
AArch64_HasV8_2aOps = 159,
AArch64_HasV8_3aOps = 160,
AArch64_HasV8_4aOps = 161,
AArch64_HasV8_5aOps = 162,
AArch64_HasV8_6aOps = 163,
AArch64_HasV8_7aOps = 164,
AArch64_HasV8_8aOps = 165,
AArch64_HasV9_0aOps = 166,
AArch64_HasV9_1aOps = 167,
AArch64_HasV9_2aOps = 168,
AArch64_HasV9_3aOps = 169,
AArch64_TuneA35 = 170,
AArch64_TuneA53 = 171,
AArch64_TuneA55 = 172,
AArch64_TuneA57 = 173,
AArch64_TuneA64FX = 174,
AArch64_TuneA65 = 175,
AArch64_TuneA72 = 176,
AArch64_TuneA73 = 177,
AArch64_TuneA75 = 178,
AArch64_TuneA76 = 179,
AArch64_TuneA77 = 180,
AArch64_TuneA78 = 181,
AArch64_TuneA78C = 182,
AArch64_TuneA510 = 183,
AArch64_TuneA710 = 184,
AArch64_TuneAmpere1 = 185,
AArch64_TuneAppleA7 = 186,
AArch64_TuneAppleA10 = 187,
AArch64_TuneAppleA11 = 188,
AArch64_TuneAppleA12 = 189,
AArch64_TuneAppleA13 = 190,
AArch64_TuneAppleA14 = 191,
AArch64_TuneCarmel = 192,
AArch64_TuneExynosM3 = 193,
AArch64_TuneExynosM4 = 194,
AArch64_TuneFalkor = 195,
AArch64_TuneKryo = 196,
AArch64_TuneNeoverse512TVB = 197,
AArch64_TuneNeoverseE1 = 198,
AArch64_TuneNeoverseN1 = 199,
AArch64_TuneNeoverseN2 = 200,
AArch64_TuneNeoverseV1 = 201,
AArch64_TuneR82 = 202,
AArch64_TuneSaphira = 203,
AArch64_TuneTSV110 = 204,
AArch64_TuneThunderX = 205,
AArch64_TuneThunderX2T99 = 206,
AArch64_TuneThunderX3T110 = 207,
AArch64_TuneThunderXT81 = 208,
AArch64_TuneThunderXT83 = 209,
AArch64_TuneThunderXT88 = 210,
AArch64_TuneX1 = 211,
AArch64_TuneX2 = 212,
AArch64_NumSubtargetFeatures = 213
AArch64_FeatureAll = 4,
AArch64_FeatureAltFPCmp = 5,
AArch64_FeatureAlternateSExtLoadCVTF32Pattern = 6,
AArch64_FeatureAppleA7SysReg = 7,
AArch64_FeatureArithmeticBccFusion = 8,
AArch64_FeatureArithmeticCbzFusion = 9,
AArch64_FeatureAscendStoreAddress = 10,
AArch64_FeatureB16B16 = 11,
AArch64_FeatureBF16 = 12,
AArch64_FeatureBRBE = 13,
AArch64_FeatureBalanceFPOps = 14,
AArch64_FeatureBranchTargetId = 15,
AArch64_FeatureCCIDX = 16,
AArch64_FeatureCCPP = 17,
AArch64_FeatureCLRBHB = 18,
AArch64_FeatureCONTEXTIDREL2 = 19,
AArch64_FeatureCRC = 20,
AArch64_FeatureCSSC = 21,
AArch64_FeatureCacheDeepPersist = 22,
AArch64_FeatureCallSavedX8 = 23,
AArch64_FeatureCallSavedX9 = 24,
AArch64_FeatureCallSavedX10 = 25,
AArch64_FeatureCallSavedX11 = 26,
AArch64_FeatureCallSavedX12 = 27,
AArch64_FeatureCallSavedX13 = 28,
AArch64_FeatureCallSavedX14 = 29,
AArch64_FeatureCallSavedX15 = 30,
AArch64_FeatureCallSavedX18 = 31,
AArch64_FeatureCmpBccFusion = 32,
AArch64_FeatureComplxNum = 33,
AArch64_FeatureCrypto = 34,
AArch64_FeatureCustomCheapAsMoveHandling = 35,
AArch64_FeatureD128 = 36,
AArch64_FeatureDIT = 37,
AArch64_FeatureDisableLatencySchedHeuristic = 38,
AArch64_FeatureDotProd = 39,
AArch64_FeatureEL2VMSA = 40,
AArch64_FeatureEL3 = 41,
AArch64_FeatureETE = 42,
AArch64_FeatureEnableSelectOptimize = 43,
AArch64_FeatureEnhancedCounterVirtualization = 44,
AArch64_FeatureExperimentalZeroingPseudos = 45,
AArch64_FeatureExynosCheapAsMoveHandling = 46,
AArch64_FeatureFMV = 47,
AArch64_FeatureFP16FML = 48,
AArch64_FeatureFPARMv8 = 49,
AArch64_FeatureFRInt3264 = 50,
AArch64_FeatureFineGrainedTraps = 51,
AArch64_FeatureFixCortexA53_835769 = 52,
AArch64_FeatureFlagM = 53,
AArch64_FeatureForce32BitJumpTables = 54,
AArch64_FeatureFullFP16 = 55,
AArch64_FeatureFuseAES = 56,
AArch64_FeatureFuseAddress = 57,
AArch64_FeatureFuseAdrpAdd = 58,
AArch64_FeatureFuseArithmeticLogic = 59,
AArch64_FeatureFuseCCSelect = 60,
AArch64_FeatureFuseCryptoEOR = 61,
AArch64_FeatureFuseLiterals = 62,
AArch64_FeatureHBC = 63,
AArch64_FeatureHCX = 64,
AArch64_FeatureHardenSlsBlr = 65,
AArch64_FeatureHardenSlsNoComdat = 66,
AArch64_FeatureHardenSlsRetBr = 67,
AArch64_FeatureITE = 68,
AArch64_FeatureJS = 69,
AArch64_FeatureLOR = 70,
AArch64_FeatureLS64 = 71,
AArch64_FeatureLSE = 72,
AArch64_FeatureLSE2 = 73,
AArch64_FeatureLSE128 = 74,
AArch64_FeatureLSLFast = 75,
AArch64_FeatureMEC = 76,
AArch64_FeatureMOPS = 77,
AArch64_FeatureMPAM = 78,
AArch64_FeatureMTE = 79,
AArch64_FeatureMatMulFP32 = 80,
AArch64_FeatureMatMulFP64 = 81,
AArch64_FeatureMatMulInt8 = 82,
AArch64_FeatureNEON = 83,
AArch64_FeatureNMI = 84,
AArch64_FeatureNV = 85,
AArch64_FeatureNoBTIAtReturnTwice = 86,
AArch64_FeatureNoNegativeImmediates = 87,
AArch64_FeatureNoZCZeroingFP = 88,
AArch64_FeatureOutlineAtomics = 89,
AArch64_FeaturePAN = 90,
AArch64_FeaturePAN_RWV = 91,
AArch64_FeaturePAuth = 92,
AArch64_FeaturePRFM_SLC = 93,
AArch64_FeaturePerfMon = 94,
AArch64_FeaturePostRAScheduler = 95,
AArch64_FeaturePredRes = 96,
AArch64_FeaturePredictableSelectIsExpensive = 97,
AArch64_FeaturePsUAO = 98,
AArch64_FeatureRAS = 99,
AArch64_FeatureRASv2 = 100,
AArch64_FeatureRCPC = 101,
AArch64_FeatureRCPC3 = 102,
AArch64_FeatureRCPC_IMMO = 103,
AArch64_FeatureRDM = 104,
AArch64_FeatureRME = 105,
AArch64_FeatureRandGen = 106,
AArch64_FeatureReserveX1 = 107,
AArch64_FeatureReserveX2 = 108,
AArch64_FeatureReserveX3 = 109,
AArch64_FeatureReserveX4 = 110,
AArch64_FeatureReserveX5 = 111,
AArch64_FeatureReserveX6 = 112,
AArch64_FeatureReserveX7 = 113,
AArch64_FeatureReserveX9 = 114,
AArch64_FeatureReserveX10 = 115,
AArch64_FeatureReserveX11 = 116,
AArch64_FeatureReserveX12 = 117,
AArch64_FeatureReserveX13 = 118,
AArch64_FeatureReserveX14 = 119,
AArch64_FeatureReserveX15 = 120,
AArch64_FeatureReserveX18 = 121,
AArch64_FeatureReserveX20 = 122,
AArch64_FeatureReserveX21 = 123,
AArch64_FeatureReserveX22 = 124,
AArch64_FeatureReserveX23 = 125,
AArch64_FeatureReserveX24 = 126,
AArch64_FeatureReserveX25 = 127,
AArch64_FeatureReserveX26 = 128,
AArch64_FeatureReserveX27 = 129,
AArch64_FeatureReserveX28 = 130,
AArch64_FeatureReserveX30 = 131,
AArch64_FeatureSB = 132,
AArch64_FeatureSEL2 = 133,
AArch64_FeatureSHA2 = 134,
AArch64_FeatureSHA3 = 135,
AArch64_FeatureSM4 = 136,
AArch64_FeatureSME = 137,
AArch64_FeatureSME2 = 138,
AArch64_FeatureSME2p1 = 139,
AArch64_FeatureSMEF16F16 = 140,
AArch64_FeatureSMEF64F64 = 141,
AArch64_FeatureSMEI16I64 = 142,
AArch64_FeatureSPE = 143,
AArch64_FeatureSPECRES2 = 144,
AArch64_FeatureSPE_EEF = 145,
AArch64_FeatureSSBS = 146,
AArch64_FeatureSVE = 147,
AArch64_FeatureSVE2 = 148,
AArch64_FeatureSVE2AES = 149,
AArch64_FeatureSVE2BitPerm = 150,
AArch64_FeatureSVE2SHA3 = 151,
AArch64_FeatureSVE2SM4 = 152,
AArch64_FeatureSVE2p1 = 153,
AArch64_FeatureSlowMisaligned128Store = 154,
AArch64_FeatureSlowPaired128 = 155,
AArch64_FeatureSlowSTRQro = 156,
AArch64_FeatureSpecRestrict = 157,
AArch64_FeatureStrictAlign = 158,
AArch64_FeatureTHE = 159,
AArch64_FeatureTLB_RMI = 160,
AArch64_FeatureTME = 161,
AArch64_FeatureTRACEV8_4 = 162,
AArch64_FeatureTRBE = 163,
AArch64_FeatureTaggedGlobals = 164,
AArch64_FeatureUseEL1ForTP = 165,
AArch64_FeatureUseEL2ForTP = 166,
AArch64_FeatureUseEL3ForTP = 167,
AArch64_FeatureUseRSqrt = 168,
AArch64_FeatureUseScalarIncVL = 169,
AArch64_FeatureVH = 170,
AArch64_FeatureWFxT = 171,
AArch64_FeatureXS = 172,
AArch64_FeatureZCRegMove = 173,
AArch64_FeatureZCZeroing = 174,
AArch64_FeatureZCZeroingFPWorkaround = 175,
AArch64_FeatureZCZeroingGP = 176,
AArch64_HasV8_0aOps = 177,
AArch64_HasV8_0rOps = 178,
AArch64_HasV8_1aOps = 179,
AArch64_HasV8_2aOps = 180,
AArch64_HasV8_3aOps = 181,
AArch64_HasV8_4aOps = 182,
AArch64_HasV8_5aOps = 183,
AArch64_HasV8_6aOps = 184,
AArch64_HasV8_7aOps = 185,
AArch64_HasV8_8aOps = 186,
AArch64_HasV8_9aOps = 187,
AArch64_HasV9_0aOps = 188,
AArch64_HasV9_1aOps = 189,
AArch64_HasV9_2aOps = 190,
AArch64_HasV9_3aOps = 191,
AArch64_HasV9_4aOps = 192,
AArch64_TuneA35 = 193,
AArch64_TuneA53 = 194,
AArch64_TuneA55 = 195,
AArch64_TuneA57 = 196,
AArch64_TuneA64FX = 197,
AArch64_TuneA65 = 198,
AArch64_TuneA72 = 199,
AArch64_TuneA73 = 200,
AArch64_TuneA75 = 201,
AArch64_TuneA76 = 202,
AArch64_TuneA77 = 203,
AArch64_TuneA78 = 204,
AArch64_TuneA78C = 205,
AArch64_TuneA510 = 206,
AArch64_TuneA710 = 207,
AArch64_TuneA715 = 208,
AArch64_TuneAmpere1 = 209,
AArch64_TuneAmpere1A = 210,
AArch64_TuneAppleA7 = 211,
AArch64_TuneAppleA10 = 212,
AArch64_TuneAppleA11 = 213,
AArch64_TuneAppleA12 = 214,
AArch64_TuneAppleA13 = 215,
AArch64_TuneAppleA14 = 216,
AArch64_TuneAppleA15 = 217,
AArch64_TuneAppleA16 = 218,
AArch64_TuneCarmel = 219,
AArch64_TuneExynosM3 = 220,
AArch64_TuneExynosM4 = 221,
AArch64_TuneFalkor = 222,
AArch64_TuneKryo = 223,
AArch64_TuneNeoverse512TVB = 224,
AArch64_TuneNeoverseE1 = 225,
AArch64_TuneNeoverseN1 = 226,
AArch64_TuneNeoverseN2 = 227,
AArch64_TuneNeoverseV1 = 228,
AArch64_TuneNeoverseV2 = 229,
AArch64_TuneR82 = 230,
AArch64_TuneSaphira = 231,
AArch64_TuneTSV110 = 232,
AArch64_TuneThunderX = 233,
AArch64_TuneThunderX2T99 = 234,
AArch64_TuneThunderX3T110 = 235,
AArch64_TuneThunderXT81 = 236,
AArch64_TuneThunderXT83 = 237,
AArch64_TuneThunderXT88 = 238,
AArch64_TuneX1 = 239,
AArch64_TuneX2 = 240,
AArch64_TuneX3 = 241,
AArch64_NumSubtargetFeatures = 242
};
#endif // GET_SUBTARGETINFO_ENUM

7579
arch/AArch64/AArch64GenSystemOperands.inc
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arch/AArch64/AArch64GenSystemOperands_enum.inc
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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
enum PStateValues {
AArch64PState_SPSel = 5,
AArch64PState_DAIFSet = 30,
AArch64PState_DAIFClr = 31,
AArch64PState_PAN = 4,
AArch64PState_UAO = 3,
AArch64PState_DIT = 26,
AArch64PState_SSBS = 25,
AArch64PState_TCO = 28,
};
enum ExactFPImmValues {
AArch64ExactFPImm_zero = 0,
AArch64ExactFPImm_half = 1,
AArch64ExactFPImm_one = 2,
AArch64ExactFPImm_two = 3,
};

5175
arch/AArch64/AArch64InstPrinter.c
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333
arch/AArch64/AArch64InstPrinter.h
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@ -1,9 +1,22 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@ -11,18 +24,316 @@
//
//===----------------------------------------------------------------------===//
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
#ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H
#define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H
#ifndef CS_LLVM_AARCH64INSTPRINTER_H
#define CS_LLVM_AARCH64INSTPRINTER_H
#include <capstone/platform.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "AArch64Mapping.h"
#include "../../MCInst.h"
#include "../../MCInstPrinter.h"
#include "../../MCRegisterInfo.h"
#include "../../SStream.h"
#include "../../utils.h"
void AArch64_printInst(MCInst *MI, SStream *O, void *);
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
#define CHAR(c) #c[0]
void AArch64_post_printer(csh handle, cs_insn *pub_insn, char *insn_asm, MCInst *mci);
void printInst(MCInst *MI, uint64_t Address, const char *Annot,
SStream *O);
void printRegName(SStream *OS, unsigned Reg);
void printRegNameAlt(SStream *OS, unsigned Reg, unsigned AltIdx);
// Autogenerated by tblgen.
const char *getRegName(unsigned Reg);
bool printSysAlias(MCInst *MI, SStream *O);
bool printSyspAlias(MCInst *MI, SStream *O);
bool printRangePrefetchAlias(MCInst *MI, SStream *O, const char *Annot);
// Operand printers
void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printImm(MCInst *MI, unsigned OpNo, SStream *O);
void printImmHex(MCInst *MI, unsigned OpNo, SStream *O);
#define DECLARE_printSImm(Size) \
void CONCAT(printSImm, Size)(MCInst * MI, unsigned OpNo, SStream *O);
DECLARE_printSImm(16);
DECLARE_printSImm(8);
#endif
#define DECLARE_printImmSVE(T) \
void CONCAT(printImmSVE, T)(T Val, SStream *O);
DECLARE_printImmSVE(int16_t);
DECLARE_printImmSVE(int8_t);
DECLARE_printImmSVE(int64_t);
DECLARE_printImmSVE(int32_t);
DECLARE_printImmSVE(uint16_t);
DECLARE_printImmSVE(uint8_t);
DECLARE_printImmSVE(uint64_t);
DECLARE_printImmSVE(uint32_t);
void printPostIncOperand(MCInst *MI, unsigned OpNo, unsigned Imm, SStream *O);
#define DEFINE_printPostIncOperand(Amount) \
static inline void CONCAT(printPostIncOperand, Amount)(MCInst * MI, unsigned OpNo, \
SStream *O) \
{ \
add_cs_detail(MI, CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), OpNo, Amount); \
printPostIncOperand(MI, OpNo, Amount, O); \
}
DEFINE_printPostIncOperand(64);
DEFINE_printPostIncOperand(32);
DEFINE_printPostIncOperand(16);
DEFINE_printPostIncOperand(8);
DEFINE_printPostIncOperand(1);
DEFINE_printPostIncOperand(4);
DEFINE_printPostIncOperand(2);
DEFINE_printPostIncOperand(48);
DEFINE_printPostIncOperand(24);
DEFINE_printPostIncOperand(3);
DEFINE_printPostIncOperand(12);
DEFINE_printPostIncOperand(6);
void printVRegOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printSysCROperand(MCInst *MI, unsigned OpNo, SStream *O);
void printAddSubImm(MCInst *MI, unsigned OpNum, SStream *O);
#define DECLARE_printLogicalImm(T) \
void CONCAT(printLogicalImm, T)(MCInst * MI, unsigned OpNum, SStream *O);
DECLARE_printLogicalImm(int64_t);
DECLARE_printLogicalImm(int32_t);
DECLARE_printLogicalImm(int8_t);
DECLARE_printLogicalImm(int16_t);
void printShifter(MCInst *MI, unsigned OpNum, SStream *O);
void printShiftedRegister(MCInst *MI, unsigned OpNum, SStream *O);
void printExtendedRegister(MCInst *MI, unsigned OpNum, SStream *O);
void printArithExtend(MCInst *MI, unsigned OpNum, SStream *O);
void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind,
unsigned Width);
void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind,
unsigned Width);
#define DEFINE_printMemExtend(SrcRegKind, Width) \
static inline void CONCAT(printMemExtend, CONCAT(SrcRegKind, Width))( \
MCInst * MI, unsigned OpNum, SStream *O) \
{ \
add_cs_detail(MI, \
CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, \
SrcRegKind), \
Width), \
OpNum, CHAR(SrcRegKind), Width); \
printMemExtend(MI, OpNum, O, CHAR(SrcRegKind), Width); \
}
DEFINE_printMemExtend(w, 8);
DEFINE_printMemExtend(x, 8);
DEFINE_printMemExtend(w, 64);
DEFINE_printMemExtend(x, 64);
DEFINE_printMemExtend(w, 16);
DEFINE_printMemExtend(x, 16);
DEFINE_printMemExtend(w, 128);
DEFINE_printMemExtend(x, 128);
DEFINE_printMemExtend(w, 32);
DEFINE_printMemExtend(x, 32);
#define DECLARE_printRegWithShiftExtend(SignedExtend, ExtWidth, SrcRegKind, \
Suffix) \
void CONCAT( \
printRegWithShiftExtend, \
CONCAT(SignedExtend, CONCAT(ExtWidth, CONCAT(SrcRegKind, Suffix))))( \
MCInst * MI, unsigned OpNum, SStream *O);
DECLARE_printRegWithShiftExtend(false, 8, x, d);
DECLARE_printRegWithShiftExtend(true, 8, w, d);
DECLARE_printRegWithShiftExtend(false, 8, w, d);
DECLARE_printRegWithShiftExtend(false, 8, x, 0);
DECLARE_printRegWithShiftExtend(true, 8, w, s);
DECLARE_printRegWithShiftExtend(false, 8, w, s);
DECLARE_printRegWithShiftExtend(false, 64, x, d);
DECLARE_printRegWithShiftExtend(true, 64, w, d);
DECLARE_printRegWithShiftExtend(false, 64, w, d);
DECLARE_printRegWithShiftExtend(false, 64, x, 0);
DECLARE_printRegWithShiftExtend(true, 64, w, s);
DECLARE_printRegWithShiftExtend(false, 64, w, s);
DECLARE_printRegWithShiftExtend(false, 16, x, d);
DECLARE_printRegWithShiftExtend(true, 16, w, d);
DECLARE_printRegWithShiftExtend(false, 16, w, d);
DECLARE_printRegWithShiftExtend(false, 16, x, 0);
DECLARE_printRegWithShiftExtend(true, 16, w, s);
DECLARE_printRegWithShiftExtend(false, 16, w, s);
DECLARE_printRegWithShiftExtend(false, 32, x, d);
DECLARE_printRegWithShiftExtend(true, 32, w, d);
DECLARE_printRegWithShiftExtend(false, 32, w, d);
DECLARE_printRegWithShiftExtend(false, 32, x, 0);
DECLARE_printRegWithShiftExtend(true, 32, w, s);
DECLARE_printRegWithShiftExtend(false, 32, w, s);
DECLARE_printRegWithShiftExtend(false, 8, x, s);
DECLARE_printRegWithShiftExtend(false, 16, x, s);
DECLARE_printRegWithShiftExtend(false, 32, x, s);
DECLARE_printRegWithShiftExtend(false, 64, x, s);
DECLARE_printRegWithShiftExtend(false, 128, x, 0);
void printCondCode(MCInst *MI, unsigned OpNum, SStream *O);
void printInverseCondCode(MCInst *MI, unsigned OpNum, SStream *O);
void printAlignedLabel(MCInst *MI, uint64_t Address, unsigned OpNum,
SStream *O);
void printUImm12Offset(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O);
void printAMIndexedWB(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O);
#define DEFINE_printUImm12Offset(Scale) \
static inline void CONCAT(printUImm12Offset, Scale)(MCInst * MI, unsigned OpNum, \
SStream *O) \
{ \
add_cs_detail( \
MI, CONCAT(AArch64_OP_GROUP_UImm12Offset, Scale), \
OpNum, Scale); \
printUImm12Offset(MI, OpNum, Scale, O); \
}
DEFINE_printUImm12Offset(1);
DEFINE_printUImm12Offset(8);
DEFINE_printUImm12Offset(2);
DEFINE_printUImm12Offset(16);
DEFINE_printUImm12Offset(4);
void printAMNoIndex(MCInst *MI, unsigned OpNum, SStream *O);
#define DECLARE_printImmScale(Scale) \
void CONCAT(printImmScale, Scale)(MCInst * MI, unsigned OpNum, SStream *O);
DECLARE_printImmScale(8);
DECLARE_printImmScale(2);
DECLARE_printImmScale(4);
DECLARE_printImmScale(16);
DECLARE_printImmScale(32);
DECLARE_printImmScale(3);
#define DECLARE_printImmRangeScale(Scale, Offset) \
void CONCAT(printImmRangeScale, CONCAT(Scale, Offset))( \
MCInst * MI, unsigned OpNum, SStream *O);
DECLARE_printImmRangeScale(2, 1);
DECLARE_printImmRangeScale(4, 3);
#define DECLARE_printPrefetchOp(IsSVEPrefetch) \
void CONCAT(printPrefetchOp, IsSVEPrefetch)( \
MCInst * MI, unsigned OpNum, SStream *O);
DECLARE_printPrefetchOp(true);
DECLARE_printPrefetchOp(false);
void printRPRFMOperand(MCInst *MI, unsigned OpNum, SStream *O);
void printPSBHintOp(MCInst *MI, unsigned OpNum, SStream *O);
void printBTIHintOp(MCInst *MI, unsigned OpNum, SStream *O);
void printVectorList(MCInst *MI, unsigned OpNum, SStream *O,
const char *LayoutSuffix);
void printMatrixTileList(MCInst *MI, unsigned OpNum, SStream *O);
/// (i.e. attached to the instruction rather than the registers).
/// Print a list of vector registers where the type suffix is implicit
void printImplicitlyTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O);
#define DECLARE_printTypedVectorList(NumLanes, LaneKind) \
void CONCAT(printTypedVectorList, CONCAT(NumLanes, LaneKind))( \
MCInst * MI, unsigned OpNum, SStream *O);
DECLARE_printTypedVectorList(0, b);
DECLARE_printTypedVectorList(0, d);
DECLARE_printTypedVectorList(0, h);
DECLARE_printTypedVectorList(0, s);
DECLARE_printTypedVectorList(0, q);
DECLARE_printTypedVectorList(16, b);
DECLARE_printTypedVectorList(1, d);
DECLARE_printTypedVectorList(2, d);
DECLARE_printTypedVectorList(2, s);
DECLARE_printTypedVectorList(4, h);
DECLARE_printTypedVectorList(4, s);
DECLARE_printTypedVectorList(8, b);
DECLARE_printTypedVectorList(8, h);
#define DECLARE_printVectorIndex(Scale) \
void CONCAT(printVectorIndex, \
Scale)(MCInst * MI, unsigned OpNum, SStream *O);
DECLARE_printVectorIndex(1);
DECLARE_printVectorIndex(8);
void printMatrixIndex(MCInst *MI, unsigned OpNum, SStream *O);
void printAdrLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O);
void printAdrpLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O);
void printBarrierOption(MCInst *MI, unsigned OpNum, SStream *O);
void printBarriernXSOption(MCInst *MI, unsigned OpNum, SStream *O);
void printMSRSystemRegister(MCInst *MI, unsigned OpNum, SStream *O);
void printMRSSystemRegister(MCInst *MI, unsigned OpNum, SStream *O);
void printSystemPStateField(MCInst *MI, unsigned OpNum, SStream *O);
void printSIMDType10Operand(MCInst *MI, unsigned OpNum, SStream *O);
#define DECLARE_printPredicateAsCounter(EltSize) \
void CONCAT(printPredicateAsCounter, EltSize)(MCInst * MI, unsigned OpNum, \
SStream *O);
DECLARE_printPredicateAsCounter(8);
DECLARE_printPredicateAsCounter(64);
DECLARE_printPredicateAsCounter(16);
DECLARE_printPredicateAsCounter(32);
DECLARE_printPredicateAsCounter(0);
#define DECLARE_printGPRSeqPairsClassOperand(size) \
void CONCAT(printGPRSeqPairsClassOperand, \
size)(MCInst * MI, unsigned OpNum, SStream *O);
DECLARE_printGPRSeqPairsClassOperand(32);
DECLARE_printGPRSeqPairsClassOperand(64);
#define DECLARE_printImm8OptLsl(T) \
void CONCAT(printImm8OptLsl, T)(MCInst * MI, unsigned OpNum, SStream *O);
DECLARE_printImm8OptLsl(int16_t);
DECLARE_printImm8OptLsl(int8_t);
DECLARE_printImm8OptLsl(int64_t);
DECLARE_printImm8OptLsl(int32_t);
DECLARE_printImm8OptLsl(uint16_t);
DECLARE_printImm8OptLsl(uint8_t);
DECLARE_printImm8OptLsl(uint64_t);
DECLARE_printImm8OptLsl(uint32_t);
#define DECLARE_printSVELogicalImm(T) \
void CONCAT(printSVELogicalImm, T)(MCInst * MI, unsigned OpNum, SStream *O);
DECLARE_printSVELogicalImm(int16_t);
DECLARE_printSVELogicalImm(int32_t);
DECLARE_printSVELogicalImm(int64_t);
void printSVEPattern(MCInst *MI, unsigned OpNum, SStream *O);
void printSVEVecLenSpecifier(MCInst *MI, unsigned OpNum, SStream *O);
#define DECLARE_printMatrixTileVector(IsVertical) \
void CONCAT(printMatrixTileVector, \
IsVertical)(MCInst * MI, unsigned OpNum, SStream *O);
DECLARE_printMatrixTileVector(0);
DECLARE_printMatrixTileVector(1);
void printMatrixTile(MCInst *MI, unsigned OpNum, SStream *O);
#define DECLARE_printMatrix(EltSize) \
void CONCAT(printMatrix, EltSize)(MCInst * MI, unsigned OpNum, SStream *O);
DECLARE_printMatrix(64);
DECLARE_printMatrix(32);
DECLARE_printMatrix(16);
DECLARE_printMatrix(0);
void printSVCROp(MCInst *MI, unsigned OpNum, SStream *O);
#define DECLARE_printSVERegOp(char) \
void CONCAT(printSVERegOp, char)(MCInst * MI, unsigned OpNum, \
SStream *O);
DECLARE_printSVERegOp(b);
DECLARE_printSVERegOp(d);
DECLARE_printSVERegOp(h);
DECLARE_printSVERegOp(s);
DECLARE_printSVERegOp(0);
DECLARE_printSVERegOp(q);
void printGPR64as32(MCInst *MI, unsigned OpNum, SStream *O);
void printGPR64x8(MCInst *MI, unsigned OpNum, SStream *O);
void printSyspXzrPair(MCInst *MI, unsigned OpNum, SStream *O);
#define DECLARE_printZPRasFPR(Width) \
void CONCAT(printZPRasFPR, Width)(MCInst * MI, unsigned OpNum, SStream *O);
DECLARE_printZPRasFPR(8);
DECLARE_printZPRasFPR(64);
DECLARE_printZPRasFPR(16);
DECLARE_printZPRasFPR(32);
DECLARE_printZPRasFPR(128);
#define DECLARE_printExactFPImm(ImmIs0, ImmIs1) \
void CONCAT(printExactFPImm, CONCAT(ImmIs0, ImmIs1))( \
MCInst * MI, unsigned OpNum, SStream *O);
DECLARE_printExactFPImm(AArch64ExactFPImm_half, AArch64ExactFPImm_one);
DECLARE_printExactFPImm(AArch64ExactFPImm_zero, AArch64ExactFPImm_one);
DECLARE_printExactFPImm(AArch64ExactFPImm_half, AArch64ExactFPImm_two);
;
// end namespace llvm
#endif // LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H

21
arch/AArch64/AArch64Linkage.h Normal file
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@ -0,0 +1,21 @@
/* Capstone Disassembly Engine */
/* By Rot127 <unisono@quyllur.org> 2022-2023 */
#ifndef CS_AARCH64_LINKAGE_H
#define CS_AARCH64_LINKAGE_H
// Function defintions to call static LLVM functions.
#include "../../MCDisassembler.h"
#include "../../MCInst.h"
#include "../../MCRegisterInfo.h"
#include "../../SStream.h"
#include "capstone/capstone.h"
DecodeStatus AArch64_LLVM_getInstruction(csh handle, const uint8_t *Bytes, size_t ByteLen,
MCInst *MI, uint16_t *Size, uint64_t Address,
void *Info);
const char *AArch64_LLVM_getRegisterName(unsigned RegNo, unsigned AltIdx);
void AArch64_LLVM_printInstruction(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info);
#endif // CS_AARCH64_LINKAGE_H

2941
arch/AArch64/AArch64Mapping.c
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arch/AArch64/AArch64Mapping.h
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/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
#ifndef CS_ARM64_MAP_H
#define CS_ARM64_MAP_H
#ifndef CS_AARCH64_MAP_H
#define CS_AARCH64_MAP_H
#include "capstone/capstone.h"
#include "../../MCInst.h"
#include "../../SStream.h"
#define ARR_SIZE(a) (sizeof(a)/sizeof(a[0]))
typedef enum {
#include "AArch64GenCSOpGroup.inc"
} aarch64_op_group;
// return name of regiser in friendly string
const char *AArch64_reg_name(csh handle, unsigned int reg);
@ -18,26 +24,51 @@ const char *AArch64_insn_name(csh handle, unsigned int id);
const char *AArch64_group_name(csh handle, unsigned int id);
// map instruction name to public instruction ID
arm64_insn AArch64_map_insn(const char *name);
void AArch64_reg_access(const cs_insn *insn, cs_regs regs_read,
uint8_t *regs_read_count, cs_regs regs_write,
uint8_t *regs_write_count);
// map internal vregister to public register
arm64_reg AArch64_map_vregister(unsigned int r);
void AArch64_add_cs_detail(MCInst *MI, int /* aarch64_op_group */ op_group,
va_list args);
arm64_sys_op AArch64_map_sys_op(const char *name);
static inline void add_cs_detail(MCInst *MI,
int /* aarch64_op_group */ op_group, ...)
{
if (!MI->flat_insn->detail)
return;
va_list args;
va_start(args, op_group);
AArch64_add_cs_detail(MI, op_group, args);
va_end(args);
}
void arm64_op_addReg(MCInst *MI, int reg);
void AArch64_init_mri(MCRegisterInfo *MRI);
void arm64_op_addVectorArrSpecifier(MCInst * MI, int sp);
void AArch64_init_cs_detail(MCInst *MI);
void arm64_op_addFP(MCInst *MI, float fp);
void AArch64_set_instr_map_data(MCInst *MI);
void arm64_op_addImm(MCInst *MI, int64_t imm);
bool AArch64_getInstruction(csh handle, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address,
void *info);
const uint8_t *AArch64_get_op_access(cs_struct *h, unsigned int id);
void AArch64_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info);
void AArch64_reg_access(const cs_insn *insn,
cs_regs regs_read, uint8_t *regs_read_count,
cs_regs regs_write, uint8_t *regs_write_count);
void AArch64_set_detail_op_reg(MCInst *MI, unsigned OpNum, aarch64_reg Reg);
void AArch64_set_detail_op_imm(MCInst *MI, unsigned OpNum, aarch64_op_type ImmType,
int64_t Imm);
void AArch64_set_detail_op_imm_range(MCInst *MI, unsigned OpNum,
int64_t FirstImm, int64_t offset);
void AArch64_set_detail_op_mem(MCInst *MI, unsigned OpNum, uint64_t Val);
void AArch64_set_detail_op_mem_offset(MCInst *MI, unsigned OpNum, uint64_t Val);
void AArch64_set_detail_shift_ext(MCInst *MI, unsigned OpNum, bool SignExtend,
bool DoShift, unsigned ExtWidth, char SrcRegKind);
void AArch64_set_detail_op_float(MCInst *MI, unsigned OpNum, float Val);
void AArch64_set_detail_op_sys(MCInst *MI, unsigned OpNum, aarch64_sysop sys_op, aarch64_op_type type);
void AArch64_set_detail_op_sme(MCInst *MI, unsigned OpNum, aarch64_sme_op_part part, AArch64Layout_VectorLayout vas, ...);
void AArch64_insert_detail_op_reg_at(MCInst *MI, unsigned index, aarch64_reg Reg, cs_ac_type access);
void AArch64_insert_detail_op_float_at(MCInst *MI, unsigned index, double val, cs_ac_type access);
void AArch64_insert_detail_op_imm_at(MCInst *MI, unsigned index, int64_t Imm);
void AArch64_add_vas(MCInst *MI, const SStream *OS);
#endif

37790
arch/AArch64/AArch64MappingInsn.inc
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1282
arch/AArch64/AArch64MappingInsnName.inc
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File diff suppressed because it is too large Load Diff

26994
arch/AArch64/AArch64MappingInsnOp.inc
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File diff suppressed because it is too large Load Diff

14
arch/AArch64/AArch64Module.c
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@ -1,11 +1,10 @@
/* Capstone Disassembly Engine */
/* By Dang Hoang Vu <danghvu@gmail.com> 2013 */
#ifdef CAPSTONE_HAS_ARM64
#ifdef CAPSTONE_HAS_AARCH64
#include "../../utils.h"
#include "../../MCRegisterInfo.h"
#include "AArch64Disassembler.h"
#include "AArch64InstPrinter.h"
#include "AArch64Mapping.h"
#include "AArch64Module.h"
@ -15,8 +14,8 @@ cs_err AArch64_global_init(cs_struct *ud)
MCRegisterInfo *mri;
mri = cs_mem_malloc(sizeof(*mri));
AArch64_init(mri);
ud->printer = AArch64_printInst;
AArch64_init_mri(mri);
ud->printer = AArch64_printer;
ud->printer_info = mri;
ud->getinsn_info = mri;
ud->disasm = AArch64_getInstruction;
@ -24,7 +23,7 @@ cs_err AArch64_global_init(cs_struct *ud)
ud->insn_id = AArch64_get_insn_id;
ud->insn_name = AArch64_insn_name;
ud->group_name = AArch64_group_name;
ud->post_printer = AArch64_post_printer;
ud->post_printer = NULL;
#ifndef CAPSTONE_DIET
ud->reg_access = AArch64_reg_access;
#endif
@ -34,8 +33,11 @@ cs_err AArch64_global_init(cs_struct *ud)
cs_err AArch64_option(cs_struct *handle, cs_opt_type type, size_t value)
{
if (type == CS_OPT_SYNTAX)
handle->syntax |= (int) value;
if (type == CS_OPT_MODE) {
handle->mode = (cs_mode)value;
handle->mode |= (cs_mode)value;
}
return CS_ERR_OK;

1
arch/ARM/ARMBaseInfo.h
View File

@ -22,7 +22,6 @@
#include <string.h>
#include "../../MCInstPrinter.h"
#include "../../utils.h"
#include "capstone/arm.h"
#define GET_INSTRINFO_ENUM

15
arch/TriCore/TriCoreMapping.c
View File

@ -124,20 +124,7 @@ const char *TriCore_group_name(csh handle, unsigned int id)
}
#ifndef CAPSTONE_DIET
/// A LLVM<->CS Mapping entry of an operand.
typedef struct insn_op {
uint8_t /* cs_op_type */ type; ///< Operand type (e.g.: reg, imm, mem)
uint8_t /* cs_ac_type */ access; ///< The access type (read, write)
uint8_t /* cs_data_type */
dtypes[10]; ///< List of op types. Terminated by CS_DATA_TYPE_LAST
} insn_op;
///< Operands of an instruction.
typedef struct {
insn_op ops[16]; ///< NULL terminated array of operands.
} insn_ops;
static const insn_ops insn_operands[] = {
static const map_insn_ops insn_operands[] = {
#include "TriCoreGenCSMappingInsnOp.inc"
};
#endif

6
bindings/Makefile
View File

@ -6,7 +6,7 @@ TEST_BASIC = $(TMPDIR)/test_basic
TEST_DETAIL = $(TMPDIR)/test_detail
TEST_CUSTOMIZED_MNEM = $(TMPDIR)/test_customized_mnem
TEST_ARM = $(TMPDIR)/test_arm
TEST_ARM64 = $(TMPDIR)/test_arm64
TEST_ARM64 = $(TMPDIR)/test_aarch64
TEST_M68K = $(TMPDIR)/test_m68k
TEST_MIPS = $(TMPDIR)/test_mips
TEST_MOS65XX = $(TMPDIR)/test_mos65xx
@ -47,7 +47,7 @@ expected:
../tests/test_detail > $(TEST_DETAIL)_e
../tests/test_customized_mnem > $(TEST_CUSTOMIZED_MNEM)_e
../tests/test_arm > $(TEST_ARM)_e
../tests/test_arm64 > $(TEST_ARM64)_e
../tests/test_aarch64 > $(TEST_ARM64)_e
../tests/test_m68k > $(TEST_M68K)_e
../tests/test_mips > $(TEST_MIPS)_e
../tests/test_mos65xx > $(TEST_MOS65XX)_e
@ -71,7 +71,7 @@ python: FORCE
$(PYTHON3) python/test_detail.py > $(TEST_DETAIL)_o
$(PYTHON3) python/test_customized_mnem.py > $(TEST_CUSTOMIZED_MNEM)_o
$(PYTHON3) python/test_arm.py > $(TEST_ARM)_o
$(PYTHON3) python/test_arm64.py > $(TEST_ARM64)_o
$(PYTHON3) python/test_aarch64.py > $(TEST_ARM64)_o
$(PYTHON3) python/test_m68k.py > $(TEST_M68K)_o
$(PYTHON3) python/test_mips.py > $(TEST_MIPS)_o
$(PYTHON3) python/test_mos65xx.py > $(TEST_MOS65XX)_o

11
bindings/const_generator.py
View File

@ -5,7 +5,7 @@ import sys, re
INCL_DIR = '../include/capstone/'
include = [ 'arm.h', 'arm64.h', 'm68k.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h', 'tms320c64x.h', 'm680x.h', 'evm.h', 'mos65xx.h', 'wasm.h', 'bpf.h' ,'riscv.h', 'sh.h', 'tricore.h' ]
include = [ 'arm.h', 'm68k.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h', 'tms320c64x.h', 'm680x.h', 'evm.h', 'mos65xx.h', 'wasm.h', 'bpf.h' ,'riscv.h', 'sh.h', 'tricore.h' ]
template = {
'java': {
@ -15,7 +15,6 @@ template = {
'out_file': './java/capstone/%s_const.java',
# prefixes for constant filenames of all archs - case sensitive
'arm.h': 'Arm',
'arm64.h': 'Arm64',
'm68k.h': 'M68k',
'mips.h': 'Mips',
'x86.h': 'X86',
@ -38,7 +37,6 @@ template = {
'out_file': './python/capstone/%s_const.py',
# prefixes for constant filenames of all archs - case sensitive
'arm.h': 'arm',
'arm64.h': 'arm64',
'm68k.h': 'm68k',
'mips.h': 'mips',
'x86.h': 'x86',
@ -65,7 +63,6 @@ template = {
'out_file': './ocaml/%s_const.ml',
# prefixes for constant filenames of all archs - case sensitive
'arm.h': 'arm',
'arm64.h': 'arm64',
'mips.h': 'mips',
'm68k.h': 'm68k',
'x86.h': 'x86',
@ -157,6 +154,10 @@ template = {
# },
}
excluded_prefixes = {
'arm.h': ["ARMCC_CondCodes", "ARMVCC_VPTCodes"],
}
# markup for comments to be added to autogen files
MARKUP = '//>'
@ -246,6 +247,8 @@ def gen(lang):
line = ' '.join(xline)
def is_with_prefix(x):
if target in excluded_prefixes and any(x.startswith(excl_pre) for excl_pre in excluded_prefixes[target]):
return False
if prefixs:
return any(x.startswith(pre) for pre in prefixs)
else:

10
bindings/ocaml/Makefile
View File

@ -5,12 +5,12 @@ LIB = capstone
FLAGS = '-Wall -Wextra -Wwrite-strings'
PYTHON2 ?= python
all: arm_const.cmxa arm64_const.cmxa m680x_const.cmxa mips_const.cmxa ppc_const.cmxa sparc_const.cmxa sysz_const.cmxa x86_const.cmxa xcore_const.cmxa arm.cmxa arm64.cmxa m680x.cmxa mips.cmxa ppc.cmxa x86.cmxa sparc.cmxa systemz.cmxa xcore.cmxa capstone.cmxa test_basic.cmx test_detail.cmx test_x86.cmx test_arm.cmx test_arm64.cmx test_mips.cmx test_ppc.cmx test_sparc.cmx test_systemz.cmx test_xcore.cmx test_m680x.cmx ocaml.o
all: arm_const.cmxa arm64_const.cmxa m680x_const.cmxa mips_const.cmxa ppc_const.cmxa sparc_const.cmxa sysz_const.cmxa x86_const.cmxa xcore_const.cmxa arm.cmxa arm64.cmxa m680x.cmxa mips.cmxa ppc.cmxa x86.cmxa sparc.cmxa systemz.cmxa xcore.cmxa capstone.cmxa test_basic.cmx test_detail.cmx test_x86.cmx test_arm.cmx test_aarch64.cmx test_mips.cmx test_ppc.cmx test_sparc.cmx test_systemz.cmx test_xcore.cmx test_m680x.cmx ocaml.o
ocamlopt -o test_basic -ccopt $(FLAGS) ocaml.o capstone.cmx test_basic.cmx -cclib -l$(LIB)
ocamlopt -o test_detail -ccopt $(FLAGS) capstone.cmx ocaml.o test_detail.cmx -cclib -l$(LIB)
ocamlopt -o test_x86 -ccopt $(FLAGS) capstone.cmx ocaml.o x86.cmx x86_const.cmx test_x86.cmx -cclib -l$(LIB)
ocamlopt -o test_arm -ccopt $(FLAGS) capstone.cmx ocaml.o arm.cmx arm_const.cmx test_arm.cmx -cclib -l$(LIB)
ocamlopt -o test_arm64 -ccopt $(FLAGS) capstone.cmx ocaml.o arm64.cmx arm64_const.cmx test_arm64.cmx -cclib -l$(LIB)
ocamlopt -o test_aarch64 -ccopt $(FLAGS) capstone.cmx ocaml.o arm64.cmx arm64_const.cmx test_aarch64.cmx -cclib -l$(LIB)
ocamlopt -o test_mips -ccopt $(FLAGS) capstone.cmx ocaml.o mips.cmx mips_const.cmx test_mips.cmx -cclib -l$(LIB)
ocamlopt -o test_ppc -ccopt $(FLAGS) capstone.cmx ocaml.o ppc.cmx ppc_const.cmx test_ppc.cmx -cclib -l$(LIB)
ocamlopt -o test_sparc -ccopt $(FLAGS) capstone.cmx ocaml.o sparc.cmx sparc_const.cmx test_sparc.cmx -cclib -l$(LIB)
@ -31,7 +31,7 @@ test_x86.cmx: test_x86.ml
test_arm.cmx: test_arm.ml
ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB)
test_arm64.cmx: test_arm64.ml
test_aarch64.cmx: test_aarch64.ml
ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB)
test_mips.cmx: test_mips.ml
@ -284,12 +284,12 @@ xcore_const.cmxa: xcore_const.cmx
ocamlopt -ccopt $(FLAGS) -a -o $@ $<
clean:
rm -f *.[oa] *.so *.cm[ixoa] *.cmxa *.mli test_basic test_detail test_x86 test_arm test_arm64 test_mips test_ppc test_sparc test_systemz test_xcore test_m680x
rm -f *.[oa] *.so *.cm[ixoa] *.cmxa *.mli test_basic test_detail test_x86 test_arm test_aarch64 test_mips test_ppc test_sparc test_systemz test_xcore test_m680x
gen_const:
cd .. && $(PYTHON2) const_generator.py ocaml
TESTS = test_basic test_detail test_arm test_arm64 test_m680x test_mips test_ppc
TESTS = test_basic test_detail test_arm test_aarch64 test_m680x test_mips test_ppc
TESTS += test_sparc test_systemz test_x86 test_xcore
check:
@for t in $(TESTS); do \

2
bindings/python/Makefile
View File

@ -68,7 +68,7 @@ clean:
rm -f *.pyc capstone/*.pyc
TESTS = test_basic.py test_detail.py test_arm.py test_arm64.py test_m68k.py test_mips.py
TESTS = test_basic.py test_detail.py test_arm.py test_aarch64.py test_m68k.py test_mips.py
TESTS += test_ppc.py test_sparc.py test_systemz.py test_x86.py test_xcore.py test_tms320c64x.py
TESTS += test_m680x.py test_skipdata.py test_mos65xx.py test_bpf.py test_riscv.py
TESTS += test_evm.py test_tricore.py test_wasm.py test_sh.py

2
bindings/python/README.txt
View File

@ -29,7 +29,7 @@ disasm engine for binary analysis and reversing in the security community.
Created by Nguyen Anh Quynh, then developed and maintained by a small community,
Capstone offers some unparalleled features:
- Support multiple hardware architectures: ARM, ARM64 (ARMv8), Mips, PPC, Sparc,
- Support multiple hardware architectures: ARM, AARCH64 (ARMv8), Mips, PPC, Sparc,
SystemZ, XCore and X86 (including X86_64).
- Having clean/simple/lightweight/intuitive architecture-neutral API.

18
bindings/python/capstone/__init__.py
View File

@ -24,7 +24,7 @@ __all__ = [
'CS_VERSION_EXTRA',
'CS_ARCH_ARM',
'CS_ARCH_ARM64',
'CS_ARCH_AARCH64',
'CS_ARCH_MIPS',
'CS_ARCH_X86',
'CS_ARCH_PPC',
@ -200,7 +200,7 @@ __version__ = "%u.%u.%u" %(CS_VERSION_MAJOR, CS_VERSION_MINOR, CS_VERSION_EXTRA)
# architectures
CS_ARCH_ARM = 0
CS_ARCH_ARM64 = 1
CS_ARCH_AARCH64 = 1
CS_ARCH_MIPS = 2
CS_ARCH_X86 = 3
CS_ARCH_PPC = 4
@ -441,11 +441,11 @@ def copy_ctypes_list(src):
return [copy_ctypes(n) for n in src]
# Weird import placement because these modules are needed by the below code but need the above functions
from . import arm, arm64, m68k, mips, ppc, sparc, systemz, x86, xcore, tms320c64x, m680x, evm, mos65xx, wasm, bpf, riscv, sh, tricore
from . import arm, aarch64, m68k, mips, ppc, sparc, systemz, x86, xcore, tms320c64x, m680x, evm, mos65xx, wasm, bpf, riscv, sh, tricore
class _cs_arch(ctypes.Union):
_fields_ = (
('arm64', arm64.CsArm64),
('aarch64', aarch64.CsAArch64),
('arm', arm.CsArm),
('m68k', m68k.CsM68K),
('mips', mips.CsMips),
@ -758,8 +758,6 @@ class CsInsn(object):
raise CsError(CS_ERR_DIET)
if self._cs._detail:
if hasattr(self, 'arm64_writeback'):
return self.arm64_writeback
return self._raw.detail.contents.writeback
raise CsError(CS_ERR_DETAIL)
@ -773,9 +771,9 @@ class CsInsn(object):
if arch == CS_ARCH_ARM:
(self.usermode, self.vector_size, self.vector_data, self.cps_mode, self.cps_flag, self.cc, self.vcc, self.update_flags, \
self.post_index, self.mem_barrier, self.pred_mask, self.operands) = arm.get_arch_info(self._raw.detail.contents.arch.arm)
elif arch == CS_ARCH_ARM64:
(self.cc, self.update_flags, self.arm64_writeback, self.post_index, self.operands) = \
arm64.get_arch_info(self._raw.detail.contents.arch.arm64)
elif arch == CS_ARCH_AARCH64:
(self.cc, self.update_flags, self.post_index, self.operands) = \
aarch64.get_arch_info(self._raw.detail.contents.arch.aarch64)
elif arch == CS_ARCH_X86:
(self.prefix, self.opcode, self.rex, self.addr_size, \
self.modrm, self.sib, self.disp, \
@ -1301,7 +1299,7 @@ def debug():
diet = "standard"
archs = {
"arm": CS_ARCH_ARM, "arm64": CS_ARCH_ARM64, "m68k": CS_ARCH_M68K,
"arm": CS_ARCH_ARM, "aarch64": CS_ARCH_AARCH64, "m68k": CS_ARCH_M68K,
"mips": CS_ARCH_MIPS, "ppc": CS_ARCH_PPC, "sparc": CS_ARCH_SPARC,
"sysz": CS_ARCH_SYSZ, 'xcore': CS_ARCH_XCORE, "tms320c64x": CS_ARCH_TMS320C64X,
"m680x": CS_ARCH_M680X, 'evm': CS_ARCH_EVM, 'mos65xx': CS_ARCH_MOS65XX,

150
bindings/python/capstone/aarch64.py Normal file
View File

@ -0,0 +1,150 @@
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
import ctypes
from . import copy_ctypes_list
from .aarch64_const import *
# define the API
class AArch64OpMem(ctypes.Structure):
_fields_ = (
('base', ctypes.c_uint),
('index', ctypes.c_uint),
('disp', ctypes.c_int32),
)
class AArch64ImmRange(ctypes.Structure):
_fields_ = (
('imm', ctypes.c_int8),
('offset', ctypes.c_int8),
)
class AArch64SMESliceOffset(ctypes.Union):
_fields_ = (
('imm', ctypes.c_int8),
('imm_range', AArch64ImmRange)
)
class AArch64OpSme(ctypes.Structure):
_fileds_ = (
('type', ctypes.c_uint),
('tile', ctypes.c_uint),
('slice_reg', ctypes.c_uint),
('slice_offset', AArch64SMESliceOffset),
('has_range_offset', ctypes.c_bool),
('is_vertical', ctypes.c_bool),
)
class AArch64OpShift(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', ctypes.c_uint),
)
class AArch64SysOpSysReg(ctypes.Union):
_fields_ = (
('sysreg', ctypes.c_uint),
('tlbi', ctypes.c_uint),
('ic', ctypes.c_uint),
('raw_val', ctypes.c_uint64),
)
class AArch64SysOpSysImm(ctypes.Union):
_fields_ = (
('dbnxs', ctypes.c_uint),
('exactfpimm', ctypes.c_uint),
('raw_val', ctypes.c_uint64),
)
class AArch64SysOpSysAlias(ctypes.Union):
_fields_ = (
('svcr', ctypes.c_uint),
('at', ctypes.c_uint),
('db', ctypes.c_uint),
('dc', ctypes.c_uint),
('isb', ctypes.c_uint),
('tsb', ctypes.c_uint),
('prfm', ctypes.c_uint),
('sveprfm', ctypes.c_uint),
('rprfm', ctypes.c_uint),
('pstateimm0_15', ctypes.c_uint),
('pstateimm0_1', ctypes.c_uint),
('psb', ctypes.c_uint),
('bti', ctypes.c_uint),
('svepredpat', ctypes.c_uint),
('sveveclenspecifier', ctypes.c_uint),
('raw_val', ctypes.c_uint64),
)
class AArch64SysOp(ctypes.Structure):
_fields_ = (
('reg', AArch64SysOpSysReg),
('imm', AArch64SysOpSysImm),
('alias', AArch64SysOpSysAlias),
('sub_type', ctypes.c_uint),
)
class AArch64OpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_int64),
('imm_range', AArch64ImmRange),
('fp', ctypes.c_double),
('mem', AArch64OpMem),
('sysop', AArch64SysOp),
('sme', AArch64OpSme),
)
class AArch64Op(ctypes.Structure):
_fields_ = (
('vector_index', ctypes.c_int),
('vas', ctypes.c_uint),
('shift', AArch64OpShift),
('ext', ctypes.c_uint),
('type', ctypes.c_uint),
('value', AArch64OpValue),
('access', ctypes.c_uint8),
('is_list_member', ctypes.c_bool),
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
@property
def fp(self):
return self.value.fp
@property
def mem(self):
return self.value.mem
@property
def imm_range(self):
return self.value.imm_range
@property
def sysop(self):
return self.value.sysop
@property
def sme(self):
return self.value.sme
class CsAArch64(ctypes.Structure):
_fields_ = (
('cc', ctypes.c_uint),
('update_flags', ctypes.c_bool),
('post_index', ctypes.c_bool),
('is_doing_sme', ctypes.c_bool),
('op_count', ctypes.c_uint8),
('operands', AArch64Op * 8),
)
def get_arch_info(a):
return (a.cc, a.update_flags, a.post_index, copy_ctypes_list(a.operands[:a.op_count]))

2320
bindings/python/capstone/aarch64_const.py Normal file
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103
bindings/python/capstone/arm64.py
View File

@ -1,103 +0,0 @@
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
import ctypes
from . import copy_ctypes_list
from .arm64_const import *
# define the API
class Arm64OpMem(ctypes.Structure):
_fields_ = (
('base', ctypes.c_uint),
('index', ctypes.c_uint),
('disp', ctypes.c_int32),
)
class Arm64OpSmeIndex(ctypes.Structure):
_fileds_ = (
('reg', ctypes.c_uint),
('base', ctypes.c_uint),
('disp', ctypes.c_int32),
)
class Arm64OpShift(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', ctypes.c_uint),
)
class Arm64OpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_int64),
('fp', ctypes.c_double),
('mem', Arm64OpMem),
('pstate', ctypes.c_int),
('sys', ctypes.c_uint),
('prefetch', ctypes.c_int),
('barrier', ctypes.c_int),
('sme_index', Arm64OpSmeIndex),
)
class Arm64Op(ctypes.Structure):
_fields_ = (
('vector_index', ctypes.c_int),
('vas', ctypes.c_int),
('shift', Arm64OpShift),
('ext', ctypes.c_uint),
('type', ctypes.c_uint),
('svcr', ctypes.c_uint),
('value', Arm64OpValue),
('access', ctypes.c_uint8),
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
@property
def fp(self):
return self.value.fp
@property
def mem(self):
return self.value.mem
@property
def pstate(self):
return self.value.pstate
@property
def sys(self):
return self.value.sys
@property
def prefetch(self):
return self.value.prefetch
@property
def barrier(self):
return self.value.barrier
@property
def sme_index(self):
return self.value.sme_index
class CsArm64(ctypes.Structure):
_fields_ = (
('cc', ctypes.c_uint),
('update_flags', ctypes.c_bool),
('writeback', ctypes.c_bool),
('post_index', ctypes.c_bool),
('op_count', ctypes.c_uint8),
('operands', Arm64Op * 8),
)
def get_arch_info(a):
return (a.cc, a.update_flags, a.writeback, a.post_index, copy_ctypes_list(a.operands[:a.op_count]))

3008
bindings/python/capstone/arm64_const.py
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File diff suppressed because it is too large Load Diff

10
bindings/python/pyx/ccapstone.pyx
View File

@ -2,7 +2,7 @@
cimport pyx.ccapstone as cc
import capstone, ctypes
from . import arm, x86, mips, ppc, arm64, sparc, systemz, xcore, tms320c64x, m68k, m680x, evm, mos65xx, wasm, bpf, riscv, sh, tricore, CsError
from . import arm, x86, mips, ppc, aarch64, sparc, systemz, xcore, tms320c64x, m68k, m680x, evm, mos65xx, wasm, bpf, riscv, sh, tricore, CsError
_diet = cc.cs_support(capstone.CS_SUPPORT_DIET)
@ -26,9 +26,9 @@ class CsDetail(object):
(self.usermode, self.vector_size, self.vector_data, self.cps_mode, self.cps_flag, \
self.cc, self.vcc, self.update_flags, self.post_index, self.mem_barrier, self.pred_mask, self.operands) = \
arm.get_arch_info(detail.arch.arm)
elif arch == capstone.CS_ARCH_ARM64:
(self.cc, self.update_flags, self.arm64_writeback, self.post_index, self.operands) = \
arm64.get_arch_info(detail.arch.arm64)
elif arch == capstone.CS_ARCH_AARCH64:
(self.cc, self.update_flags, self.post_index, self.operands) = \
aarch64.get_arch_info(detail.arch.aarch64)
elif arch == capstone.CS_ARCH_X86:
(self.prefix, self.opcode, self.rex, self.addr_size, \
self.modrm, self.sib, self.disp, \
@ -359,7 +359,7 @@ def debug():
else:
diet = "standard"
archs = { "arm": capstone.CS_ARCH_ARM, "arm64": capstone.CS_ARCH_ARM64, \
archs = { "arm": capstone.CS_ARCH_ARM, "aarch64": capstone.CS_ARCH_AARCH64, \
"m68k": capstone.CS_ARCH_M68K, "mips": capstone.CS_ARCH_MIPS, \
"ppc": capstone.CS_ARCH_PPC, "sparc": capstone.CS_ARCH_SPARC, \
"sysz": capstone.CS_ARCH_SYSZ, "xcore": capstone.CS_ARCH_XCORE, \

2
bindings/python/setup_cython.py
View File

@ -69,7 +69,7 @@ else:
compile_args = ['-O3', '-fomit-frame-pointer', '-I' + HEADERS_DIR]
link_args = ['-L' + LIBS_DIR]
ext_module_names = ['arm', 'arm_const', 'arm64', 'arm64_const', 'm68k', 'm68k_const', 'm680x', 'm680x_const', 'mips', 'mips_const', 'ppc', 'ppc_const', 'x86', 'x86_const', 'sparc', 'sparc_const', 'systemz', 'sysz_const', 'xcore', 'xcore_const', 'tms320c64x', 'tms320c64x_const', 'evm', 'evm_const', 'mos65xx', 'mos65xx_const', 'wasm', 'wasm_const', 'bpf', 'bpf_const', 'riscv', 'riscv_const', 'sh', 'sh_const', 'tricore', 'tricore_const' ]
ext_module_names = ['arm', 'arm_const', 'aarch64', 'aarch64_const', 'm68k', 'm68k_const', 'm680x', 'm680x_const', 'mips', 'mips_const', 'ppc', 'ppc_const', 'x86', 'x86_const', 'sparc', 'sparc_const', 'systemz', 'sysz_const', 'xcore', 'xcore_const', 'tms320c64x', 'tms320c64x_const', 'evm', 'evm_const', 'mos65xx', 'mos65xx_const', 'wasm', 'wasm_const', 'bpf', 'bpf_const', 'riscv', 'riscv_const', 'sh', 'sh_const', 'tricore', 'tricore_const' ]
ext_modules = [Extension("capstone.ccapstone",
["pyx/ccapstone.pyx"],

185
bindings/python/test_aarch64.py Executable file
View File

@ -0,0 +1,185 @@
#!/usr/bin/env python
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
from __future__ import print_function
from capstone import *
from capstone.aarch64 import *
from xprint import to_hex, to_x, to_x_32
AArch64_CODE = b"\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c\xfd\x7b\xba\xa9\xfd\xc7\x43\xf8"
all_tests = (
(CS_ARCH_AARCH64, CS_MODE_ARM, AArch64_CODE, "AARCH64"),
)
def print_insn_detail(insn):
# print address, mnemonic and operands
print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
# "data" instruction generated by SKIPDATA option has no detail
if insn.id == 0:
return
if len(insn.operands) > 0:
print("\top_count: %u" % len(insn.operands))
c = -1
for i in insn.operands:
c += 1
if i.type == AArch64_OP_REG:
print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
if i.type == AArch64_OP_IMM:
print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
if i.type == AArch64_OP_CIMM:
print("\t\toperands[%u].type: C-IMM = %u" % (c, i.imm))
if i.type == AArch64_OP_FP:
print("\t\toperands[%u].type: FP = %f" % (c, i.fp))
if i.type == AArch64_OP_MEM:
print("\t\toperands[%u].type: MEM" % c)
if i.mem.base != 0:
print("\t\t\toperands[%u].mem.base: REG = %s" \
% (c, insn.reg_name(i.mem.base)))
if i.mem.index != 0:
print("\t\t\toperands[%u].mem.index: REG = %s" \
% (c, insn.reg_name(i.mem.index)))
if i.mem.disp != 0:
print("\t\t\toperands[%u].mem.disp: 0x%s" \
% (c, to_x_32(i.mem.disp)))
if insn.post_index:
print("\t\t\tpost-indexed: true");
if i.type == AArch64_OP_SME_MATRIX:
print("\t\toperands[%u].type: SME_MATRIX" % (c))
print("\t\toperands[%u].sme.type: %d" % (c, i.sme.type))
if i.sme.tile != AArch64_REG_INVALID:
print("\t\toperands[%u].sme.tile: %s" % (c, insn.reg_name(i.sme.tile)))
if i.sme.slice_reg != AArch64_REG_INVALID:
print("\t\toperands[%u].sme.slice_reg: %s" % (c, insn.reg_name(i.sme.slice_reg)))
if i.sme.slice_offset.imm != -1 or i.sme.slice_offset.imm_range.first != -1:
print("\t\toperands[%u].sme.slice_offset: " % (c))
if i.sme.has_range_offset:
print("%hhd:%hhd" % (i.sme.slice_offset.imm_range.first, i.sme.slice_offset.imm_range.offset))
else:
print("%d" % (i.sme.slice_offset.imm))
if i.sme.slice_reg != AArch64_REG_INVALID or i.sme.slice_offset.imm != -1:
print("\t\toperands[%u].sme.is_vertical: %s" % (c, ("true" if i.sme.is_vertical else "false")))
if i.type == AArch64_OP_SYSREG:
print("\t\toperands[%u].type: SYS REG:" % (c))
if i.sysop.sub_type == AArch64_OP_REG_MRS:
print("\t\toperands[%u].subtype: REG_MRS = 0x%x" % (c, i.sysop.reg.sysreg))
if i.sysop.sub_type == AArch64_OP_REG_MSR:
print("\t\toperands[%u].subtype: REG_MSR = 0x%x" % (c, i.sysop.reg.sysreg))
if i.sysop.sub_type == AArch64_OP_TLBI:
print("\t\toperands[%u].subtype TLBI = 0x%x" % (c, i.sysop.reg.tlbi))
if i.sysop.sub_type == AArch64_OP_IC:
print("\t\toperands[%u].subtype IC = 0x%x" % (c, i.sysop.reg.ic))
if i.type == AArch64_OP_SYSALIAS:
print("\t\toperands[%u].type: SYS ALIAS:" % (c))
if i.sysop.sub_type == AArch64_OP_SVCR:
if i.sysop.alias.svcr == AArch64_SVCR_SVCRSM:
print("\t\t\toperands[%u].svcr: BIT = SM" % (c))
elif i.sysop.alias.svcr == AArch64_SVCR_SVCRZA:
print("\t\t\toperands[%u].svcr: BIT = ZA" % (c))
elif i.sysop.alias.svcr == AArch64_SVCR_SVCRSMZA:
print("\t\t\toperands[%u].svcr: BIT = SM & ZA" % (c))
if i.sysop.sub_type == AArch64_OP_AT:
print("\t\toperands[%u].subtype AT = 0x%x" % (c, i.sysop.alias.at))
if i.sysop.sub_type == AArch64_OP_DB:
print("\t\toperands[%u].subtype DB = 0x%x" % (c, i.sysop.alias.db))
if i.sysop.sub_type == AArch64_OP_DC:
print("\t\toperands[%u].subtype DC = 0x%x" % (c, i.sysop.alias.dc))
if i.sysop.sub_type == AArch64_OP_ISB:
print("\t\toperands[%u].subtype ISB = 0x%x" % (c, i.sysop.alias.isb))
if i.sysop.sub_type == AArch64_OP_TSB:
print("\t\toperands[%u].subtype TSB = 0x%x" % (c, i.sysop.alias.tsb))
if i.sysop.sub_type == AArch64_OP_PRFM:
print("\t\toperands[%u].subtype PRFM = 0x%x" % (c, i.sysop.alias.prfm))
if i.sysop.sub_type == AArch64_OP_SVEPRFM:
print("\t\toperands[%u].subtype SVEPRFM = 0x%x" % (c, i.sysop.alias.sveprfm))
if i.sysop.sub_type == AArch64_OP_RPRFM:
print("\t\toperands[%u].subtype RPRFM = 0x%x" % (c, i.sysop.alias.rprfm))
if i.sysop.sub_type == AArch64_OP_PSTATEIMM0_15:
print("\t\toperands[%u].subtype PSTATEIMM0_15 = 0x%x" % (c, i.sysop.alias.pstateimm0_15))
if i.sysop.sub_type == AArch64_OP_PSTATEIMM0_1:
print("\t\toperands[%u].subtype PSTATEIMM0_1 = 0x%x" % (c, i.sysop.alias.pstateimm0_1))
if i.sysop.sub_type == AArch64_OP_PSB:
print("\t\toperands[%u].subtype PSB = 0x%x" % (c, i.sysop.alias.psb))
if i.sysop.sub_type == AArch64_OP_BTI:
print("\t\toperands[%u].subtype BTI = 0x%x" % (c, i.sysop.alias.bti))
if i.sysop.sub_type == AArch64_OP_SVEPREDPAT:
print("\t\toperands[%u].subtype SVEPREDPAT = 0x%x" % (c, i.sysop.alias.svepredpat))
if i.sysop.sub_type == AArch64_OP_SVEVECLENSPECIFIER:
print("\t\toperands[%u].subtype SVEVECLENSPECIFIER = 0x%x" % (c, i.sysop.alias.sveveclenspecifier))
if i.type == AArch64_OP_SYSIMM:
print("\t\toperands[%u].type: SYS IMM:" % (c))
if i.sysop.sub_type == AArch64_OP_EXACTFPIMM:
print("\t\toperands[%u].subtype EXACTFPIMM = %d" % (c, i.sysop.imm.exactfpimm))
if i.sysop.sub_type == AArch64_OP_DBNXS:
print("\t\toperands[%u].subtype DBNXS = %d" % (c, i.sysop.imm.dbnxs))
if i.access == CS_AC_READ:
print("\t\toperands[%u].access: READ" % (c))
elif i.access == CS_AC_WRITE:
print("\t\toperands[%u].access: WRITE" % (c))
elif i.access == CS_AC_READ | CS_AC_WRITE:
print("\t\toperands[%u].access: READ | WRITE" % (c))
if i.shift.type != AArch64_SFT_INVALID and i.shift.value:
print("\t\t\tShift: type = %u, value = %u" % (i.shift.type, i.shift.value))
if i.ext != AArch64_EXT_INVALID:
print("\t\t\tExt: %u" % i.ext)
if i.vas != AArch64Layout_Invalid:
print("\t\t\tVector Arrangement Specifier: 0x%x" % i.vas)
if i.vector_index != -1:
print("\t\t\tVector Index: %u" % i.vector_index)
if insn.writeback:
print("\tWrite-back: True")
if not insn.cc in [AArch64CC_AL, AArch64CC_Invalid]:
print("\tCode-condition: %u" % insn.cc)
if insn.update_flags:
print("\tUpdate-flags: True")
(regs_read, regs_write) = insn.regs_access()
if len(regs_read) > 0:
print("\tRegisters read:", end="")
for r in regs_read:
print(" %s" %(insn.reg_name(r)), end="")
print("")
if len(regs_write) > 0:
print("\tRegisters modified:", end="")
for r in regs_write:
print(" %s" %(insn.reg_name(r)), end="")
print("")
# ## Test class Cs
def test_class():
for (arch, mode, code, comment) in all_tests:
print("*" * 16)
print("Platform: %s" % comment)
print("Code: %s" % to_hex(code))
print("Disasm:")
try:
md = Cs(arch, mode)
md.detail = True
for insn in md.disasm(code, 0x2c):
print_insn_detail(insn)
print ()
print("0x%x:\n" % (insn.address + insn.size))
except CsError as e:
print("ERROR: %s" % e)
if __name__ == '__main__':
test_class()

4
bindings/python/test_all.py
View File

@ -1,12 +1,12 @@
#!/usr/bin/env python
import test_basic, test_arm, test_arm64, test_detail, test_lite, test_m68k, test_mips, \
import test_basic, test_arm, test_aarch64, test_detail, test_lite, test_m68k, test_mips, \
test_ppc, test_x86, test_skipdata, test_sparc, test_systemz, test_tms320c64x, test_customized_mnem, \
test_m680x, test_mos65xx, test_xcore, test_riscv
test_basic.test_class()
test_arm.test_class()
test_arm64.test_class()
test_aarch64.test_class()
test_detail.test_class()
test_lite.test_class()
test_m68k.test_class()

144
bindings/python/test_arm64.py
View File

@ -1,144 +0,0 @@
#!/usr/bin/env python
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
from __future__ import print_function
from capstone import *
from capstone.arm64 import *
from xprint import to_hex, to_x, to_x_32
ARM64_CODE = b"\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c\xfd\x7b\xba\xa9\xfd\xc7\x43\xf8"
all_tests = (
(CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64"),
)
def print_insn_detail(insn):
# print address, mnemonic and operands
print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
# "data" instruction generated by SKIPDATA option has no detail
if insn.id == 0:
return
if len(insn.operands) > 0:
print("\top_count: %u" % len(insn.operands))
c = -1
for i in insn.operands:
c += 1
if i.type == ARM64_OP_REG:
print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
if i.type == ARM64_OP_IMM:
print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
if i.type == ARM64_OP_CIMM:
print("\t\toperands[%u].type: C-IMM = %u" % (c, i.imm))
if i.type == ARM64_OP_FP:
print("\t\toperands[%u].type: FP = %f" % (c, i.fp))
if i.type == ARM64_OP_MEM:
print("\t\toperands[%u].type: MEM" % c)
if i.mem.base != 0:
print("\t\t\toperands[%u].mem.base: REG = %s" \
% (c, insn.reg_name(i.mem.base)))
if i.mem.index != 0:
print("\t\t\toperands[%u].mem.index: REG = %s" \
% (c, insn.reg_name(i.mem.index)))
if i.mem.disp != 0:
print("\t\t\toperands[%u].mem.disp: 0x%s" \
% (c, to_x_32(i.mem.disp)))
if i.type == ARM64_OP_REG_MRS:
print("\t\toperands[%u].type: REG_MRS = 0x%x" % (c, i.reg))
if i.type == ARM64_OP_REG_MSR:
print("\t\toperands[%u].type: REG_MSR = 0x%x" % (c, i.reg))
if i.type == ARM64_OP_PSTATE:
print("\t\toperands[%u].type: PSTATE = 0x%x" % (c, i.pstate))
if i.type == ARM64_OP_SYS:
print("\t\toperands[%u].type: SYS = 0x%x" % (c, i.sys))
if i.type == ARM64_OP_PREFETCH:
print("\t\toperands[%u].type: PREFETCH = 0x%x" % (c, i.prefetch))
if i.type == ARM64_OP_BARRIER:
print("\t\toperands[%u].type: BARRIER = 0x%x" % (c, i.barrier))
if i.type == ARM64_OP_SVCR:
print("\t\toperands[%u].type: SYS = 0x%x" % (c, i.sys))
if i.svcr == ARM64_SVCR_SVCRSM:
print("\t\t\toperands[%u].svcr: BIT = SM" % (c))
if i.svcr == ARM64_SVCR_SVCRZA:
print("\t\t\toperands[%u].svcr: BIT = ZA" % (c))
if i.svcr == ARM64_SVCR_SVCRSMZA:
print("\t\t\toperands[%u].svcr: BIT = SM & ZA" % (c))
if i.type == ARM64_OP_SME_INDEX:
print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
if i.sme_index.base != ARM64_REG_INVALID:
print("\t\t\toperands[%u].index.base: REG = %s" % (c, insn.reg_name(i.reg)))
if i.sme_index.disp != 0 :
print("\t\t\toperands[%u].index.disp: 0x%x" %(c, i.sme_index.disp))
if i.access == CS_AC_READ:
print("\t\toperands[%u].access: READ" % (c))
elif i.access == CS_AC_WRITE:
print("\t\toperands[%u].access: WRITE" % (c))
elif i.access == CS_AC_READ | CS_AC_WRITE:
print("\t\toperands[%u].access: READ | WRITE" % (c))
if i.shift.type != ARM64_SFT_INVALID and i.shift.value:
print("\t\t\tShift: type = %u, value = %u" % (i.shift.type, i.shift.value))
if i.ext != ARM64_EXT_INVALID:
print("\t\t\tExt: %u" % i.ext)
if i.vas != ARM64_VAS_INVALID:
print("\t\t\tVector Arrangement Specifier: 0x%x" % i.vas)
if i.vector_index != -1:
print("\t\t\tVector Index: %u" % i.vector_index)
if insn.writeback:
if insn.post_index:
print("\tWrite-back: Post")
else:
print("\tWrite-back: Pre")
if not insn.cc in [ARM64_CC_AL, ARM64_CC_INVALID]:
print("\tCode-condition: %u" % insn.cc)
if insn.update_flags:
print("\tUpdate-flags: True")
(regs_read, regs_write) = insn.regs_access()
if len(regs_read) > 0:
print("\tRegisters read:", end="")
for r in regs_read:
print(" %s" %(insn.reg_name(r)), end="")
print("")
if len(regs_write) > 0:
print("\tRegisters modified:", end="")
for r in regs_write:
print(" %s" %(insn.reg_name(r)), end="")
print("")
# ## Test class Cs
def test_class():
for (arch, mode, code, comment) in all_tests:
print("*" * 16)
print("Platform: %s" % comment)
print("Code: %s" % to_hex(code))
print("Disasm:")
try:
md = Cs(arch, mode)
md.detail = True
for insn in md.disasm(code, 0x2c):
print_insn_detail(insn)
print ()
print("0x%x:\n" % (insn.address + insn.size))
except CsError as e:
print("ERROR: %s" % e)
if __name__ == '__main__':
test_class()

4
bindings/python/test_basic.py
View File

@ -24,7 +24,7 @@ MIPS_CODE = b"\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x
MIPS_CODE2 = b"\x56\x34\x21\x34\xc2\x17\x01\x00"
MIPS_32R6M = b"\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
MIPS_32R6 = b"\xec\x80\x00\x19\x7c\x43\x22\xa0"
ARM64_CODE = b"\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9"
AARCH64_CODE = b"\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9"
PPC_CODE = b"\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21"
PPC_CODE2 = b"\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f"
SPARC_CODE = b"\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
@ -58,7 +58,7 @@ all_tests = (
(CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", None),
(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)", None),
(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)", None),
(CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64", None),
(CS_ARCH_AARCH64, CS_MODE_ARM, AARCH64_CODE, "AARCH64", None),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64", None),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64, print register with number only", CS_OPT_SYNTAX_NOREGNAME),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN + CS_MODE_QPX, PPC_CODE2, "PPC-64 + QPX", None),

4
bindings/python/test_detail.py
View File

@ -19,7 +19,7 @@ MIPS_CODE = b"\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x
MIPS_CODE2 = b"\x56\x34\x21\x34\xc2\x17\x01\x00"
MIPS_32R6M = b"\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
MIPS_32R6 = b"\xec\x80\x00\x19\x7c\x43\x22\xa0"
ARM64_CODE = b"\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c"
AARCH64_CODE = b"\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c"
PPC_CODE = b"\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14"
PPC_CODE2 = b"\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f"
SPARC_CODE = b"\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
@ -42,7 +42,7 @@ all_tests = (
(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2", None),
(CS_ARCH_ARM, CS_MODE_THUMB + CS_MODE_MCLASS, THUMB_MCLASS, "Thumb-MClass", None),
(CS_ARCH_ARM, CS_MODE_ARM + CS_MODE_V8, ARMV8, "Arm-V8", None),
(CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64", None),
(CS_ARCH_AARCH64, CS_MODE_ARM, AARCH64_CODE, "AARCH64", None),
(CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", None),
(CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", None),
(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)", None),

4
bindings/python/test_iter.py
View File

@ -19,7 +19,7 @@ MIPS_CODE = b"\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x
MIPS_CODE2 = b"\x56\x34\x21\x34\xc2\x17\x01\x00"
MIPS_32R6M = b"\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
MIPS_32R6 = b"\xec\x80\x00\x19\x7c\x43\x22\xa0"
ARM64_CODE = b"\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9"
AARCH64_CODE = b"\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9"
PPC_CODE = b"\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21"
PPC_CODE2 = b"\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f"
SPARC_CODE = b"\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
@ -45,7 +45,7 @@ all_tests = (
(CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", None),
(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)", None),
(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)", None),
(CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64", None),
(CS_ARCH_AARCH64, CS_MODE_ARM, AARCH64_CODE, "AARCH64", None),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64", None),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64, print register with number only", CS_OPT_SYNTAX_NOREGNAME),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN + CS_MODE_QPX, PPC_CODE2, "PPC-64 + QPX", CS_OPT_SYNTAX_NOREGNAME),

4
bindings/python/test_lite.py
View File

@ -19,7 +19,7 @@ MIPS_CODE = b"\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x
MIPS_CODE2 = b"\x56\x34\x21\x34\xc2\x17\x01\x00"
MIPS_32R6M = b"\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
MIPS_32R6 = b"\xec\x80\x00\x19\x7c\x43\x22\xa0"
ARM64_CODE = b"\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9"
AARCH64_CODE = b"\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9"
PPC_CODE = b"\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21"
PPC_CODE2 = b"\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f"
SPARC_CODE = b"\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
@ -45,7 +45,7 @@ all_tests = (
(CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", None),
(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)", None),
(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)", None),
(CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64", None),
(CS_ARCH_AARCH64, CS_MODE_ARM, AARCH64_CODE, "AARCH64", None),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64", None),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64, print register with number only", CS_OPT_SYNTAX_NOREGNAME),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN + CS_MODE_QPX, PPC_CODE2, "PPC-64 + QPX", CS_OPT_SYNTAX_NOREGNAME),

5
cmake.sh
View File

@ -13,7 +13,10 @@ case $1 in
ARCH=ARM
;;
ARM64)
ARCH=ARM64
ARCH=AARCH64
;;
AARCH64)
ARCH=AARCH64
;;
M68K)
ARCH=M68K

25
cs.c
View File

@ -25,7 +25,7 @@
// Issue #681: Windows kernel does not support formatting float point
#if defined(_KERNEL_MODE) && !defined(CAPSTONE_DIET)
#if defined(CAPSTONE_HAS_ARM) || defined(CAPSTONE_HAS_ARM64) || defined(CAPSTONE_HAS_M68K)
#if defined(CAPSTONE_HAS_ARM) || defined(CAPSTONE_HAS_AARCH64) || defined(CAPSTONE_HAS_M68K)
#define CAPSTONE_STR_INTERNAL(x) #x
#define CAPSTONE_STR(x) CAPSTONE_STR_INTERNAL(x)
#define CAPSTONE_MSVC_WRANING_PREFIX __FILE__ "("CAPSTONE_STR(__LINE__)") : warning message : "
@ -90,7 +90,7 @@ static const struct {
#else
{ NULL, NULL, 0 },
#endif
#ifdef CAPSTONE_HAS_ARM64
#ifdef CAPSTONE_HAS_AARCH64
{
AArch64_global_init,
AArch64_option,
@ -262,8 +262,8 @@ static const uint32_t all_arch = 0
#ifdef CAPSTONE_HAS_ARM
| (1 << CS_ARCH_ARM)
#endif
#ifdef CAPSTONE_HAS_ARM64
| (1 << CS_ARCH_ARM64)
#if defined(CAPSTONE_HAS_AARCH64) || defined(CAPSTONE_HAS_ARM64)
| (1 << CS_ARCH_AARCH64)
#endif
#ifdef CAPSTONE_HAS_MIPS
| (1 << CS_ARCH_MIPS)
@ -378,7 +378,8 @@ CAPSTONE_EXPORT
bool CAPSTONE_API cs_support(int query)
{
if (query == CS_ARCH_ALL)
return all_arch == ((1 << CS_ARCH_ARM) | (1 << CS_ARCH_ARM64) |
return all_arch ==
((1 << CS_ARCH_ARM) | (1 << CS_ARCH_AARCH64) |
(1 << CS_ARCH_MIPS) | (1 << CS_ARCH_X86) |
(1 << CS_ARCH_PPC) | (1 << CS_ARCH_SPARC) |
(1 << CS_ARCH_SYSZ) | (1 << CS_ARCH_XCORE) |
@ -668,7 +669,7 @@ static uint8_t skipdata_size(cs_struct *handle)
return 2;
// otherwise, skip 4 bytes
return 4;
case CS_ARCH_ARM64:
case CS_ARCH_AARCH64:
case CS_ARCH_MIPS:
case CS_ARCH_PPC:
case CS_ARCH_SPARC:
@ -1376,9 +1377,9 @@ int CAPSTONE_API cs_op_count(csh ud, const cs_insn *insn, unsigned int op_type)
if (insn->detail->arm.operands[i].type == (arm_op_type)op_type)
count++;
break;
case CS_ARCH_ARM64:
for (i = 0; i < insn->detail->arm64.op_count; i++)
if (insn->detail->arm64.operands[i].type == (arm64_op_type)op_type)
case CS_ARCH_AARCH64:
for (i = 0; i < insn->detail->aarch64.op_count; i++)
if (insn->detail->aarch64.operands[i].type == (aarch64_op_type)op_type)
count++;
break;
case CS_ARCH_X86:
@ -1498,9 +1499,9 @@ int CAPSTONE_API cs_op_index(csh ud, const cs_insn *insn, unsigned int op_type,
return i;
}
break;
case CS_ARCH_ARM64:
for (i = 0; i < insn->detail->arm64.op_count; i++) {
if (insn->detail->arm64.operands[i].type == (arm64_op_type)op_type)
case CS_ARCH_AARCH64:
for (i = 0; i < insn->detail->aarch64.op_count; i++) {
if (insn->detail->aarch64.operands[i].type == (aarch64_op_type)op_type)
count++;
if (count == post)
return i;

18
cstool/cstool.c
View File

@ -30,8 +30,8 @@ static struct {
{ "thumb", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB },
{ "thumbbe", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_BIG_ENDIAN },
{ "thumble", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_LITTLE_ENDIAN },
{ "arm64", CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN },
{ "arm64be", CS_ARCH_ARM64, CS_MODE_BIG_ENDIAN },
{ "aarch64", CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN },
{ "aarch64be", CS_ARCH_AARCH64, CS_MODE_BIG_ENDIAN },
{ "mips", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_LITTLE_ENDIAN },
{ "mipsmicro", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_MICRO },
{ "mipsbemicro", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_MICRO | CS_MODE_BIG_ENDIAN },
@ -203,9 +203,9 @@ static void usage(char *prog)
printf(" thumbv8be thumb v8 + big endian\n");
}
if (cs_support(CS_ARCH_ARM64)) {
printf(" arm64 aarch64 mode\n");
printf(" arm64be aarch64 + big endian\n");
if (cs_support(CS_ARCH_AARCH64)) {
printf(" aarch64 aarch64 mode\n");
printf(" aarch64be aarch64 + big endian\n");
}
if (cs_support(CS_ARCH_MIPS)) {
@ -344,8 +344,8 @@ static void print_details(csh handle, cs_arch arch, cs_mode md, cs_insn *ins)
case CS_ARCH_ARM:
print_insn_detail_arm(handle, ins);
break;
case CS_ARCH_ARM64:
print_insn_detail_arm64(handle, ins);
case CS_ARCH_AARCH64:
print_insn_detail_aarch64(handle, ins);
break;
case CS_ARCH_MIPS:
print_insn_detail_mips(handle, ins);
@ -456,8 +456,8 @@ int main(int argc, char **argv)
printf("arm=1 ");
}
if (cs_support(CS_ARCH_ARM64)) {
printf("arm64=1 ");
if (cs_support(CS_ARCH_AARCH64)) {
printf("aarch64=1 ");
}
if (cs_support(CS_ARCH_MIPS)) {

2
cstool/cstool.h
View File

@ -3,7 +3,7 @@
void print_insn_detail_x86(csh ud, cs_mode mode, cs_insn *ins);
void print_insn_detail_arm(csh handle, cs_insn *ins);
void print_insn_detail_arm64(csh handle, cs_insn *ins);
void print_insn_detail_aarch64(csh handle, cs_insn *ins);
void print_insn_detail_mips(csh handle, cs_insn *ins);
void print_insn_detail_ppc(csh handle, cs_insn *ins);
void print_insn_detail_sparc(csh handle, cs_insn *ins);

232
cstool/cstool_aarch64.c Normal file
View File

@ -0,0 +1,232 @@
/* Capstone Disassembler Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
#include "capstone/aarch64.h"
#include <stdio.h>
#include <stdlib.h>
#include <capstone/capstone.h>
#include "cstool.h"
void print_insn_detail_aarch64(csh handle, cs_insn *ins)
{
cs_aarch64 *aarch64;
int i;
cs_regs regs_read, regs_write;
uint8_t regs_read_count, regs_write_count;
uint8_t access;
// detail can be NULL if SKIPDATA option is turned ON
if (ins->detail == NULL)
return;
aarch64 = &(ins->detail->aarch64);
if (aarch64->op_count)
printf("\top_count: %u\n", aarch64->op_count);
for (i = 0; i < aarch64->op_count; i++) {
cs_aarch64_op *op = &(aarch64->operands[i]);
switch(op->type) {
default:
break;
case AArch64_OP_REG:
printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
break;
case AArch64_OP_IMM:
printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm);
break;
case AArch64_OP_FP:
#if defined(_KERNEL_MODE)
// Issue #681: Windows kernel does not support formatting float point
printf("\t\toperands[%u].type: FP = <float_point_unsupported>\n", i);
#else
printf("\t\toperands[%u].type: FP = %f\n", i, op->fp);
#endif
break;
case AArch64_OP_MEM:
printf("\t\toperands[%u].type: MEM\n", i);
if (op->mem.base != AArch64_REG_INVALID)
printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base));
if (op->mem.index != AArch64_REG_INVALID)
printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, cs_reg_name(handle, op->mem.index));
if (op->mem.disp != 0)
printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp);
if (ins->detail->aarch64.post_index)
printf("\t\t\tpost-indexed: true\n");
break;
case AArch64_OP_SME_MATRIX:
printf("\t\toperands[%u].type: SME_MATRIX\n", i);
printf("\t\toperands[%u].sme.type: %d\n", i, op->sme.type);
if (op->sme.tile != AArch64_REG_INVALID)
printf("\t\toperands[%u].sme.tile: %s\n", i, cs_reg_name(handle, op->sme.tile));
if (op->sme.slice_reg != AArch64_REG_INVALID)
printf("\t\toperands[%u].sme.slice_reg: %s\n", i, cs_reg_name(handle, op->sme.slice_reg));
if (op->sme.slice_offset.imm != -1 || op->sme.slice_offset.imm_range.first != -1) {
printf("\t\toperands[%u].sme.slice_offset: ", i);
if (op->sme.has_range_offset)
printf("%hhd:%hhd\n", op->sme.slice_offset.imm_range.first, op->sme.slice_offset.imm_range.offset);
else
printf("%d\n", op->sme.slice_offset.imm);
}
if (op->sme.slice_reg != AArch64_REG_INVALID || op->sme.slice_offset.imm != -1)
printf("\t\toperands[%u].sme.is_vertical: %s\n", i, (op->sme.is_vertical ? "true" : "false"));
break;
case AArch64_OP_CIMM:
printf("\t\toperands[%u].type: C-IMM = %u\n", i, (int)op->imm);
break;
case AArch64_OP_SYSREG:
printf("\t\toperands[%u].type: SYS REG:\n", i);
switch (op->sysop.sub_type) {
default:
printf("Sub type %d not handled.\n", op->sysop.sub_type);
break;
case AArch64_OP_REG_MRS:
printf("\t\toperands[%u].subtype: REG_MRS = 0x%x\n", i, op->sysop.reg.sysreg);
break;
case AArch64_OP_REG_MSR:
printf("\t\toperands[%u].subtype: REG_MSR = 0x%x\n", i, op->sysop.reg.sysreg);
break;
case AArch64_OP_TLBI:
printf("\t\toperands[%u].subtype TLBI = 0x%x\n", i, op->sysop.reg.tlbi);
break;
case AArch64_OP_IC:
printf("\t\toperands[%u].subtype IC = 0x%x\n", i, op->sysop.reg.ic);
break;
}
break;
case AArch64_OP_SYSALIAS:
printf("\t\toperands[%u].type: SYS ALIAS:\n", i);
switch (op->sysop.sub_type) {
default:
printf("Sub type %d not handled.\n", op->sysop.sub_type);
break;
case AArch64_OP_SVCR:
if(op->sysop.alias.svcr == AArch64_SVCR_SVCRSM)
printf("\t\t\toperands[%u].svcr: BIT = SM\n", i);
else if(op->sysop.alias.svcr == AArch64_SVCR_SVCRZA)
printf("\t\t\toperands[%u].svcr: BIT = ZA\n", i);
else if(op->sysop.alias.svcr == AArch64_SVCR_SVCRSMZA)
printf("\t\t\toperands[%u].svcr: BIT = SM & ZA\n", i);
break;
case AArch64_OP_AT:
printf("\t\toperands[%u].subtype AT = 0x%x\n", i, op->sysop.alias.at);
break;
case AArch64_OP_DB:
printf("\t\toperands[%u].subtype DB = 0x%x\n", i, op->sysop.alias.db);
break;
case AArch64_OP_DC:
printf("\t\toperands[%u].subtype DC = 0x%x\n", i, op->sysop.alias.dc);
break;
case AArch64_OP_ISB:
printf("\t\toperands[%u].subtype ISB = 0x%x\n", i, op->sysop.alias.isb);
break;
case AArch64_OP_TSB:
printf("\t\toperands[%u].subtype TSB = 0x%x\n", i, op->sysop.alias.tsb);
break;
case AArch64_OP_PRFM:
printf("\t\toperands[%u].subtype PRFM = 0x%x\n", i, op->sysop.alias.prfm);
break;
case AArch64_OP_SVEPRFM:
printf("\t\toperands[%u].subtype SVEPRFM = 0x%x\n", i, op->sysop.alias.sveprfm);
break;
case AArch64_OP_RPRFM:
printf("\t\toperands[%u].subtype RPRFM = 0x%x\n", i, op->sysop.alias.rprfm);
break;
case AArch64_OP_PSTATEIMM0_15:
printf("\t\toperands[%u].subtype PSTATEIMM0_15 = 0x%x\n", i, op->sysop.alias.pstateimm0_15);
break;
case AArch64_OP_PSTATEIMM0_1:
printf("\t\toperands[%u].subtype PSTATEIMM0_1 = 0x%x\n", i, op->sysop.alias.pstateimm0_1);
break;
case AArch64_OP_PSB:
printf("\t\toperands[%u].subtype PSB = 0x%x\n", i, op->sysop.alias.psb);
break;
case AArch64_OP_BTI:
printf("\t\toperands[%u].subtype BTI = 0x%x\n", i, op->sysop.alias.bti);
break;
case AArch64_OP_SVEPREDPAT:
printf("\t\toperands[%u].subtype SVEPREDPAT = 0x%x\n", i, op->sysop.alias.svepredpat);
break;
case AArch64_OP_SVEVECLENSPECIFIER:
printf("\t\toperands[%u].subtype SVEVECLENSPECIFIER = 0x%x\n", i, op->sysop.alias.sveveclenspecifier);
break;
}
break;
case AArch64_OP_SYSIMM:
printf("\t\toperands[%u].type: SYS IMM:\n", i);
switch(op->sysop.sub_type) {
default:
printf("Sub type %d not handled.\n", op->sysop.sub_type);
break;
case AArch64_OP_EXACTFPIMM:
printf("\t\toperands[%u].subtype EXACTFPIMM = %d\n", i, op->sysop.imm.exactfpimm);
break;
case AArch64_OP_DBNXS:
printf("\t\toperands[%u].subtype DBNXS = %d\n", i, op->sysop.imm.dbnxs);
break;
}
break;
}
access = op->access;
switch(access) {
default:
break;
case CS_AC_READ:
printf("\t\toperands[%u].access: READ\n", i);
break;
case CS_AC_WRITE:
printf("\t\toperands[%u].access: WRITE\n", i);
break;
case CS_AC_READ | CS_AC_WRITE:
printf("\t\toperands[%u].access: READ | WRITE\n", i);
break;
}
if (op->shift.type != AArch64_SFT_INVALID &&
op->shift.value)
printf("\t\t\tShift: type = %u, value = %u\n",
op->shift.type, op->shift.value);
if (op->ext != AArch64_EXT_INVALID)
printf("\t\t\tExt: %u\n", op->ext);
if (op->vas != AArch64Layout_Invalid)
printf("\t\t\tVector Arrangement Specifier: 0x%x\n", op->vas);
if (op->vector_index != -1)
printf("\t\t\tVector Index: %u\n", op->vector_index);
}
if (aarch64->update_flags)
printf("\tUpdate-flags: True\n");
if (ins->detail->writeback)
printf("\tWrite-back: True\n");
if (aarch64->cc != AArch64CC_Invalid)
printf("\tCode-condition: %u\n", aarch64->cc);
// Print out all registers accessed by this instruction (either implicit or explicit)
if (!cs_regs_access(handle, ins,
regs_read, &regs_read_count,
regs_write, &regs_write_count)) {
if (regs_read_count) {
printf("\tRegisters read:");
for(i = 0; i < regs_read_count; i++) {
printf(" %s", cs_reg_name(handle, regs_read[i]));
}
printf("\n");
}
if (regs_write_count) {
printf("\tRegisters modified:");
for(i = 0; i < regs_write_count; i++) {
printf(" %s", cs_reg_name(handle, regs_write[i]));
}
printf("\n");
}
}
}

153
cstool/cstool_arm64.c
View File

@ -1,153 +0,0 @@
/* Capstone Disassembler Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
#include <stdio.h>
#include <stdlib.h>
#include <capstone/capstone.h>
#include "cstool.h"
void print_insn_detail_arm64(csh handle, cs_insn *ins)
{
cs_arm64 *arm64;
int i;
cs_regs regs_read, regs_write;
uint8_t regs_read_count, regs_write_count;
uint8_t access;
// detail can be NULL if SKIPDATA option is turned ON
if (ins->detail == NULL)
return;
arm64 = &(ins->detail->arm64);
if (arm64->op_count)
printf("\top_count: %u\n", arm64->op_count);
for (i = 0; i < arm64->op_count; i++) {
cs_arm64_op *op = &(arm64->operands[i]);
switch(op->type) {
default:
break;
case ARM64_OP_REG:
printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
break;
case ARM64_OP_IMM:
printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm);
break;
case ARM64_OP_FP:
#if defined(_KERNEL_MODE)
// Issue #681: Windows kernel does not support formatting float point
printf("\t\toperands[%u].type: FP = <float_point_unsupported>\n", i);
#else
printf("\t\toperands[%u].type: FP = %f\n", i, op->fp);
#endif
break;
case ARM64_OP_MEM:
printf("\t\toperands[%u].type: MEM\n", i);
if (op->mem.base != ARM64_REG_INVALID)
printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base));
if (op->mem.index != ARM64_REG_INVALID)
printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, cs_reg_name(handle, op->mem.index));
if (op->mem.disp != 0)
printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp);
break;
case ARM64_OP_CIMM:
printf("\t\toperands[%u].type: C-IMM = %u\n", i, (int)op->imm);
break;
case ARM64_OP_REG_MRS:
printf("\t\toperands[%u].type: REG_MRS = 0x%x\n", i, op->reg);
break;
case ARM64_OP_REG_MSR:
printf("\t\toperands[%u].type: REG_MSR = 0x%x\n", i, op->reg);
break;
case ARM64_OP_PSTATE:
printf("\t\toperands[%u].type: PSTATE = 0x%x\n", i, op->pstate);
break;
case ARM64_OP_SYS:
printf("\t\toperands[%u].type: SYS = 0x%x\n", i, op->sys);
break;
case ARM64_OP_PREFETCH:
printf("\t\toperands[%u].type: PREFETCH = 0x%x\n", i, op->prefetch);
break;
case ARM64_OP_BARRIER:
printf("\t\toperands[%u].type: BARRIER = 0x%x\n", i, op->barrier);
break;
case ARM64_OP_SVCR:
printf("\t\toperands[%u].type: SYS = 0x%x\n", i, op->sys);
if(op->svcr == ARM64_SVCR_SVCRSM)
printf("\t\t\toperands[%u].svcr: BIT = SM\n", i);
if(op->svcr == ARM64_SVCR_SVCRZA)
printf("\t\t\toperands[%u].svcr: BIT = ZA\n", i);
if(op->svcr == ARM64_SVCR_SVCRSMZA)
printf("\t\t\toperands[%u].svcr: BIT = SM & ZA\n", i);
break;
case ARM64_OP_SME_INDEX:
printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->sme_index.reg));
if (op->sme_index.base != ARM64_REG_INVALID)
printf("\t\t\toperands[%u].index.base: REG = %s\n", i, cs_reg_name(handle, op->sme_index.base));
if (op->sme_index.disp != 0)
printf("\t\t\toperands[%u].index.disp: 0x%x\n", i, op->sme_index.disp);
break;
}
access = op->access;
switch(access) {
default:
break;
case CS_AC_READ:
printf("\t\toperands[%u].access: READ\n", i);
break;
case CS_AC_WRITE:
printf("\t\toperands[%u].access: WRITE\n", i);
break;
case CS_AC_READ | CS_AC_WRITE:
printf("\t\toperands[%u].access: READ | WRITE\n", i);
break;
}
if (op->shift.type != ARM64_SFT_INVALID &&
op->shift.value)
printf("\t\t\tShift: type = %u, value = %u\n",
op->shift.type, op->shift.value);
if (op->ext != ARM64_EXT_INVALID)
printf("\t\t\tExt: %u\n", op->ext);
if (op->vas != ARM64_VAS_INVALID)
printf("\t\t\tVector Arrangement Specifier: 0x%x\n", op->vas);
if (op->vector_index != -1)
printf("\t\t\tVector Index: %u\n", op->vector_index);
}
if (arm64->update_flags)
printf("\tUpdate-flags: True\n");
if (arm64->writeback)
printf("\tWrite-back: True\n");
if (arm64->cc)
printf("\tCode-condition: %u\n", arm64->cc);
// Print out all registers accessed by this instruction (either implicit or explicit)
if (!cs_regs_access(handle, ins,
regs_read, &regs_read_count,
regs_write, &regs_write_count)) {
if (regs_read_count) {
printf("\tRegisters read:");
for(i = 0; i < regs_read_count; i++) {
printf(" %s", cs_reg_name(handle, regs_read[i]));
}
printf("\n");
}
if (regs_write_count) {
printf("\tRegisters modified:");
for(i = 0; i < regs_write_count; i++) {
printf(" %s", cs_reg_name(handle, regs_write[i]));
}
printf("\n");
}
}
}

4751
include/capstone/aarch64.h Normal file
View File

File diff suppressed because it is too large Load Diff

3159
include/capstone/arm64.h
View File

File diff suppressed because it is too large Load Diff

8
include/capstone/capstone.h
View File

@ -74,7 +74,7 @@ typedef size_t csh;
/// Architecture type
typedef enum cs_arch {
CS_ARCH_ARM = 0, ///< ARM architecture (including Thumb, Thumb-2)
CS_ARCH_ARM64, ///< ARM-64, also called AArch64
CS_ARCH_AARCH64, ///< AArch64
CS_ARCH_MIPS, ///< Mips architecture
CS_ARCH_X86, ///< X86 architecture (including x86 & x86-64)
CS_ARCH_PPC, ///< PowerPC architecture
@ -272,7 +272,7 @@ typedef struct cs_opt_skipdata {
/// NOTE: if this callback pointer is NULL, Capstone would skip a number
/// of bytes depending on architectures, as following:
/// Arm: 2 bytes (Thumb mode) or 4 bytes.
/// Arm64: 4 bytes.
/// AArch64: 4 bytes.
/// Mips: 4 bytes.
/// M680x: 1 byte.
/// PowerPC: 4 bytes.
@ -294,7 +294,7 @@ typedef struct cs_opt_skipdata {
#include "arm.h"
#include "arm64.h"
#include "aarch64.h"
#include "m68k.h"
#include "mips.h"
#include "ppc.h"
@ -338,7 +338,7 @@ typedef struct cs_detail {
/// Architecture-specific instruction info
union {
cs_x86 x86; ///< X86 architecture, including 16-bit, 32-bit & 64-bit mode
cs_arm64 arm64; ///< ARM64 architecture (aka AArch64)
cs_aarch64 aarch64; ///< AARCH64 architecture (aka AArch64)
cs_arm arm; ///< ARM architecture (including Thumb/Thumb2)
cs_m68k m68k; ///< M68K architecture
cs_mips mips; ///< MIPS architecture

3
include/capstone/cs_operand.h
View File

@ -26,6 +26,9 @@ typedef enum cs_op_type {
CS_OP_SPECIAL = 0x10, ///< Special operands from archs
CS_OP_MEM =
0x80, ///< Memory operand. Can be ORed with another operand type.
CS_OP_MEM_REG = CS_OP_MEM | CS_OP_REG, ///< Memory referenceing register operand.
CS_OP_MEM_IMM = CS_OP_MEM | CS_OP_IMM, ///< Memory referenceing immediate operand.
} cs_op_type;
/// Common instruction operand access types - to be consistent across all architectures.

2
msvc/capstone.sln
View File

@ -18,7 +18,7 @@ Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "test_arm", "test_arm\test_a
{5B01D900-2359-44CA-9914-6B0C6AFB7BE7} = {5B01D900-2359-44CA-9914-6B0C6AFB7BE7}
EndProjectSection
EndProject
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "test_arm64", "test_arm64\test_arm64.vcxproj", "{CBE31473-7D0E-41F5-AFCB-8C8422ED8908}"
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "test_aarch64", "test_aarch64\test_aarch64.vcxproj", "{CBE31473-7D0E-41F5-AFCB-8C8422ED8908}"
ProjectSection(ProjectDependencies) = postProject
{5B01D900-2359-44CA-9914-6B0C6AFB7BE7} = {5B01D900-2359-44CA-9914-6B0C6AFB7BE7}
EndProjectSection

164
msvc/test_arm64/test_arm64.vcxproj
View File

@ -1,164 +0,0 @@
<?xml version="1.0" encoding="utf-8"?>
<Project DefaultTargets="Build" ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
<ItemGroup Label="ProjectConfigurations">
<ProjectConfiguration Include="Debug|Win32">
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<Platform>Win32</Platform>
</ProjectConfiguration>
<ProjectConfiguration Include="Debug|x64">
<Configuration>Debug</Configuration>
<Platform>x64</Platform>
</ProjectConfiguration>
<ProjectConfiguration Include="Release|Win32">
<Configuration>Release</Configuration>
<Platform>Win32</Platform>
</ProjectConfiguration>
<ProjectConfiguration Include="Release|x64">
<Configuration>Release</Configuration>
<Platform>x64</Platform>
</ProjectConfiguration>
</ItemGroup>
<PropertyGroup Label="Globals">
<ProjectGuid>{CBE31473-7D0E-41F5-AFCB-8C8422ED8908}</ProjectGuid>
<Keyword>Win32Proj</Keyword>
<RootNamespace>capstonetestarm64</RootNamespace>
<ProjectName>test_arm64</ProjectName>
</PropertyGroup>
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.Default.props" />
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'" Label="Configuration">
<ConfigurationType>Application</ConfigurationType>
<UseDebugLibraries>true</UseDebugLibraries>
<CharacterSet>Unicode</CharacterSet>
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<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|x64'" Label="Configuration">
<ConfigurationType>Application</ConfigurationType>
<UseDebugLibraries>true</UseDebugLibraries>
<CharacterSet>Unicode</CharacterSet>
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<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'" Label="Configuration">
<ConfigurationType>Application</ConfigurationType>
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<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|x64'" Label="Configuration">
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<Import Project="$(VCTargetsPath)\Microsoft.Cpp.props" />
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<GenerateDebugInformation>true</GenerateDebugInformation>
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<GenerateDebugInformation>true</GenerateDebugInformation>
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0
suite/auto-sync/CppTranslator/requirements.txt → requirements.txt
View File

2
suite/MC/AArch64/a64-ignored-fields.txt.cs Normal file
View File

@ -0,0 +1,2 @@
# CS_ARCH_AARCH64, 0, None
0xe8,0x23,0x20,0x1e = fcmp s31, #0.0

5
suite/MC/AArch64/arm64-adr.s.cs Normal file
View File

@ -0,0 +1,5 @@
# CS_ARCH_AARCH64, 0, None
0x00,0x00,0x00,0x10 = adr x0, #0
0x00,0x00,0x00,0x30 = adr x0, #1
0x00,0x00,0x00,0x90 = adrp x0, #0
0x00,0x00,0x00,0xb0 = adrp x0, #4096

955
suite/MC/AArch64/arm64-advsimd.s.cs Normal file
View File

@ -0,0 +1,955 @@
# CS_ARCH_AARCH64, 0, None
0x00,0xb8,0x20,0x0e = abs v0.8b, v0.8b
0x00,0xb8,0x20,0x4e = abs v0.16b, v0.16b
0x00,0xb8,0x60,0x0e = abs v0.4h, v0.4h
0x00,0xb8,0x60,0x4e = abs v0.8h, v0.8h
0x00,0xb8,0xa0,0x0e = abs v0.2s, v0.2s
0x00,0xb8,0xa0,0x4e = abs v0.4s, v0.4s
0x00,0x84,0x20,0x0e = add v0.8b, v0.8b, v0.8b
0x00,0x84,0x20,0x4e = add v0.16b, v0.16b, v0.16b
0x00,0x84,0x60,0x0e = add v0.4h, v0.4h, v0.4h
0x00,0x84,0x60,0x4e = add v0.8h, v0.8h, v0.8h
0x00,0x84,0xa0,0x0e = add v0.2s, v0.2s, v0.2s
0x00,0x84,0xa0,0x4e = add v0.4s, v0.4s, v0.4s
0x00,0x84,0xe0,0x4e = add v0.2d, v0.2d, v0.2d
0x41,0x84,0xe3,0x5e = add d1, d2, d3
0x00,0x40,0x20,0x0e = addhn v0.8b, v0.8h, v0.8h
0x00,0x40,0x20,0x4e = addhn2 v0.16b, v0.8h, v0.8h
0x00,0x40,0x60,0x0e = addhn v0.4h, v0.4s, v0.4s
0x00,0x40,0x60,0x4e = addhn2 v0.8h, v0.4s, v0.4s
0x00,0x40,0xa0,0x0e = addhn v0.2s, v0.2d, v0.2d
0x00,0x40,0xa0,0x4e = addhn2 v0.4s, v0.2d, v0.2d
0x00,0xbc,0x20,0x0e = addp v0.8b, v0.8b, v0.8b
0x00,0xbc,0x20,0x4e = addp v0.16b, v0.16b, v0.16b
0x00,0xbc,0x60,0x0e = addp v0.4h, v0.4h, v0.4h
0x00,0xbc,0x60,0x4e = addp v0.8h, v0.8h, v0.8h
0x00,0xbc,0xa0,0x0e = addp v0.2s, v0.2s, v0.2s
0x00,0xbc,0xa0,0x4e = addp v0.4s, v0.4s, v0.4s
0x00,0xbc,0xe0,0x4e = addp v0.2d, v0.2d, v0.2d
0x00,0xb8,0xf1,0x5e = addp d0, v0.2d
0x00,0xb8,0x31,0x0e = addv b0, v0.8b
0x00,0xb8,0x31,0x4e = addv b0, v0.16b
0x00,0xb8,0x71,0x0e = addv h0, v0.4h
0x00,0xb8,0x71,0x4e = addv h0, v0.8h
0x00,0xb8,0xb1,0x4e = addv s0, v0.4s
0x60,0x0c,0x08,0x4e = dup v0.2d, x3
0x60,0x0c,0x04,0x4e = dup v0.4s, w3
0x60,0x0c,0x04,0x0e = dup v0.2s, w3
0x60,0x0c,0x02,0x4e = dup v0.8h, w3
0x60,0x0c,0x02,0x0e = dup v0.4h, w3
0x60,0x0c,0x01,0x4e = dup v0.16b, w3
0x60,0x0c,0x01,0x0e = dup v0.8b, w3
0x61,0x0c,0x08,0x4e = dup v1.2d, x3
0x82,0x0c,0x04,0x4e = dup v2.4s, w4
0xa3,0x0c,0x04,0x0e = dup v3.2s, w5
0xc4,0x0c,0x02,0x4e = dup v4.8h, w6
0xe5,0x0c,0x02,0x0e = dup v5.4h, w7
0x06,0x0d,0x01,0x4e = dup v6.16b, w8
0x27,0x0d,0x01,0x0e = dup v7.8b, w9
0x60,0x04,0x18,0x4e = dup v0.2d, v3.d[1]
0x60,0x04,0x0c,0x0e = dup v0.2s, v3.s[1]
0x60,0x04,0x0c,0x4e = dup v0.4s, v3.s[1]
0x60,0x04,0x06,0x0e = dup v0.4h, v3.h[1]
0x60,0x04,0x06,0x4e = dup v0.8h, v3.h[1]
0x60,0x04,0x03,0x0e = dup v0.8b, v3.b[1]
0x60,0x04,0x03,0x4e = dup v0.16b, v3.b[1]
0x27,0x05,0x18,0x4e = dup v7.2d, v9.d[1]
0x06,0x05,0x0c,0x0e = dup v6.2s, v8.s[1]
0xe5,0x04,0x14,0x4e = dup v5.4s, v7.s[2]
0xc4,0x04,0x0e,0x0e = dup v4.4h, v6.h[3]
0xa3,0x04,0x12,0x4e = dup v3.8h, v5.h[4]
0x82,0x04,0x0b,0x0e = dup v2.8b, v4.b[5]
0x61,0x04,0x0d,0x4e = dup v1.16b, v3.b[6]
0x83,0x04,0x03,0x5e = mov b3, v4.b[1]
0x83,0x04,0x06,0x5e = mov h3, v4.h[1]
0x83,0x04,0x0c,0x5e = mov s3, v4.s[1]
0x83,0x04,0x18,0x5e = mov d3, v4.d[1]
0x83,0x04,0x03,0x5e = mov b3, v4.b[1]
0x83,0x04,0x06,0x5e = mov h3, v4.h[1]
0x83,0x04,0x0c,0x5e = mov s3, v4.s[1]
0x83,0x04,0x18,0x5e = mov d3, v4.d[1]
0x83,0x04,0x03,0x5e = mov b3, v4.b[1]
0x83,0x04,0x06,0x5e = mov h3, v4.h[1]
0x83,0x04,0x0c,0x5e = mov s3, v4.s[1]
0x83,0x04,0x18,0x5e = mov d3, v4.d[1]
0x83,0x04,0x03,0x5e = mov b3, v4.b[1]
0x83,0x04,0x06,0x5e = mov h3, v4.h[1]
0x83,0x04,0x0c,0x5e = mov s3, v4.s[1]
0x83,0x04,0x18,0x5e = mov d3, v4.d[1]
0x43,0x2c,0x14,0x4e = smov x3, v2.s[2]
0x43,0x2c,0x14,0x4e = smov x3, v2.s[2]
0x43,0x3c,0x14,0x0e = mov w3, v2.s[2]
0x43,0x3c,0x14,0x0e = mov w3, v2.s[2]
0x43,0x3c,0x18,0x4e = mov x3, v2.d[1]
0x43,0x3c,0x18,0x4e = mov x3, v2.d[1]
0x62,0x3c,0x1c,0x0e = mov w2, v3.s[3]
0xe5,0x3c,0x14,0x0e = mov w5, v7.s[2]
0xab,0x3d,0x18,0x4e = mov x11, v13.d[1]
0x71,0x3e,0x08,0x4e = mov x17, v19.d[0]
0xa2,0x1c,0x18,0x4e = mov v2.d[1], x5
0xa2,0x1c,0x0c,0x4e = mov v2.s[1], w5
0xa2,0x1c,0x06,0x4e = mov v2.h[1], w5
0xa2,0x1c,0x03,0x4e = mov v2.b[1], w5
0xa2,0x1c,0x18,0x4e = mov v2.d[1], x5
0xa2,0x1c,0x0c,0x4e = mov v2.s[1], w5
0xa2,0x1c,0x06,0x4e = mov v2.h[1], w5
0xa2,0x1c,0x03,0x4e = mov v2.b[1], w5
0xe2,0x45,0x18,0x6e = mov v2.d[1], v15.d[1]
0xe2,0x25,0x0c,0x6e = mov v2.s[1], v15.s[1]
0xe2,0x15,0x06,0x6e = mov v2.h[1], v15.h[1]
0xe2,0x0d,0x03,0x6e = mov v2.b[1], v15.b[1]
0xe2,0x05,0x18,0x6e = mov v2.d[1], v15.d[0]
0xe2,0x45,0x1c,0x6e = mov v2.s[3], v15.s[2]
0xe2,0x35,0x1e,0x6e = mov v2.h[7], v15.h[3]
0xe2,0x2d,0x15,0x6e = mov v2.b[10], v15.b[5]
0xa2,0x1c,0x18,0x4e = mov v2.d[1], x5
0xc3,0x1c,0x0c,0x4e = mov v3.s[1], w6
0xe4,0x1c,0x06,0x4e = mov v4.h[1], w7
0x05,0x1d,0x03,0x4e = mov v5.b[1], w8
0x49,0x1c,0x18,0x4e = mov v9.d[1], x2
0x68,0x1c,0x0c,0x4e = mov v8.s[1], w3
0x87,0x1c,0x06,0x4e = mov v7.h[1], w4
0xa6,0x1c,0x03,0x4e = mov v6.b[1], w5
0x41,0x45,0x18,0x6e = mov v1.d[1], v10.d[1]
0x62,0x25,0x0c,0x6e = mov v2.s[1], v11.s[1]
0x87,0x15,0x06,0x6e = mov v7.h[1], v12.h[1]
0xe8,0x0d,0x03,0x6e = mov v8.b[1], v15.b[1]
0xe2,0x05,0x18,0x6e = mov v2.d[1], v15.d[0]
0x07,0x46,0x1c,0x6e = mov v7.s[3], v16.s[2]
0x28,0x36,0x1e,0x6e = mov v8.h[7], v17.h[3]
0x49,0x2e,0x15,0x6e = mov v9.b[10], v18.b[5]
0x00,0x1c,0x20,0x0e = and v0.8b, v0.8b, v0.8b
0x00,0x1c,0x20,0x4e = and v0.16b, v0.16b, v0.16b
0x00,0x1c,0x60,0x0e = bic v0.8b, v0.8b, v0.8b
0x00,0x8c,0x20,0x2e = cmeq v0.8b, v0.8b, v0.8b
0x00,0x3c,0x20,0x0e = cmge v0.8b, v0.8b, v0.8b
0x00,0x34,0x20,0x0e = cmgt v0.8b, v0.8b, v0.8b
0x00,0x34,0x20,0x2e = cmhi v0.8b, v0.8b, v0.8b
0x00,0x3c,0x20,0x2e = cmhs v0.8b, v0.8b, v0.8b
0x00,0x8c,0x20,0x0e = cmtst v0.8b, v0.8b, v0.8b
0x00,0xd4,0xa0,0x2e = fabd v0.2s, v0.2s, v0.2s
0x00,0xec,0x20,0x2e = facge v0.2s, v0.2s, v0.2s
0x00,0xec,0xa0,0x2e = facgt v0.2s, v0.2s, v0.2s
0x00,0xd4,0x20,0x2e = faddp v0.2s, v0.2s, v0.2s
0x00,0xd4,0x20,0x0e = fadd v0.2s, v0.2s, v0.2s
0x00,0xe4,0x20,0x0e = fcmeq v0.2s, v0.2s, v0.2s
0x00,0xe4,0x20,0x2e = fcmge v0.2s, v0.2s, v0.2s
0x00,0xe4,0xa0,0x2e = fcmgt v0.2s, v0.2s, v0.2s
0x00,0xfc,0x20,0x2e = fdiv v0.2s, v0.2s, v0.2s
0x00,0xc4,0x20,0x2e = fmaxnmp v0.2s, v0.2s, v0.2s
0x00,0xc4,0x20,0x0e = fmaxnm v0.2s, v0.2s, v0.2s
0x00,0xf4,0x20,0x2e = fmaxp v0.2s, v0.2s, v0.2s
0x00,0xf4,0x20,0x0e = fmax v0.2s, v0.2s, v0.2s
0x00,0xc4,0xa0,0x2e = fminnmp v0.2s, v0.2s, v0.2s
0x00,0xc4,0xa0,0x0e = fminnm v0.2s, v0.2s, v0.2s
0x00,0xf4,0xa0,0x2e = fminp v0.2s, v0.2s, v0.2s
0x00,0xf4,0xa0,0x0e = fmin v0.2s, v0.2s, v0.2s
0x00,0xcc,0x20,0x0e = fmla v0.2s, v0.2s, v0.2s
0x00,0xcc,0xa0,0x0e = fmls v0.2s, v0.2s, v0.2s
0x00,0xdc,0x20,0x0e = fmulx v0.2s, v0.2s, v0.2s
0x00,0xdc,0x20,0x2e = fmul v0.2s, v0.2s, v0.2s
0x62,0xdc,0x61,0x5e = fmulx d2, d3, d1
0x62,0xdc,0x21,0x5e = fmulx s2, s3, s1
0x00,0xfc,0x20,0x0e = frecps v0.2s, v0.2s, v0.2s
0x00,0xfc,0xa0,0x0e = frsqrts v0.2s, v0.2s, v0.2s
0x00,0xd4,0xa0,0x0e = fsub v0.2s, v0.2s, v0.2s
0x00,0x94,0x20,0x0e = mla v0.8b, v0.8b, v0.8b
0x00,0x94,0x20,0x2e = mls v0.8b, v0.8b, v0.8b
0x00,0x9c,0x20,0x0e = mul v0.8b, v0.8b, v0.8b
0x00,0x9c,0x20,0x2e = pmul v0.8b, v0.8b, v0.8b
0x00,0x7c,0x20,0x0e = saba v0.8b, v0.8b, v0.8b
0x00,0x74,0x20,0x0e = sabd v0.8b, v0.8b, v0.8b
0x00,0x04,0x20,0x0e = shadd v0.8b, v0.8b, v0.8b
0x00,0x24,0x20,0x0e = shsub v0.8b, v0.8b, v0.8b
0x00,0xa4,0x20,0x0e = smaxp v0.8b, v0.8b, v0.8b
0x00,0x64,0x20,0x0e = smax v0.8b, v0.8b, v0.8b
0x00,0xac,0x20,0x0e = sminp v0.8b, v0.8b, v0.8b
0x00,0x6c,0x20,0x0e = smin v0.8b, v0.8b, v0.8b
0x00,0x0c,0x20,0x0e = sqadd v0.8b, v0.8b, v0.8b
0x00,0xb4,0x60,0x0e = sqdmulh v0.4h, v0.4h, v0.4h
0x00,0xb4,0x60,0x2e = sqrdmulh v0.4h, v0.4h, v0.4h
0x00,0x5c,0x20,0x0e = sqrshl v0.8b, v0.8b, v0.8b
0x00,0x4c,0x20,0x0e = sqshl v0.8b, v0.8b, v0.8b
0x00,0x2c,0x20,0x0e = sqsub v0.8b, v0.8b, v0.8b
0x00,0x14,0x20,0x0e = srhadd v0.8b, v0.8b, v0.8b
0x00,0x54,0x20,0x0e = srshl v0.8b, v0.8b, v0.8b
0x00,0x44,0x20,0x0e = sshl v0.8b, v0.8b, v0.8b
0x00,0x84,0x20,0x2e = sub v0.8b, v0.8b, v0.8b
0x00,0x7c,0x20,0x2e = uaba v0.8b, v0.8b, v0.8b
0x00,0x74,0x20,0x2e = uabd v0.8b, v0.8b, v0.8b
0x00,0x04,0x20,0x2e = uhadd v0.8b, v0.8b, v0.8b
0x00,0x24,0x20,0x2e = uhsub v0.8b, v0.8b, v0.8b
0x00,0xa4,0x20,0x2e = umaxp v0.8b, v0.8b, v0.8b
0x00,0x64,0x20,0x2e = umax v0.8b, v0.8b, v0.8b
0x00,0xac,0x20,0x2e = uminp v0.8b, v0.8b, v0.8b
0x00,0x6c,0x20,0x2e = umin v0.8b, v0.8b, v0.8b
0x00,0x0c,0x20,0x2e = uqadd v0.8b, v0.8b, v0.8b
0x00,0x5c,0x20,0x2e = uqrshl v0.8b, v0.8b, v0.8b
0x00,0x4c,0x20,0x2e = uqshl v0.8b, v0.8b, v0.8b
0x00,0x2c,0x20,0x2e = uqsub v0.8b, v0.8b, v0.8b
0x00,0x14,0x20,0x2e = urhadd v0.8b, v0.8b, v0.8b
0x00,0x54,0x20,0x2e = urshl v0.8b, v0.8b, v0.8b
0x00,0x44,0x20,0x2e = ushl v0.8b, v0.8b, v0.8b
0x00,0x14,0xc0,0x2e = fabd v0.4h, v0.4h, v0.4h
0x00,0x2c,0x40,0x2e = facge v0.4h, v0.4h, v0.4h
0x00,0x2c,0xc0,0x2e = facgt v0.4h, v0.4h, v0.4h
0x00,0x14,0x40,0x2e = faddp v0.4h, v0.4h, v0.4h
0x00,0x14,0x40,0x0e = fadd v0.4h, v0.4h, v0.4h
0x00,0x24,0x40,0x0e = fcmeq v0.4h, v0.4h, v0.4h
0x00,0x24,0x40,0x2e = fcmge v0.4h, v0.4h, v0.4h
0x00,0x24,0xc0,0x2e = fcmgt v0.4h, v0.4h, v0.4h
0x00,0x3c,0x40,0x2e = fdiv v0.4h, v0.4h, v0.4h
0x00,0x04,0x40,0x2e = fmaxnmp v0.4h, v0.4h, v0.4h
0x00,0x04,0x40,0x0e = fmaxnm v0.4h, v0.4h, v0.4h
0x00,0x34,0x40,0x2e = fmaxp v0.4h, v0.4h, v0.4h
0x00,0x34,0x40,0x0e = fmax v0.4h, v0.4h, v0.4h
0x00,0x04,0xc0,0x2e = fminnmp v0.4h, v0.4h, v0.4h
0x00,0x04,0xc0,0x0e = fminnm v0.4h, v0.4h, v0.4h
0x00,0x34,0xc0,0x2e = fminp v0.4h, v0.4h, v0.4h
0x00,0x34,0xc0,0x0e = fmin v0.4h, v0.4h, v0.4h
0x00,0x0c,0x40,0x0e = fmla v0.4h, v0.4h, v0.4h
0x00,0x0c,0xc0,0x0e = fmls v0.4h, v0.4h, v0.4h
0x00,0x1c,0x40,0x0e = fmulx v0.4h, v0.4h, v0.4h
0x00,0x1c,0x40,0x2e = fmul v0.4h, v0.4h, v0.4h
0x00,0x3c,0x40,0x0e = frecps v0.4h, v0.4h, v0.4h
0x00,0x3c,0xc0,0x0e = frsqrts v0.4h, v0.4h, v0.4h
0x00,0x14,0xc0,0x0e = fsub v0.4h, v0.4h, v0.4h
0x00,0x14,0xc0,0x6e = fabd v0.8h, v0.8h, v0.8h
0x00,0x2c,0x40,0x6e = facge v0.8h, v0.8h, v0.8h
0x00,0x2c,0xc0,0x6e = facgt v0.8h, v0.8h, v0.8h
0x00,0x14,0x40,0x6e = faddp v0.8h, v0.8h, v0.8h
0x00,0x14,0x40,0x4e = fadd v0.8h, v0.8h, v0.8h
0x00,0x24,0x40,0x4e = fcmeq v0.8h, v0.8h, v0.8h
0x00,0x24,0x40,0x6e = fcmge v0.8h, v0.8h, v0.8h
0x00,0x24,0xc0,0x6e = fcmgt v0.8h, v0.8h, v0.8h
0x00,0x3c,0x40,0x6e = fdiv v0.8h, v0.8h, v0.8h
0x00,0x04,0x40,0x6e = fmaxnmp v0.8h, v0.8h, v0.8h
0x00,0x04,0x40,0x4e = fmaxnm v0.8h, v0.8h, v0.8h
0x00,0x34,0x40,0x6e = fmaxp v0.8h, v0.8h, v0.8h
0x00,0x34,0x40,0x4e = fmax v0.8h, v0.8h, v0.8h
0x00,0x04,0xc0,0x6e = fminnmp v0.8h, v0.8h, v0.8h
0x00,0x04,0xc0,0x4e = fminnm v0.8h, v0.8h, v0.8h
0x00,0x34,0xc0,0x6e = fminp v0.8h, v0.8h, v0.8h
0x00,0x34,0xc0,0x4e = fmin v0.8h, v0.8h, v0.8h
0x00,0x0c,0x40,0x4e = fmla v0.8h, v0.8h, v0.8h
0x00,0x0c,0xc0,0x4e = fmls v0.8h, v0.8h, v0.8h
0x00,0x1c,0x40,0x4e = fmulx v0.8h, v0.8h, v0.8h
0x00,0x1c,0x40,0x6e = fmul v0.8h, v0.8h, v0.8h
0x00,0x3c,0x40,0x4e = frecps v0.8h, v0.8h, v0.8h
0x00,0x3c,0xc0,0x4e = frsqrts v0.8h, v0.8h, v0.8h
0x00,0x14,0xc0,0x4e = fsub v0.8h, v0.8h, v0.8h
0x00,0x1c,0xe0,0x2e = bif v0.8b, v0.8b, v0.8b
0x00,0x1c,0xa0,0x2e = bit v0.8b, v0.8b, v0.8b
0x00,0x1c,0x60,0x2e = bsl v0.8b, v0.8b, v0.8b
0x00,0x1c,0x20,0x2e = eor v0.8b, v0.8b, v0.8b
0x00,0x1c,0xe0,0x0e = orn v0.8b, v0.8b, v0.8b
0x00,0x1c,0xa1,0x0e = orr v0.8b, v0.8b, v1.8b
0x00,0x68,0x20,0x0e = sadalp v0.4h, v0.8b
0x00,0x68,0x20,0x4e = sadalp v0.8h, v0.16b
0x00,0x68,0x60,0x0e = sadalp v0.2s, v0.4h
0x00,0x68,0x60,0x4e = sadalp v0.4s, v0.8h
0x00,0x68,0xa0,0x0e = sadalp v0.1d, v0.2s
0x00,0x68,0xa0,0x4e = sadalp v0.2d, v0.4s
0x00,0x48,0x20,0x0e = cls v0.8b, v0.8b
0x00,0x48,0x20,0x2e = clz v0.8b, v0.8b
0x00,0x58,0x20,0x0e = cnt v0.8b, v0.8b
0x00,0xf8,0xa0,0x0e = fabs v0.2s, v0.2s
0x00,0xf8,0xa0,0x2e = fneg v0.2s, v0.2s
0x00,0xd8,0xa1,0x0e = frecpe v0.2s, v0.2s
0x00,0x88,0x21,0x2e = frinta v0.2s, v0.2s
0x00,0x98,0x21,0x2e = frintx v0.2s, v0.2s
0x00,0x98,0xa1,0x2e = frinti v0.2s, v0.2s
0x00,0x98,0x21,0x0e = frintm v0.2s, v0.2s
0x00,0x88,0x21,0x0e = frintn v0.2s, v0.2s
0x00,0x88,0xa1,0x0e = frintp v0.2s, v0.2s
0x00,0x98,0xa1,0x0e = frintz v0.2s, v0.2s
0x00,0xd8,0xa1,0x2e = frsqrte v0.2s, v0.2s
0x00,0xf8,0xa1,0x2e = fsqrt v0.2s, v0.2s
0x00,0xb8,0x20,0x2e = neg v0.8b, v0.8b
0x00,0x58,0x20,0x2e = mvn v0.8b, v0.8b
0x00,0x58,0x60,0x2e = rbit v0.8b, v0.8b
0x00,0x18,0x20,0x0e = rev16 v0.8b, v0.8b
0x00,0x08,0x20,0x2e = rev32 v0.8b, v0.8b
0x00,0x08,0x20,0x0e = rev64 v0.8b, v0.8b
0x00,0x68,0x20,0x0e = sadalp v0.4h, v0.8b
0x00,0x28,0x20,0x0e = saddlp v0.4h, v0.8b
0x00,0xd8,0x21,0x0e = scvtf v0.2s, v0.2s
0x00,0x78,0x20,0x0e = sqabs v0.8b, v0.8b
0x00,0x78,0x20,0x2e = sqneg v0.8b, v0.8b
0x00,0x48,0x21,0x0e = sqxtn v0.8b, v0.8h
0x00,0x28,0x21,0x2e = sqxtun v0.8b, v0.8h
0x00,0x38,0x20,0x0e = suqadd v0.8b, v0.8b
0x00,0x68,0x20,0x2e = uadalp v0.4h, v0.8b
0x00,0x28,0x20,0x2e = uaddlp v0.4h, v0.8b
0x00,0xd8,0x21,0x2e = ucvtf v0.2s, v0.2s
0x00,0x48,0x21,0x2e = uqxtn v0.8b, v0.8h
0x00,0xc8,0xa1,0x0e = urecpe v0.2s, v0.2s
0x00,0xc8,0xa1,0x2e = ursqrte v0.2s, v0.2s
0x00,0x38,0x20,0x2e = usqadd v0.8b, v0.8b
0x00,0x28,0x21,0x0e = xtn v0.8b, v0.8h
0x41,0x38,0x21,0x2e = shll v1.8h, v2.8b, #8
0x83,0x38,0x61,0x2e = shll v3.4s, v4.4h, #16
0xc5,0x38,0xa1,0x2e = shll v5.2d, v6.2s, #32
0x07,0x39,0x21,0x6e = shll2 v7.8h, v8.16b, #8
0x49,0x39,0x61,0x6e = shll2 v9.4s, v10.8h, #16
0x8b,0x39,0xa1,0x6e = shll2 v11.2d, v12.4s, #32
0x41,0x38,0x21,0x2e = shll v1.8h, v2.8b, #8
0x41,0x38,0x61,0x2e = shll v1.4s, v2.4h, #16
0x41,0x38,0xa1,0x2e = shll v1.2d, v2.2s, #32
0x41,0x38,0x21,0x6e = shll2 v1.8h, v2.16b, #8
0x41,0x38,0x61,0x6e = shll2 v1.4s, v2.8h, #16
0x41,0x38,0xa1,0x6e = shll2 v1.2d, v2.4s, #32
0x00,0xf8,0xf8,0x0e = fabs v0.4h, v0.4h
0x00,0xf8,0xf8,0x2e = fneg v0.4h, v0.4h
0x00,0xd8,0xf9,0x0e = frecpe v0.4h, v0.4h
0x00,0x88,0x79,0x2e = frinta v0.4h, v0.4h
0x00,0x98,0x79,0x2e = frintx v0.4h, v0.4h
0x00,0x98,0xf9,0x2e = frinti v0.4h, v0.4h
0x00,0x98,0x79,0x0e = frintm v0.4h, v0.4h
0x00,0x88,0x79,0x0e = frintn v0.4h, v0.4h
0x00,0x88,0xf9,0x0e = frintp v0.4h, v0.4h
0x00,0x98,0xf9,0x0e = frintz v0.4h, v0.4h
0x00,0xd8,0xf9,0x2e = frsqrte v0.4h, v0.4h
0x00,0xf8,0xf9,0x2e = fsqrt v0.4h, v0.4h
0x00,0xf8,0xf8,0x4e = fabs v0.8h, v0.8h
0x00,0xf8,0xf8,0x6e = fneg v0.8h, v0.8h
0x00,0xd8,0xf9,0x4e = frecpe v0.8h, v0.8h
0x00,0x88,0x79,0x6e = frinta v0.8h, v0.8h
0x00,0x98,0x79,0x6e = frintx v0.8h, v0.8h
0x00,0x98,0xf9,0x6e = frinti v0.8h, v0.8h
0x00,0x98,0x79,0x4e = frintm v0.8h, v0.8h
0x00,0x88,0x79,0x4e = frintn v0.8h, v0.8h
0x00,0x88,0xf9,0x4e = frintp v0.8h, v0.8h
0x00,0x98,0xf9,0x4e = frintz v0.8h, v0.8h
0x00,0xd8,0xf9,0x6e = frsqrte v0.8h, v0.8h
0x00,0xf8,0xf9,0x6e = fsqrt v0.8h, v0.8h
0x00,0x98,0x20,0x0e = cmeq v0.8b, v0.8b, #0
0x00,0x98,0x20,0x4e = cmeq v0.16b, v0.16b, #0
0x00,0x98,0x60,0x0e = cmeq v0.4h, v0.4h, #0
0x00,0x98,0x60,0x4e = cmeq v0.8h, v0.8h, #0
0x00,0x98,0xa0,0x0e = cmeq v0.2s, v0.2s, #0
0x00,0x98,0xa0,0x4e = cmeq v0.4s, v0.4s, #0
0x00,0x98,0xe0,0x4e = cmeq v0.2d, v0.2d, #0
0x00,0x88,0x20,0x2e = cmge v0.8b, v0.8b, #0
0x00,0x88,0x20,0x0e = cmgt v0.8b, v0.8b, #0
0x00,0x98,0x20,0x2e = cmle v0.8b, v0.8b, #0
0x00,0xa8,0x20,0x0e = cmlt v0.8b, v0.8b, #0
0x00,0xd8,0xa0,0x0e = fcmeq v0.2s, v0.2s, #0.0
0x00,0xc8,0xa0,0x2e = fcmge v0.2s, v0.2s, #0.0
0x00,0xc8,0xa0,0x0e = fcmgt v0.2s, v0.2s, #0.0
0x00,0xd8,0xa0,0x2e = fcmle v0.2s, v0.2s, #0.0
0x00,0xe8,0xa0,0x0e = fcmlt v0.2s, v0.2s, #0.0
0xc8,0xa9,0x20,0x0e = cmlt v8.8b, v14.8b, #0
0xc8,0xa9,0x20,0x4e = cmlt v8.16b, v14.16b, #0
0xc8,0xa9,0x60,0x0e = cmlt v8.4h, v14.4h, #0
0xc8,0xa9,0x60,0x4e = cmlt v8.8h, v14.8h, #0
0xc8,0xa9,0xa0,0x0e = cmlt v8.2s, v14.2s, #0
0xc8,0xa9,0xa0,0x4e = cmlt v8.4s, v14.4s, #0
0xc8,0xa9,0xe0,0x4e = cmlt v8.2d, v14.2d, #0
0x00,0xc8,0x21,0x0e = fcvtas v0.2s, v0.2s
0x00,0xc8,0x21,0x4e = fcvtas v0.4s, v0.4s
0x00,0xc8,0x61,0x4e = fcvtas v0.2d, v0.2d
0x00,0xc8,0x21,0x5e = fcvtas s0, s0
0x00,0xc8,0x61,0x5e = fcvtas d0, d0
0x00,0xc8,0x21,0x2e = fcvtau v0.2s, v0.2s
0x00,0xc8,0x21,0x6e = fcvtau v0.4s, v0.4s
0x00,0xc8,0x61,0x6e = fcvtau v0.2d, v0.2d
0x00,0xc8,0x21,0x7e = fcvtau s0, s0
0x00,0xc8,0x61,0x7e = fcvtau d0, d0
0xa1,0x78,0x21,0x0e = fcvtl v1.4s, v5.4h
0xc2,0x78,0x61,0x0e = fcvtl v2.2d, v6.2s
0xe3,0x78,0x21,0x4e = fcvtl2 v3.4s, v7.8h
0x04,0x79,0x61,0x4e = fcvtl2 v4.2d, v8.4s
0x00,0xb8,0x21,0x0e = fcvtms v0.2s, v0.2s
0x00,0xb8,0x21,0x4e = fcvtms v0.4s, v0.4s
0x00,0xb8,0x61,0x4e = fcvtms v0.2d, v0.2d
0x00,0xb8,0x21,0x5e = fcvtms s0, s0
0x00,0xb8,0x61,0x5e = fcvtms d0, d0
0x00,0xb8,0x21,0x2e = fcvtmu v0.2s, v0.2s
0x00,0xb8,0x21,0x6e = fcvtmu v0.4s, v0.4s
0x00,0xb8,0x61,0x6e = fcvtmu v0.2d, v0.2d
0x00,0xb8,0x21,0x7e = fcvtmu s0, s0
0x00,0xb8,0x61,0x7e = fcvtmu d0, d0
0x00,0xa8,0x21,0x0e = fcvtns v0.2s, v0.2s
0x00,0xa8,0x21,0x4e = fcvtns v0.4s, v0.4s
0x00,0xa8,0x61,0x4e = fcvtns v0.2d, v0.2d
0x00,0xa8,0x21,0x5e = fcvtns s0, s0
0x00,0xa8,0x61,0x5e = fcvtns d0, d0
0x00,0xa8,0x21,0x2e = fcvtnu v0.2s, v0.2s
0x00,0xa8,0x21,0x6e = fcvtnu v0.4s, v0.4s
0x00,0xa8,0x61,0x6e = fcvtnu v0.2d, v0.2d
0x00,0xa8,0x21,0x7e = fcvtnu s0, s0
0x00,0xa8,0x61,0x7e = fcvtnu d0, d0
0x82,0x68,0x21,0x0e = fcvtn v2.4h, v4.4s
0xa3,0x68,0x61,0x0e = fcvtn v3.2s, v5.2d
0xc4,0x68,0x21,0x4e = fcvtn2 v4.8h, v6.4s
0xe5,0x68,0x61,0x4e = fcvtn2 v5.4s, v7.2d
0x26,0x69,0x61,0x2e = fcvtxn v6.2s, v9.2d
0x07,0x69,0x61,0x6e = fcvtxn2 v7.4s, v8.2d
0x00,0xa8,0xa1,0x0e = fcvtps v0.2s, v0.2s
0x00,0xa8,0xa1,0x4e = fcvtps v0.4s, v0.4s
0x00,0xa8,0xe1,0x4e = fcvtps v0.2d, v0.2d
0x00,0xa8,0xa1,0x5e = fcvtps s0, s0
0x00,0xa8,0xe1,0x5e = fcvtps d0, d0
0x00,0xa8,0xa1,0x2e = fcvtpu v0.2s, v0.2s
0x00,0xa8,0xa1,0x6e = fcvtpu v0.4s, v0.4s
0x00,0xa8,0xe1,0x6e = fcvtpu v0.2d, v0.2d
0x00,0xa8,0xa1,0x7e = fcvtpu s0, s0
0x00,0xa8,0xe1,0x7e = fcvtpu d0, d0
0x00,0xb8,0xa1,0x0e = fcvtzs v0.2s, v0.2s
0x00,0xb8,0xa1,0x4e = fcvtzs v0.4s, v0.4s
0x00,0xb8,0xe1,0x4e = fcvtzs v0.2d, v0.2d
0x00,0xb8,0xa1,0x5e = fcvtzs s0, s0
0x00,0xb8,0xe1,0x5e = fcvtzs d0, d0
0x00,0xb8,0xa1,0x2e = fcvtzu v0.2s, v0.2s
0x00,0xb8,0xa1,0x6e = fcvtzu v0.4s, v0.4s
0x00,0xb8,0xe1,0x6e = fcvtzu v0.2d, v0.2d
0x00,0xb8,0xa1,0x7e = fcvtzu s0, s0
0x00,0xb8,0xe1,0x7e = fcvtzu d0, d0
0x20,0x14,0x00,0x2f = bic v0.2s, #1
0x20,0x14,0x00,0x2f = bic v0.2s, #1
0x20,0x34,0x00,0x2f = bic v0.2s, #1, lsl #8
0x20,0x54,0x00,0x2f = bic v0.2s, #1, lsl #16
0x20,0x74,0x00,0x2f = bic v0.2s, #1, lsl #24
0x20,0x94,0x00,0x2f = bic v0.4h, #1
0x20,0x94,0x00,0x2f = bic v0.4h, #1
0x20,0xb4,0x00,0x2f = bic v0.4h, #1, lsl #8
0x20,0x14,0x00,0x6f = bic v0.4s, #1
0x20,0x14,0x00,0x6f = bic v0.4s, #1
0x20,0x34,0x00,0x6f = bic v0.4s, #1, lsl #8
0x20,0x54,0x00,0x6f = bic v0.4s, #1, lsl #16
0x20,0x74,0x00,0x6f = bic v0.4s, #1, lsl #24
0x20,0x94,0x00,0x6f = bic v0.8h, #1
0x20,0x94,0x00,0x6f = bic v0.8h, #1
0x20,0xb4,0x00,0x6f = bic v0.8h, #1, lsl #8
0x00,0xf4,0x02,0x6f = fmov v0.2d, #0.12500000
0x00,0xf4,0x02,0x0f = fmov v0.2s, #0.12500000
0x00,0xf4,0x02,0x4f = fmov v0.4s, #0.12500000
0x20,0x14,0x00,0x0f = orr v0.2s, #1
0x20,0x14,0x00,0x0f = orr v0.2s, #1
0x20,0x34,0x00,0x0f = orr v0.2s, #1, lsl #8
0x20,0x54,0x00,0x0f = orr v0.2s, #1, lsl #16
0x20,0x74,0x00,0x0f = orr v0.2s, #1, lsl #24
0x20,0x94,0x00,0x0f = orr v0.4h, #1
0x20,0x94,0x00,0x0f = orr v0.4h, #1
0x20,0xb4,0x00,0x0f = orr v0.4h, #1, lsl #8
0x20,0x14,0x00,0x4f = orr v0.4s, #1
0x20,0x14,0x00,0x4f = orr v0.4s, #1
0x20,0x34,0x00,0x4f = orr v0.4s, #1, lsl #8
0x20,0x54,0x00,0x4f = orr v0.4s, #1, lsl #16
0x20,0x74,0x00,0x4f = orr v0.4s, #1, lsl #24
0x20,0x94,0x00,0x4f = orr v0.8h, #1
0x20,0x94,0x00,0x4f = orr v0.8h, #1
0x20,0xb4,0x00,0x4f = orr v0.8h, #1, lsl #8
0x20,0xe4,0x00,0x2f = movi d0, #0x000000000000ff
0x20,0xe4,0x00,0x6f = movi v0.2d, #0x000000000000ff
0x20,0x04,0x00,0x0f = movi v0.2s, #1
0x20,0x04,0x00,0x0f = movi v0.2s, #1
0x20,0x24,0x00,0x0f = movi v0.2s, #1, lsl #8
0x20,0x44,0x00,0x0f = movi v0.2s, #1, lsl #16
0x20,0x64,0x00,0x0f = movi v0.2s, #1, lsl #24
0x20,0x04,0x00,0x4f = movi v0.4s, #1
0x20,0x04,0x00,0x4f = movi v0.4s, #1
0x20,0x24,0x00,0x4f = movi v0.4s, #1, lsl #8
0x20,0x44,0x00,0x4f = movi v0.4s, #1, lsl #16
0x20,0x64,0x00,0x4f = movi v0.4s, #1, lsl #24
0x20,0x84,0x00,0x0f = movi v0.4h, #1
0x20,0x84,0x00,0x0f = movi v0.4h, #1
0x20,0xa4,0x00,0x0f = movi v0.4h, #1, lsl #8
0x20,0x84,0x00,0x4f = movi v0.8h, #1
0x20,0x84,0x00,0x4f = movi v0.8h, #1
0x20,0xa4,0x00,0x4f = movi v0.8h, #1, lsl #8
0x20,0xc4,0x00,0x0f = movi v0.2s, #1, msl #8
0x20,0xd4,0x00,0x0f = movi v0.2s, #1, msl #16
0x20,0xc4,0x00,0x4f = movi v0.4s, #1, msl #8
0x20,0xd4,0x00,0x4f = movi v0.4s, #1, msl #16
0x20,0xe4,0x00,0x0f = movi v0.8b, #1
0x20,0xe4,0x00,0x4f = movi v0.16b, #1
0x20,0x04,0x00,0x2f = mvni v0.2s, #1
0x20,0x04,0x00,0x2f = mvni v0.2s, #1
0x20,0x24,0x00,0x2f = mvni v0.2s, #1, lsl #8
0x20,0x44,0x00,0x2f = mvni v0.2s, #1, lsl #16
0x20,0x64,0x00,0x2f = mvni v0.2s, #1, lsl #24
0x20,0x04,0x00,0x6f = mvni v0.4s, #1
0x20,0x04,0x00,0x6f = mvni v0.4s, #1
0x20,0x24,0x00,0x6f = mvni v0.4s, #1, lsl #8
0x20,0x44,0x00,0x6f = mvni v0.4s, #1, lsl #16
0x20,0x64,0x00,0x6f = mvni v0.4s, #1, lsl #24
0x20,0x84,0x00,0x2f = mvni v0.4h, #1
0x20,0x84,0x00,0x2f = mvni v0.4h, #1
0x20,0xa4,0x00,0x2f = mvni v0.4h, #1, lsl #8
0x20,0x84,0x00,0x6f = mvni v0.8h, #1
0x20,0x84,0x00,0x6f = mvni v0.8h, #1
0x20,0xa4,0x00,0x6f = mvni v0.8h, #1, lsl #8
0x20,0xc4,0x00,0x2f = mvni v0.2s, #1, msl #8
0x20,0xd4,0x00,0x2f = mvni v0.2s, #1, msl #16
0x20,0xc4,0x00,0x6f = mvni v0.4s, #1, msl #8
0x20,0xd4,0x00,0x6f = mvni v0.4s, #1, msl #16
0x00,0x18,0xa0,0x5f = fmla s0, s0, v0.s[3]
0x00,0x18,0xc0,0x5f = fmla d0, d0, v0.d[1]
0x00,0x58,0xa0,0x5f = fmls s0, s0, v0.s[3]
0x00,0x58,0xc0,0x5f = fmls d0, d0, v0.d[1]
0x00,0x98,0xa0,0x7f = fmulx s0, s0, v0.s[3]
0x00,0x98,0xc0,0x7f = fmulx d0, d0, v0.d[1]
0x00,0x98,0xa0,0x5f = fmul s0, s0, v0.s[3]
0x00,0x98,0xc0,0x5f = fmul d0, d0, v0.d[1]
0x00,0x38,0x70,0x5f = sqdmlal s0, h0, v0.h[7]
0x00,0x38,0xa0,0x5f = sqdmlal d0, s0, v0.s[3]
0x00,0x78,0x70,0x5f = sqdmlsl s0, h0, v0.h[7]
0x00,0xc8,0x70,0x5f = sqdmulh h0, h0, v0.h[7]
0x00,0xc8,0xa0,0x5f = sqdmulh s0, s0, v0.s[3]
0x00,0xb8,0x70,0x5f = sqdmull s0, h0, v0.h[7]
0x00,0xb8,0xa0,0x5f = sqdmull d0, s0, v0.s[3]
0x00,0xd8,0x70,0x5f = sqrdmulh h0, h0, v0.h[7]
0x00,0xd8,0xa0,0x5f = sqrdmulh s0, s0, v0.s[3]
0x41,0x80,0x23,0x0e = smlal v1.8h, v2.8b, v3.8b
0x41,0x80,0x63,0x0e = smlal v1.4s, v2.4h, v3.4h
0x41,0x80,0xa3,0x0e = smlal v1.2d, v2.2s, v3.2s
0x41,0x80,0x23,0x4e = smlal2 v1.8h, v2.16b, v3.16b
0x41,0x80,0x63,0x4e = smlal2 v1.4s, v2.8h, v3.8h
0x41,0x80,0xa3,0x4e = smlal2 v1.2d, v2.4s, v3.4s
0x0d,0x81,0x20,0x0e = smlal v13.8h, v8.8b, v0.8b
0x0d,0x81,0x60,0x0e = smlal v13.4s, v8.4h, v0.4h
0x0d,0x81,0xa0,0x0e = smlal v13.2d, v8.2s, v0.2s
0x0d,0x81,0x20,0x4e = smlal2 v13.8h, v8.16b, v0.16b
0x0d,0x81,0x60,0x4e = smlal2 v13.4s, v8.8h, v0.8h
0x0d,0x81,0xa0,0x4e = smlal2 v13.2d, v8.4s, v0.4s
0x00,0x10,0x80,0x0f = fmla v0.2s, v0.2s, v0.s[0]
0x00,0x10,0xa0,0x4f = fmla v0.4s, v0.4s, v0.s[1]
0x00,0x18,0xc0,0x4f = fmla v0.2d, v0.2d, v0.d[1]
0x00,0x50,0x80,0x0f = fmls v0.2s, v0.2s, v0.s[0]
0x00,0x50,0xa0,0x4f = fmls v0.4s, v0.4s, v0.s[1]
0x00,0x58,0xc0,0x4f = fmls v0.2d, v0.2d, v0.d[1]
0x00,0x90,0x80,0x2f = fmulx v0.2s, v0.2s, v0.s[0]
0x00,0x90,0xa0,0x6f = fmulx v0.4s, v0.4s, v0.s[1]
0x00,0x98,0xc0,0x6f = fmulx v0.2d, v0.2d, v0.d[1]
0x00,0x90,0x80,0x0f = fmul v0.2s, v0.2s, v0.s[0]
0x00,0x90,0xa0,0x4f = fmul v0.4s, v0.4s, v0.s[1]
0x00,0x98,0xc0,0x4f = fmul v0.2d, v0.2d, v0.d[1]
0x00,0x00,0x40,0x2f = mla v0.4h, v0.4h, v0.h[0]
0x00,0x00,0x50,0x6f = mla v0.8h, v0.8h, v0.h[1]
0x00,0x08,0x80,0x2f = mla v0.2s, v0.2s, v0.s[2]
0x00,0x08,0xa0,0x6f = mla v0.4s, v0.4s, v0.s[3]
0x00,0x40,0x40,0x2f = mls v0.4h, v0.4h, v0.h[0]
0x00,0x40,0x50,0x6f = mls v0.8h, v0.8h, v0.h[1]
0x00,0x48,0x80,0x2f = mls v0.2s, v0.2s, v0.s[2]
0x00,0x48,0xa0,0x6f = mls v0.4s, v0.4s, v0.s[3]
0x00,0x80,0x40,0x0f = mul v0.4h, v0.4h, v0.h[0]
0x00,0x80,0x50,0x4f = mul v0.8h, v0.8h, v0.h[1]
0x00,0x88,0x80,0x0f = mul v0.2s, v0.2s, v0.s[2]
0x00,0x88,0xa0,0x4f = mul v0.4s, v0.4s, v0.s[3]
0x00,0x20,0x40,0x0f = smlal v0.4s, v0.4h, v0.h[0]
0x00,0x20,0x50,0x4f = smlal2 v0.4s, v0.8h, v0.h[1]
0x00,0x28,0x80,0x0f = smlal v0.2d, v0.2s, v0.s[2]
0x00,0x28,0xa0,0x4f = smlal2 v0.2d, v0.4s, v0.s[3]
0x00,0x60,0x40,0x0f = smlsl v0.4s, v0.4h, v0.h[0]
0x00,0x60,0x50,0x4f = smlsl2 v0.4s, v0.8h, v0.h[1]
0x00,0x68,0x80,0x0f = smlsl v0.2d, v0.2s, v0.s[2]
0x00,0x68,0xa0,0x4f = smlsl2 v0.2d, v0.4s, v0.s[3]
0x00,0xa0,0x40,0x0f = smull v0.4s, v0.4h, v0.h[0]
0x00,0xa0,0x50,0x4f = smull2 v0.4s, v0.8h, v0.h[1]
0x00,0xa8,0x80,0x0f = smull v0.2d, v0.2s, v0.s[2]
0x00,0xa8,0xa0,0x4f = smull2 v0.2d, v0.4s, v0.s[3]
0x00,0x30,0x40,0x0f = sqdmlal v0.4s, v0.4h, v0.h[0]
0x00,0x30,0x50,0x4f = sqdmlal2 v0.4s, v0.8h, v0.h[1]
0x00,0x38,0x80,0x0f = sqdmlal v0.2d, v0.2s, v0.s[2]
0x00,0x38,0xa0,0x4f = sqdmlal2 v0.2d, v0.4s, v0.s[3]
0x00,0x70,0x40,0x0f = sqdmlsl v0.4s, v0.4h, v0.h[0]
0x00,0x70,0x50,0x4f = sqdmlsl2 v0.4s, v0.8h, v0.h[1]
0x00,0x78,0x80,0x0f = sqdmlsl v0.2d, v0.2s, v0.s[2]
0x00,0x78,0xa0,0x4f = sqdmlsl2 v0.2d, v0.4s, v0.s[3]
0x00,0xc0,0x40,0x0f = sqdmulh v0.4h, v0.4h, v0.h[0]
0x00,0xc0,0x50,0x4f = sqdmulh v0.8h, v0.8h, v0.h[1]
0x00,0xc8,0x80,0x0f = sqdmulh v0.2s, v0.2s, v0.s[2]
0x00,0xc8,0xa0,0x4f = sqdmulh v0.4s, v0.4s, v0.s[3]
0x00,0xb0,0x40,0x0f = sqdmull v0.4s, v0.4h, v0.h[0]
0x00,0xb0,0x50,0x4f = sqdmull2 v0.4s, v0.8h, v0.h[1]
0x00,0xb8,0x80,0x0f = sqdmull v0.2d, v0.2s, v0.s[2]
0x00,0xb8,0xa0,0x4f = sqdmull2 v0.2d, v0.4s, v0.s[3]
0x00,0xd0,0x40,0x0f = sqrdmulh v0.4h, v0.4h, v0.h[0]
0x00,0xd0,0x50,0x4f = sqrdmulh v0.8h, v0.8h, v0.h[1]
0x00,0xd8,0x80,0x0f = sqrdmulh v0.2s, v0.2s, v0.s[2]
0x00,0xd8,0xa0,0x4f = sqrdmulh v0.4s, v0.4s, v0.s[3]
0x00,0x20,0x40,0x2f = umlal v0.4s, v0.4h, v0.h[0]
0x00,0x20,0x50,0x6f = umlal2 v0.4s, v0.8h, v0.h[1]
0x00,0x28,0x80,0x2f = umlal v0.2d, v0.2s, v0.s[2]
0x00,0x28,0xa0,0x6f = umlal2 v0.2d, v0.4s, v0.s[3]
0x00,0x60,0x40,0x2f = umlsl v0.4s, v0.4h, v0.h[0]
0x00,0x60,0x50,0x6f = umlsl2 v0.4s, v0.8h, v0.h[1]
0x00,0x68,0x80,0x2f = umlsl v0.2d, v0.2s, v0.s[2]
0x00,0x68,0xa0,0x6f = umlsl2 v0.2d, v0.4s, v0.s[3]
0x00,0xa0,0x40,0x2f = umull v0.4s, v0.4h, v0.h[0]
0x00,0xa0,0x50,0x6f = umull2 v0.4s, v0.8h, v0.h[1]
0x00,0xa8,0x80,0x2f = umull v0.2d, v0.2s, v0.s[2]
0x00,0xa8,0xa0,0x6f = umull2 v0.2d, v0.4s, v0.s[3]
0x00,0xfc,0x3f,0x5f = fcvtzs s0, s0, #1
0x00,0xfc,0x7e,0x5f = fcvtzs d0, d0, #2
0x00,0xfc,0x3f,0x7f = fcvtzu s0, s0, #1
0x00,0xfc,0x7e,0x7f = fcvtzu d0, d0, #2
0x00,0x54,0x41,0x5f = shl d0, d0, #1
0x00,0x54,0x41,0x7f = sli d0, d0, #1
0x00,0x9c,0x0f,0x5f = sqrshrn b0, h0, #1
0x00,0x9c,0x1e,0x5f = sqrshrn h0, s0, #2
0x00,0x9c,0x3d,0x5f = sqrshrn s0, d0, #3
0x00,0x8c,0x0f,0x7f = sqrshrun b0, h0, #1
0x00,0x8c,0x1e,0x7f = sqrshrun h0, s0, #2
0x00,0x8c,0x3d,0x7f = sqrshrun s0, d0, #3
0x00,0x64,0x09,0x7f = sqshlu b0, b0, #1
0x00,0x64,0x12,0x7f = sqshlu h0, h0, #2
0x00,0x64,0x23,0x7f = sqshlu s0, s0, #3
0x00,0x64,0x44,0x7f = sqshlu d0, d0, #4
0x00,0x74,0x09,0x5f = sqshl b0, b0, #1
0x00,0x74,0x12,0x5f = sqshl h0, h0, #2
0x00,0x74,0x23,0x5f = sqshl s0, s0, #3
0x00,0x74,0x44,0x5f = sqshl d0, d0, #4
0x00,0x94,0x0f,0x5f = sqshrn b0, h0, #1
0x00,0x94,0x1e,0x5f = sqshrn h0, s0, #2
0x00,0x94,0x3d,0x5f = sqshrn s0, d0, #3
0x00,0x84,0x0f,0x7f = sqshrun b0, h0, #1
0x00,0x84,0x1e,0x7f = sqshrun h0, s0, #2
0x00,0x84,0x3d,0x7f = sqshrun s0, d0, #3
0x00,0x44,0x7f,0x7f = sri d0, d0, #1
0x00,0x24,0x7f,0x5f = srshr d0, d0, #1
0x00,0x34,0x7f,0x5f = srsra d0, d0, #1
0x00,0x04,0x7f,0x5f = sshr d0, d0, #1
0x00,0xe4,0x3f,0x7f = ucvtf s0, s0, #1
0x00,0xe4,0x7e,0x7f = ucvtf d0, d0, #2
0x00,0xe4,0x3f,0x5f = scvtf s0, s0, #1
0x00,0xe4,0x7e,0x5f = scvtf d0, d0, #2
0x00,0x9c,0x0f,0x7f = uqrshrn b0, h0, #1
0x00,0x9c,0x1e,0x7f = uqrshrn h0, s0, #2
0x00,0x9c,0x3d,0x7f = uqrshrn s0, d0, #3
0x00,0x74,0x09,0x7f = uqshl b0, b0, #1
0x00,0x74,0x12,0x7f = uqshl h0, h0, #2
0x00,0x74,0x23,0x7f = uqshl s0, s0, #3
0x00,0x74,0x44,0x7f = uqshl d0, d0, #4
0x00,0x94,0x0f,0x7f = uqshrn b0, h0, #1
0x00,0x94,0x1e,0x7f = uqshrn h0, s0, #2
0x00,0x94,0x3d,0x7f = uqshrn s0, d0, #3
0x00,0x24,0x7f,0x7f = urshr d0, d0, #1
0x00,0x34,0x7f,0x7f = ursra d0, d0, #1
0x00,0x04,0x7f,0x7f = ushr d0, d0, #1
0x00,0x14,0x7f,0x7f = usra d0, d0, #1
0x00,0xfc,0x3f,0x0f = fcvtzs v0.2s, v0.2s, #1
0x00,0xfc,0x3e,0x4f = fcvtzs v0.4s, v0.4s, #2
0x00,0xfc,0x7d,0x4f = fcvtzs v0.2d, v0.2d, #3
0x00,0xfc,0x3f,0x2f = fcvtzu v0.2s, v0.2s, #1
0x00,0xfc,0x3e,0x6f = fcvtzu v0.4s, v0.4s, #2
0x00,0xfc,0x7d,0x6f = fcvtzu v0.2d, v0.2d, #3
0x00,0x8c,0x0f,0x0f = rshrn v0.8b, v0.8h, #1
0x00,0x8c,0x0e,0x4f = rshrn2 v0.16b, v0.8h, #2
0x00,0x8c,0x1d,0x0f = rshrn v0.4h, v0.4s, #3
0x00,0x8c,0x1c,0x4f = rshrn2 v0.8h, v0.4s, #4
0x00,0x8c,0x3b,0x0f = rshrn v0.2s, v0.2d, #5
0x00,0x8c,0x3a,0x4f = rshrn2 v0.4s, v0.2d, #6
0x00,0xe4,0x3f,0x0f = scvtf v0.2s, v0.2s, #1
0x00,0xe4,0x3e,0x4f = scvtf v0.4s, v0.4s, #2
0x00,0xe4,0x7d,0x4f = scvtf v0.2d, v0.2d, #3
0x00,0x54,0x09,0x0f = shl v0.8b, v0.8b, #1
0x00,0x54,0x0a,0x4f = shl v0.16b, v0.16b, #2
0x00,0x54,0x13,0x0f = shl v0.4h, v0.4h, #3
0x00,0x54,0x14,0x4f = shl v0.8h, v0.8h, #4
0x00,0x54,0x25,0x0f = shl v0.2s, v0.2s, #5
0x00,0x54,0x26,0x4f = shl v0.4s, v0.4s, #6
0x00,0x54,0x47,0x4f = shl v0.2d, v0.2d, #7
0x00,0x84,0x0f,0x0f = shrn v0.8b, v0.8h, #1
0x00,0x84,0x0e,0x4f = shrn2 v0.16b, v0.8h, #2
0x00,0x84,0x1d,0x0f = shrn v0.4h, v0.4s, #3
0x00,0x84,0x1c,0x4f = shrn2 v0.8h, v0.4s, #4
0x00,0x84,0x3b,0x0f = shrn v0.2s, v0.2d, #5
0x00,0x84,0x3a,0x4f = shrn2 v0.4s, v0.2d, #6
0x00,0x54,0x09,0x2f = sli v0.8b, v0.8b, #1
0x00,0x54,0x0a,0x6f = sli v0.16b, v0.16b, #2
0x00,0x54,0x13,0x2f = sli v0.4h, v0.4h, #3
0x00,0x54,0x14,0x6f = sli v0.8h, v0.8h, #4
0x00,0x54,0x25,0x2f = sli v0.2s, v0.2s, #5
0x00,0x54,0x26,0x6f = sli v0.4s, v0.4s, #6
0x00,0x54,0x47,0x6f = sli v0.2d, v0.2d, #7
0x00,0x9c,0x0f,0x0f = sqrshrn v0.8b, v0.8h, #1
0x00,0x9c,0x0e,0x4f = sqrshrn2 v0.16b, v0.8h, #2
0x00,0x9c,0x1d,0x0f = sqrshrn v0.4h, v0.4s, #3
0x00,0x9c,0x1c,0x4f = sqrshrn2 v0.8h, v0.4s, #4
0x00,0x9c,0x3b,0x0f = sqrshrn v0.2s, v0.2d, #5
0x00,0x9c,0x3a,0x4f = sqrshrn2 v0.4s, v0.2d, #6
0x00,0x8c,0x0f,0x2f = sqrshrun v0.8b, v0.8h, #1
0x00,0x8c,0x0e,0x6f = sqrshrun2 v0.16b, v0.8h, #2
0x00,0x8c,0x1d,0x2f = sqrshrun v0.4h, v0.4s, #3
0x00,0x8c,0x1c,0x6f = sqrshrun2 v0.8h, v0.4s, #4
0x00,0x8c,0x3b,0x2f = sqrshrun v0.2s, v0.2d, #5
0x00,0x8c,0x3a,0x6f = sqrshrun2 v0.4s, v0.2d, #6
0x00,0x64,0x09,0x2f = sqshlu v0.8b, v0.8b, #1
0x00,0x64,0x0a,0x6f = sqshlu v0.16b, v0.16b, #2
0x00,0x64,0x13,0x2f = sqshlu v0.4h, v0.4h, #3
0x00,0x64,0x14,0x6f = sqshlu v0.8h, v0.8h, #4
0x00,0x64,0x25,0x2f = sqshlu v0.2s, v0.2s, #5
0x00,0x64,0x26,0x6f = sqshlu v0.4s, v0.4s, #6
0x00,0x64,0x47,0x6f = sqshlu v0.2d, v0.2d, #7
0x00,0x74,0x09,0x0f = sqshl v0.8b, v0.8b, #1
0x00,0x74,0x0a,0x4f = sqshl v0.16b, v0.16b, #2
0x00,0x74,0x13,0x0f = sqshl v0.4h, v0.4h, #3
0x00,0x74,0x14,0x4f = sqshl v0.8h, v0.8h, #4
0x00,0x74,0x25,0x0f = sqshl v0.2s, v0.2s, #5
0x00,0x74,0x26,0x4f = sqshl v0.4s, v0.4s, #6
0x00,0x74,0x47,0x4f = sqshl v0.2d, v0.2d, #7
0x00,0x94,0x0f,0x0f = sqshrn v0.8b, v0.8h, #1
0x00,0x94,0x0e,0x4f = sqshrn2 v0.16b, v0.8h, #2
0x00,0x94,0x1d,0x0f = sqshrn v0.4h, v0.4s, #3
0x00,0x94,0x1c,0x4f = sqshrn2 v0.8h, v0.4s, #4
0x00,0x94,0x3b,0x0f = sqshrn v0.2s, v0.2d, #5
0x00,0x94,0x3a,0x4f = sqshrn2 v0.4s, v0.2d, #6
0x00,0x84,0x0f,0x2f = sqshrun v0.8b, v0.8h, #1
0x00,0x84,0x0e,0x6f = sqshrun2 v0.16b, v0.8h, #2
0x00,0x84,0x1d,0x2f = sqshrun v0.4h, v0.4s, #3
0x00,0x84,0x1c,0x6f = sqshrun2 v0.8h, v0.4s, #4
0x00,0x84,0x3b,0x2f = sqshrun v0.2s, v0.2d, #5
0x00,0x84,0x3a,0x6f = sqshrun2 v0.4s, v0.2d, #6
0x00,0x44,0x0f,0x2f = sri v0.8b, v0.8b, #1
0x00,0x44,0x0e,0x6f = sri v0.16b, v0.16b, #2
0x00,0x44,0x1d,0x2f = sri v0.4h, v0.4h, #3
0x00,0x44,0x1c,0x6f = sri v0.8h, v0.8h, #4
0x00,0x44,0x3b,0x2f = sri v0.2s, v0.2s, #5
0x00,0x44,0x3a,0x6f = sri v0.4s, v0.4s, #6
0x00,0x44,0x79,0x6f = sri v0.2d, v0.2d, #7
0x00,0x24,0x0f,0x0f = srshr v0.8b, v0.8b, #1
0x00,0x24,0x0e,0x4f = srshr v0.16b, v0.16b, #2
0x00,0x24,0x1d,0x0f = srshr v0.4h, v0.4h, #3
0x00,0x24,0x1c,0x4f = srshr v0.8h, v0.8h, #4
0x00,0x24,0x3b,0x0f = srshr v0.2s, v0.2s, #5
0x00,0x24,0x3a,0x4f = srshr v0.4s, v0.4s, #6
0x00,0x24,0x79,0x4f = srshr v0.2d, v0.2d, #7
0x00,0x34,0x0f,0x0f = srsra v0.8b, v0.8b, #1
0x00,0x34,0x0e,0x4f = srsra v0.16b, v0.16b, #2
0x00,0x34,0x1d,0x0f = srsra v0.4h, v0.4h, #3
0x00,0x34,0x1c,0x4f = srsra v0.8h, v0.8h, #4
0x00,0x34,0x3b,0x0f = srsra v0.2s, v0.2s, #5
0x00,0x34,0x3a,0x4f = srsra v0.4s, v0.4s, #6
0x00,0x34,0x79,0x4f = srsra v0.2d, v0.2d, #7
0x00,0xa4,0x09,0x0f = sshll v0.8h, v0.8b, #1
0x00,0xa4,0x0a,0x4f = sshll2 v0.8h, v0.16b, #2
0x00,0xa4,0x13,0x0f = sshll v0.4s, v0.4h, #3
0x00,0xa4,0x14,0x4f = sshll2 v0.4s, v0.8h, #4
0x00,0xa4,0x25,0x0f = sshll v0.2d, v0.2s, #5
0x00,0xa4,0x26,0x4f = sshll2 v0.2d, v0.4s, #6
0x00,0x04,0x0f,0x0f = sshr v0.8b, v0.8b, #1
0x00,0x04,0x0e,0x4f = sshr v0.16b, v0.16b, #2
0x00,0x04,0x1d,0x0f = sshr v0.4h, v0.4h, #3
0x00,0x04,0x1c,0x4f = sshr v0.8h, v0.8h, #4
0x00,0x04,0x3b,0x0f = sshr v0.2s, v0.2s, #5
0x00,0x04,0x3a,0x4f = sshr v0.4s, v0.4s, #6
0x00,0x04,0x79,0x4f = sshr v0.2d, v0.2d, #7
0x00,0x04,0x0f,0x0f = sshr v0.8b, v0.8b, #1
0x00,0x14,0x0e,0x4f = ssra v0.16b, v0.16b, #2
0x00,0x14,0x1d,0x0f = ssra v0.4h, v0.4h, #3
0x00,0x14,0x1c,0x4f = ssra v0.8h, v0.8h, #4
0x00,0x14,0x3b,0x0f = ssra v0.2s, v0.2s, #5
0x00,0x14,0x3a,0x4f = ssra v0.4s, v0.4s, #6
0x00,0x14,0x79,0x4f = ssra v0.2d, v0.2d, #7
0x00,0x14,0x40,0x5f = ssra d0, d0, #64
0x00,0xe4,0x3f,0x2f = ucvtf v0.2s, v0.2s, #1
0x00,0xe4,0x3e,0x6f = ucvtf v0.4s, v0.4s, #2
0x00,0xe4,0x7d,0x6f = ucvtf v0.2d, v0.2d, #3
0x00,0x9c,0x0f,0x2f = uqrshrn v0.8b, v0.8h, #1
0x00,0x9c,0x0e,0x6f = uqrshrn2 v0.16b, v0.8h, #2
0x00,0x9c,0x1d,0x2f = uqrshrn v0.4h, v0.4s, #3
0x00,0x9c,0x1c,0x6f = uqrshrn2 v0.8h, v0.4s, #4
0x00,0x9c,0x3b,0x2f = uqrshrn v0.2s, v0.2d, #5
0x00,0x9c,0x3a,0x6f = uqrshrn2 v0.4s, v0.2d, #6
0x00,0x74,0x09,0x2f = uqshl v0.8b, v0.8b, #1
0x00,0x74,0x0a,0x6f = uqshl v0.16b, v0.16b, #2
0x00,0x74,0x13,0x2f = uqshl v0.4h, v0.4h, #3
0x00,0x74,0x14,0x6f = uqshl v0.8h, v0.8h, #4
0x00,0x74,0x25,0x2f = uqshl v0.2s, v0.2s, #5
0x00,0x74,0x26,0x6f = uqshl v0.4s, v0.4s, #6
0x00,0x74,0x47,0x6f = uqshl v0.2d, v0.2d, #7
0x00,0x94,0x0f,0x2f = uqshrn v0.8b, v0.8h, #1
0x00,0x94,0x0e,0x6f = uqshrn2 v0.16b, v0.8h, #2
0x00,0x94,0x1d,0x2f = uqshrn v0.4h, v0.4s, #3
0x00,0x94,0x1c,0x6f = uqshrn2 v0.8h, v0.4s, #4
0x00,0x94,0x3b,0x2f = uqshrn v0.2s, v0.2d, #5
0x00,0x94,0x3a,0x6f = uqshrn2 v0.4s, v0.2d, #6
0x00,0x24,0x0f,0x2f = urshr v0.8b, v0.8b, #1
0x00,0x24,0x0e,0x6f = urshr v0.16b, v0.16b, #2
0x00,0x24,0x1d,0x2f = urshr v0.4h, v0.4h, #3
0x00,0x24,0x1c,0x6f = urshr v0.8h, v0.8h, #4
0x00,0x24,0x3b,0x2f = urshr v0.2s, v0.2s, #5
0x00,0x24,0x3a,0x6f = urshr v0.4s, v0.4s, #6
0x00,0x24,0x79,0x6f = urshr v0.2d, v0.2d, #7
0x00,0x34,0x0f,0x2f = ursra v0.8b, v0.8b, #1
0x00,0x34,0x0e,0x6f = ursra v0.16b, v0.16b, #2
0x00,0x34,0x1d,0x2f = ursra v0.4h, v0.4h, #3
0x00,0x34,0x1c,0x6f = ursra v0.8h, v0.8h, #4
0x00,0x34,0x3b,0x2f = ursra v0.2s, v0.2s, #5
0x00,0x34,0x3a,0x6f = ursra v0.4s, v0.4s, #6
0x00,0x34,0x79,0x6f = ursra v0.2d, v0.2d, #7
0x00,0xa4,0x09,0x2f = ushll v0.8h, v0.8b, #1
0x00,0xa4,0x0a,0x6f = ushll2 v0.8h, v0.16b, #2
0x00,0xa4,0x13,0x2f = ushll v0.4s, v0.4h, #3
0x00,0xa4,0x14,0x6f = ushll2 v0.4s, v0.8h, #4
0x00,0xa4,0x25,0x2f = ushll v0.2d, v0.2s, #5
0x00,0xa4,0x26,0x6f = ushll2 v0.2d, v0.4s, #6
0x00,0x04,0x0f,0x2f = ushr v0.8b, v0.8b, #1
0x00,0x04,0x0e,0x6f = ushr v0.16b, v0.16b, #2
0x00,0x04,0x1d,0x2f = ushr v0.4h, v0.4h, #3
0x00,0x04,0x1c,0x6f = ushr v0.8h, v0.8h, #4
0x00,0x04,0x3b,0x2f = ushr v0.2s, v0.2s, #5
0x00,0x04,0x3a,0x6f = ushr v0.4s, v0.4s, #6
0x00,0x04,0x79,0x6f = ushr v0.2d, v0.2d, #7
0x00,0x14,0x0f,0x2f = usra v0.8b, v0.8b, #1
0x00,0x14,0x0e,0x6f = usra v0.16b, v0.16b, #2
0x00,0x14,0x1d,0x2f = usra v0.4h, v0.4h, #3
0x00,0x14,0x1c,0x6f = usra v0.8h, v0.8h, #4
0x00,0x14,0x3b,0x2f = usra v0.2s, v0.2s, #5
0x00,0x14,0x3a,0x6f = usra v0.4s, v0.4s, #6
0x00,0x14,0x79,0x6f = usra v0.2d, v0.2d, #7
0x69,0x8d,0x0f,0x0f = rshrn v9.8b, v11.8h, #1
0x28,0x8d,0x0e,0x4f = rshrn2 v8.16b, v9.8h, #2
0x07,0x8d,0x1d,0x0f = rshrn v7.4h, v8.4s, #3
0xe6,0x8c,0x1c,0x4f = rshrn2 v6.8h, v7.4s, #4
0xc5,0x8c,0x3b,0x0f = rshrn v5.2s, v6.2d, #5
0xa4,0x8c,0x3a,0x4f = rshrn2 v4.4s, v5.2d, #6
0x69,0x85,0x0f,0x0f = shrn v9.8b, v11.8h, #1
0x28,0x85,0x0e,0x4f = shrn2 v8.16b, v9.8h, #2
0x07,0x85,0x1d,0x0f = shrn v7.4h, v8.4s, #3
0xe6,0x84,0x1c,0x4f = shrn2 v6.8h, v7.4s, #4
0xc5,0x84,0x3b,0x0f = shrn v5.2s, v6.2d, #5
0xa4,0x84,0x3a,0x4f = shrn2 v4.4s, v5.2d, #6
0x69,0x9d,0x0f,0x0f = sqrshrn v9.8b, v11.8h, #1
0x28,0x9d,0x0e,0x4f = sqrshrn2 v8.16b, v9.8h, #2
0x07,0x9d,0x1d,0x0f = sqrshrn v7.4h, v8.4s, #3
0xe6,0x9c,0x1c,0x4f = sqrshrn2 v6.8h, v7.4s, #4
0xc5,0x9c,0x3b,0x0f = sqrshrn v5.2s, v6.2d, #5
0xa4,0x9c,0x3a,0x4f = sqrshrn2 v4.4s, v5.2d, #6
0x69,0x95,0x0f,0x0f = sqshrn v9.8b, v11.8h, #1
0x28,0x95,0x0e,0x4f = sqshrn2 v8.16b, v9.8h, #2
0x07,0x95,0x1d,0x0f = sqshrn v7.4h, v8.4s, #3
0xe6,0x94,0x1c,0x4f = sqshrn2 v6.8h, v7.4s, #4
0xc5,0x94,0x3b,0x0f = sqshrn v5.2s, v6.2d, #5
0xa4,0x94,0x3a,0x4f = sqshrn2 v4.4s, v5.2d, #6
0x69,0x8d,0x0f,0x2f = sqrshrun v9.8b, v11.8h, #1
0x28,0x8d,0x0e,0x6f = sqrshrun2 v8.16b, v9.8h, #2
0x07,0x8d,0x1d,0x2f = sqrshrun v7.4h, v8.4s, #3
0xe6,0x8c,0x1c,0x6f = sqrshrun2 v6.8h, v7.4s, #4
0xc5,0x8c,0x3b,0x2f = sqrshrun v5.2s, v6.2d, #5
0xa4,0x8c,0x3a,0x6f = sqrshrun2 v4.4s, v5.2d, #6
0x69,0x85,0x0f,0x2f = sqshrun v9.8b, v11.8h, #1
0x28,0x85,0x0e,0x6f = sqshrun2 v8.16b, v9.8h, #2
0x07,0x85,0x1d,0x2f = sqshrun v7.4h, v8.4s, #3
0xe6,0x84,0x1c,0x6f = sqshrun2 v6.8h, v7.4s, #4
0xc5,0x84,0x3b,0x2f = sqshrun v5.2s, v6.2d, #5
0xa4,0x84,0x3a,0x6f = sqshrun2 v4.4s, v5.2d, #6
0x69,0x9d,0x0f,0x2f = uqrshrn v9.8b, v11.8h, #1
0x28,0x9d,0x0e,0x6f = uqrshrn2 v8.16b, v9.8h, #2
0x07,0x9d,0x1d,0x2f = uqrshrn v7.4h, v8.4s, #3
0xe6,0x9c,0x1c,0x6f = uqrshrn2 v6.8h, v7.4s, #4
0xc5,0x9c,0x3b,0x2f = uqrshrn v5.2s, v6.2d, #5
0xa4,0x9c,0x3a,0x6f = uqrshrn2 v4.4s, v5.2d, #6
0x69,0x95,0x0f,0x2f = uqshrn v9.8b, v11.8h, #1
0x28,0x95,0x0e,0x6f = uqshrn2 v8.16b, v9.8h, #2
0x07,0x95,0x1d,0x2f = uqshrn v7.4h, v8.4s, #3
0xe6,0x94,0x1c,0x6f = uqshrn2 v6.8h, v7.4s, #4
0xc5,0x94,0x3b,0x2f = uqshrn v5.2s, v6.2d, #5
0xa4,0x94,0x3a,0x6f = uqshrn2 v4.4s, v5.2d, #6
0x6a,0xa4,0x0e,0x4f = sshll2 v10.8h, v3.16b, #6
0x8b,0xa4,0x15,0x4f = sshll2 v11.4s, v4.8h, #5
0xac,0xa4,0x24,0x4f = sshll2 v12.2d, v5.4s, #4
0xcd,0xa4,0x0b,0x0f = sshll v13.8h, v6.8b, #3
0xee,0xa4,0x12,0x0f = sshll v14.4s, v7.4h, #2
0x0f,0xa5,0x27,0x0f = sshll v15.2d, v8.2s, #7
0x6a,0xa4,0x0e,0x6f = ushll2 v10.8h, v3.16b, #6
0x8b,0xa4,0x15,0x6f = ushll2 v11.4s, v4.8h, #5
0xac,0xa4,0x24,0x6f = ushll2 v12.2d, v5.4s, #4
0xcd,0xa4,0x0b,0x2f = ushll v13.8h, v6.8b, #3
0xee,0xa4,0x12,0x2f = ushll v14.4s, v7.4h, #2
0x0f,0xa5,0x27,0x2f = ushll v15.2d, v8.2s, #7
0x00,0xe0,0x20,0x0e = pmull v0.8h, v0.8b, v0.8b
0x00,0xe0,0x20,0x4e = pmull2 v0.8h, v0.16b, v0.16b
0x62,0xe0,0xe4,0x0e = pmull v2.1q, v3.1d, v4.1d
0x62,0xe0,0xe4,0x4e = pmull2 v2.1q, v3.2d, v4.2d
0x62,0xe0,0xe4,0x0e = pmull v2.1q, v3.1d, v4.1d
0x62,0xe0,0xe4,0x4e = pmull2 v2.1q, v3.2d, v4.2d
0x41,0xd8,0x70,0x7e = faddp d1, v2.2d
0x83,0xd8,0x30,0x7e = faddp s3, v4.2s
0x82,0x60,0x01,0x4e = tbl v2.16b, { v4.16b, v5.16b, v6.16b, v7.16b }, v1.16b
0x80,0x60,0x01,0x0e = tbl v0.8b, { v4.16b, v5.16b, v6.16b, v7.16b }, v1.8b
0xa2,0x00,0x01,0x4e = tbl v2.16b, { v5.16b }, v1.16b
0xa0,0x00,0x01,0x0e = tbl v0.8b, { v5.16b }, v1.8b
0xa2,0x40,0x01,0x4e = tbl v2.16b, { v5.16b, v6.16b, v7.16b }, v1.16b
0xa0,0x40,0x01,0x0e = tbl v0.8b, { v5.16b, v6.16b, v7.16b }, v1.8b
0xc2,0x20,0x01,0x4e = tbl v2.16b, { v6.16b, v7.16b }, v1.16b
0xc0,0x20,0x01,0x0e = tbl v0.8b, { v6.16b, v7.16b }, v1.8b
0x82,0x60,0x01,0x4e = tbl v2.16b, { v4.16b, v5.16b, v6.16b, v7.16b }, v1.16b
0x80,0x60,0x01,0x0e = tbl v0.8b, { v4.16b, v5.16b, v6.16b, v7.16b }, v1.8b
0xa2,0x00,0x01,0x4e = tbl v2.16b, { v5.16b }, v1.16b
0xa0,0x00,0x01,0x0e = tbl v0.8b, { v5.16b }, v1.8b
0xa2,0x40,0x01,0x4e = tbl v2.16b, { v5.16b, v6.16b, v7.16b }, v1.16b
0xa0,0x40,0x01,0x0e = tbl v0.8b, { v5.16b, v6.16b, v7.16b }, v1.8b
0xc2,0x20,0x01,0x4e = tbl v2.16b, { v6.16b, v7.16b }, v1.16b
0xc0,0x20,0x01,0x0e = tbl v0.8b, { v6.16b, v7.16b }, v1.8b
0x00,0xd0,0x60,0x5e = sqdmull s0, h0, h0
0x00,0xd0,0xa0,0x5e = sqdmull d0, s0, s0
0x00,0xd8,0xa1,0x7e = frsqrte s0, s0
0x00,0xd8,0xe1,0x7e = frsqrte d0, d0
0x00,0x1c,0xa0,0x4e = mov v0.16b, v0.16b
0x00,0x1c,0xa0,0x0e = mov v0.8b, v0.8b
0x2e,0x6b,0x20,0x2e = uadalp v14.4h, v25.8b
0x0f,0x6b,0x20,0x6e = uadalp v15.8h, v24.16b
0xf0,0x6a,0x60,0x2e = uadalp v16.2s, v23.4h
0xd1,0x6a,0x60,0x6e = uadalp v17.4s, v22.8h
0xb2,0x6a,0xa0,0x2e = uadalp v18.1d, v21.2s
0x93,0x6a,0xa0,0x6e = uadalp v19.2d, v20.4s
0x61,0x69,0x20,0x0e = sadalp v1.4h, v11.8b
0x82,0x69,0x20,0x4e = sadalp v2.8h, v12.16b
0xa3,0x69,0x60,0x0e = sadalp v3.2s, v13.4h
0xc4,0x69,0x60,0x4e = sadalp v4.4s, v14.8h
0xe5,0x69,0xa0,0x0e = sadalp v5.1d, v15.2s
0x06,0x6a,0xa0,0x4e = sadalp v6.2d, v16.4s
0x81,0x58,0x20,0x2e = mvn v1.8b, v4.8b
0x33,0x5a,0x20,0x6e = mvn v19.16b, v17.16b
0xca,0x58,0x20,0x2e = mvn v10.8b, v6.8b
0xeb,0x58,0x20,0x6e = mvn v11.16b, v7.16b
0x8a,0xd1,0x6c,0x0e = sqdmull v10.4s, v12.4h, v12.4h
0xaa,0xd1,0x6d,0x4e = sqdmull2 v10.4s, v13.8h, v13.8h
0xaa,0xd1,0xad,0x0e = sqdmull v10.2d, v13.2s, v13.2s
0xaa,0xd1,0xad,0x4e = sqdmull2 v10.2d, v13.4s, v13.4s
0xce,0x29,0x21,0x0e = xtn v14.8b, v14.8h
0xce,0x29,0x21,0x4e = xtn2 v14.16b, v14.8h
0xce,0x29,0x61,0x0e = xtn v14.4h, v14.4s
0xce,0x29,0x61,0x4e = xtn2 v14.8h, v14.4s
0xce,0x29,0xa1,0x0e = xtn v14.2s, v14.2d
0xce,0x29,0xa1,0x4e = xtn2 v14.4s, v14.2d
0xa9,0x01,0x2e,0x2e = uaddl v9.8h, v13.8b, v14.8b
0xa9,0x01,0x2e,0x6e = uaddl2 v9.8h, v13.16b, v14.16b
0xa9,0x01,0x6e,0x2e = uaddl v9.4s, v13.4h, v14.4h
0xa9,0x01,0x6e,0x6e = uaddl2 v9.4s, v13.8h, v14.8h
0xa9,0x01,0xae,0x2e = uaddl v9.2d, v13.2s, v14.2s
0xa9,0x01,0xae,0x6e = uaddl2 v9.2d, v13.4s, v14.4s
0x49,0x1d,0xaa,0x6e = bit v9.16b, v10.16b, v10.16b
0x49,0x1d,0xaa,0x2e = bit v9.8b, v10.8b, v10.8b
0x08,0xe1,0x28,0x0e = pmull v8.8h, v8.8b, v8.8b
0x08,0xe1,0x28,0x4e = pmull2 v8.8h, v8.16b, v8.16b
0x08,0xe1,0xe8,0x0e = pmull v8.1q, v8.1d, v8.1d
0x08,0xe1,0xe8,0x4e = pmull2 v8.1q, v8.2d, v8.2d
0xa9,0x21,0x2e,0x2e = usubl v9.8h, v13.8b, v14.8b
0xa9,0x21,0x2e,0x6e = usubl2 v9.8h, v13.16b, v14.16b
0xa9,0x21,0x6e,0x2e = usubl v9.4s, v13.4h, v14.4h
0xa9,0x21,0x6e,0x6e = usubl2 v9.4s, v13.8h, v14.8h
0xa9,0x21,0xae,0x2e = usubl v9.2d, v13.2s, v14.2s
0xa9,0x21,0xae,0x6e = usubl2 v9.2d, v13.4s, v14.4s
0xa9,0x71,0x2e,0x2e = uabdl v9.8h, v13.8b, v14.8b
0xa9,0x71,0x2e,0x6e = uabdl2 v9.8h, v13.16b, v14.16b
0xa9,0x71,0x6e,0x2e = uabdl v9.4s, v13.4h, v14.4h
0xa9,0x71,0x6e,0x6e = uabdl2 v9.4s, v13.8h, v14.8h
0xa9,0x71,0xae,0x2e = uabdl v9.2d, v13.2s, v14.2s
0xa9,0x71,0xae,0x6e = uabdl2 v9.2d, v13.4s, v14.4s
0xa9,0xc1,0x2e,0x2e = umull v9.8h, v13.8b, v14.8b
0xa9,0xc1,0x2e,0x6e = umull2 v9.8h, v13.16b, v14.16b
0xa9,0xc1,0x6e,0x2e = umull v9.4s, v13.4h, v14.4h
0xa9,0xc1,0x6e,0x6e = umull2 v9.4s, v13.8h, v14.8h
0xa9,0xc1,0xae,0x2e = umull v9.2d, v13.2s, v14.2s
0xa9,0xc1,0xae,0x6e = umull2 v9.2d, v13.4s, v14.4s
0xa9,0xc1,0x2e,0x0e = smull v9.8h, v13.8b, v14.8b
0xa9,0xc1,0x2e,0x4e = smull2 v9.8h, v13.16b, v14.16b
0xa9,0xc1,0x6e,0x0e = smull v9.4s, v13.4h, v14.4h
0xa9,0xc1,0x6e,0x4e = smull2 v9.4s, v13.8h, v14.8h
0xa9,0xc1,0xae,0x0e = smull v9.2d, v13.2s, v14.2s
0xa9,0xc1,0xae,0x4e = smull2 v9.2d, v13.4s, v14.4s

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suite/MC/AArch64/arm64-aliases.s.cs Normal file
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# CS_ARCH_AARCH64, 0, None
0x3f,0x04,0x00,0x72 = tst w1, #0x3
0x3f,0x04,0x40,0xf2 = tst x1, #0x3
0x3f,0x00,0x02,0x6a = tst w1, w2
0x3f,0x00,0x02,0xea = tst x1, x2
0x3f,0x08,0x02,0x6a = tst w1, w2, lsl #2
0x3f,0x0c,0x02,0xea = tst x1, x2, lsl #3
0x7f,0x7c,0x07,0x6a = tst w3, w7, lsl #31
0x5f,0x00,0x94,0xea = tst x2, x20, asr #0
0x3f,0x0c,0x00,0x31 = cmn w1, #3
0x5f,0x00,0x50,0xb1 = cmn x2, #1024, lsl #12
0x9f,0x00,0x05,0x2b = cmn w4, w5
0xdf,0x00,0x07,0xab = cmn x6, x7
0x1f,0x0d,0x89,0x2b = cmn w8, w9, asr #3
0x5f,0x10,0x43,0xab = cmn x2, x3, lsr #4
0x5f,0x04,0x23,0xab = cmn x2, w3, uxtb #1
0x9f,0x64,0x25,0xab = cmn x4, x5, uxtx #1
0x3f,0x00,0x50,0x71 = cmp w1, #1024, lsl #12
0x5f,0x00,0x10,0xf1 = cmp x2, #1024
0x9f,0x00,0x05,0x6b = cmp w4, w5
0xdf,0x00,0x07,0xeb = cmp x6, x7
0x1f,0x0d,0x89,0x6b = cmp w8, w9, asr #3
0x5f,0x10,0x43,0xeb = cmp x2, x3, lsr #4
0x5f,0x28,0x23,0xeb = cmp x2, w3, uxth #2
0x9f,0x60,0x25,0xeb = cmp x4, x5, uxtx
0xff,0x03,0x01,0x6b = cmp wzr, w1
0x1f,0x41,0x28,0xeb = cmp x8, w8, uxtw
0x3f,0x41,0x28,0x6b = cmp w9, w8, uxtw
0xff,0x43,0x29,0x6b = cmp wsp, w9
0xe4,0x03,0x29,0x2a = mvn w4, w9
0xe2,0x03,0x23,0xaa = mvn x2, x3
0xe4,0x03,0x29,0x2a = mvn w4, w9
0xe4,0x07,0x29,0x2a = mvn w4, w9, lsl #1
0xe2,0x07,0x23,0xaa = mvn x2, x3, lsl #1
0xe4,0x07,0x29,0x2a = mvn w4, w9, lsl #1
0x1f,0x71,0x08,0xd5 = ic ialluis
0x1f,0x75,0x08,0xd5 = ic iallu
0x20,0x75,0x0b,0xd5 = ic ivau, x0
0x20,0x74,0x0b,0xd5 = dc zva, x0
0x20,0x76,0x08,0xd5 = dc ivac, x0
0x40,0x76,0x08,0xd5 = dc isw, x0
0x20,0x7a,0x0b,0xd5 = dc cvac, x0
0x40,0x7a,0x08,0xd5 = dc csw, x0
0x20,0x7b,0x0b,0xd5 = dc cvau, x0
0x20,0x7e,0x0b,0xd5 = dc civac, x0
0x40,0x7e,0x08,0xd5 = dc cisw, x0
0x00,0x78,0x08,0xd5 = at s1e1r, x0
0x00,0x78,0x0c,0xd5 = at s1e2r, x0
0x00,0x78,0x0e,0xd5 = at s1e3r, x0
0x20,0x78,0x08,0xd5 = at s1e1w, x0
0x20,0x78,0x0c,0xd5 = at s1e2w, x0
0x20,0x78,0x0e,0xd5 = at s1e3w, x0
0x40,0x78,0x08,0xd5 = at s1e0r, x0
0x60,0x78,0x08,0xd5 = at s1e0w, x0
0x80,0x78,0x0c,0xd5 = at s12e1r, x0
0xa0,0x78,0x0c,0xd5 = at s12e1w, x0
0xc0,0x78,0x0c,0xd5 = at s12e0r, x0
0xe0,0x78,0x0c,0xd5 = at s12e0w, x0
0x1f,0x83,0x08,0xd5 = tlbi vmalle1is
0x1f,0x83,0x0c,0xd5 = tlbi alle2is
0x1f,0x83,0x0e,0xd5 = tlbi alle3is
0x20,0x83,0x08,0xd5 = tlbi vae1is, x0
0x20,0x83,0x0c,0xd5 = tlbi vae2is, x0
0x20,0x83,0x0e,0xd5 = tlbi vae3is, x0
0x40,0x83,0x08,0xd5 = tlbi aside1is, x0
0x60,0x83,0x08,0xd5 = tlbi vaae1is, x0
0x9f,0x83,0x0c,0xd5 = tlbi alle1is
0xa0,0x83,0x08,0xd5 = tlbi vale1is, x0
0xe0,0x83,0x08,0xd5 = tlbi vaale1is, x0
0x1f,0x87,0x08,0xd5 = tlbi vmalle1
0x1f,0x87,0x0c,0xd5 = tlbi alle2
0xa0,0x83,0x0c,0xd5 = tlbi vale2is, x0
0xa0,0x83,0x0e,0xd5 = tlbi vale3is, x0
0x1f,0x87,0x0e,0xd5 = tlbi alle3
0x20,0x87,0x08,0xd5 = tlbi vae1, x0
0x20,0x87,0x0c,0xd5 = tlbi vae2, x0
0x20,0x87,0x0e,0xd5 = tlbi vae3, x0
0x40,0x87,0x08,0xd5 = tlbi aside1, x0
0x60,0x87,0x08,0xd5 = tlbi vaae1, x0
0xa0,0x87,0x08,0xd5 = tlbi vale1, x0
0xa0,0x87,0x0c,0xd5 = tlbi vale2, x0
0xa0,0x87,0x0e,0xd5 = tlbi vale3, x0
0xe0,0x87,0x08,0xd5 = tlbi vaale1, x0
0x20,0x84,0x0c,0xd5 = tlbi ipas2e1, x0
0xa0,0x84,0x0c,0xd5 = tlbi ipas2le1, x0
0x20,0x80,0x0c,0xd5 = tlbi ipas2e1is, x0
0xa0,0x80,0x0c,0xd5 = tlbi ipas2le1is, x0
0xdf,0x87,0x0c,0xd5 = tlbi vmalls12e1
0xdf,0x83,0x0c,0xd5 = tlbi vmalls12e1is
0x04,0xe4,0x00,0x4f = movi v4.16b, #0
0x24,0xe4,0x00,0x4f = movi v4.16b, #1
0x44,0xe4,0x00,0x0f = movi v4.8b, #2
0x64,0xe4,0x00,0x0f = movi v4.8b, #3
0x21,0xe4,0x00,0x6f = movi v1.2d, #0x000000000000ff
0x22,0xe4,0x00,0x6f = movi v2.2d, #0x000000000000ff

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suite/MC/AArch64/arm64-arithmetic-encoding.s.cs Normal file
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# CS_ARCH_AARCH64, 0, None
0x41,0x00,0x03,0x1a = adc w1, w2, w3
0x41,0x00,0x03,0x9a = adc x1, x2, x3
0x85,0x00,0x03,0x3a = adcs w5, w4, w3
0x85,0x00,0x03,0xba = adcs x5, x4, x3
0x41,0x00,0x03,0x5a = sbc w1, w2, w3
0x41,0x00,0x03,0xda = sbc x1, x2, x3
0x41,0x00,0x03,0x7a = sbcs w1, w2, w3
0x41,0x00,0x03,0xfa = sbcs x1, x2, x3
0x83,0x00,0x10,0x11 = add w3, w4, #1024
0x83,0x00,0x10,0x11 = add w3, w4, #1024
0x83,0x00,0x10,0x91 = add x3, x4, #1024
0x83,0x00,0x10,0x91 = add x3, x4, #1024
0x83,0x00,0x50,0x11 = add w3, w4, #1024, lsl #12
0x83,0x00,0x50,0x11 = add w3, w4, #1024, lsl #12
0x83,0x00,0x40,0x11 = add w3, w4, #0, lsl #12
0x83,0x00,0x50,0x91 = add x3, x4, #1024, lsl #12
0x83,0x00,0x50,0x91 = add x3, x4, #1024, lsl #12
0x83,0x00,0x40,0x91 = add x3, x4, #0, lsl #12
0xff,0x83,0x00,0x91 = add sp, sp, #32
0x83,0x00,0x10,0x31 = adds w3, w4, #1024
0x83,0x00,0x10,0x31 = adds w3, w4, #1024
0x83,0x00,0x50,0x31 = adds w3, w4, #1024, lsl #12
0x83,0x00,0x10,0xb1 = adds x3, x4, #1024
0x83,0x00,0x10,0xb1 = adds x3, x4, #1024
0x83,0x00,0x50,0xb1 = adds x3, x4, #1024, lsl #12
0x83,0x00,0x10,0x51 = sub w3, w4, #1024
0x83,0x00,0x10,0x51 = sub w3, w4, #1024
0x83,0x00,0x50,0x51 = sub w3, w4, #1024, lsl #12
0x83,0x00,0x10,0xd1 = sub x3, x4, #1024
0x83,0x00,0x10,0xd1 = sub x3, x4, #1024
0x83,0x00,0x50,0xd1 = sub x3, x4, #1024, lsl #12
0xff,0x83,0x00,0xd1 = sub sp, sp, #32
0x83,0x00,0x10,0x71 = subs w3, w4, #1024
0x83,0x00,0x10,0x71 = subs w3, w4, #1024
0x83,0x00,0x50,0x71 = subs w3, w4, #1024, lsl #12
0x83,0x00,0x10,0xf1 = subs x3, x4, #1024
0x83,0x00,0x10,0xf1 = subs x3, x4, #1024
0x83,0x00,0x50,0xf1 = subs x3, x4, #1024, lsl #12
0xac,0x01,0x0e,0x0b = add w12, w13, w14
0xac,0x01,0x0e,0x8b = add x12, x13, x14
0xac,0x31,0x0e,0x0b = add w12, w13, w14, lsl #12
0xac,0x31,0x0e,0x8b = add x12, x13, x14, lsl #12
0xac,0xa9,0x4e,0x8b = add x12, x13, x14, lsr #42
0xac,0x9d,0x8e,0x8b = add x12, x13, x14, asr #39
0xac,0x01,0x0e,0x4b = sub w12, w13, w14
0xac,0x01,0x0e,0xcb = sub x12, x13, x14
0xac,0x31,0x0e,0x4b = sub w12, w13, w14, lsl #12
0xac,0x31,0x0e,0xcb = sub x12, x13, x14, lsl #12
0xac,0xa9,0x4e,0xcb = sub x12, x13, x14, lsr #42
0xac,0x9d,0x8e,0xcb = sub x12, x13, x14, asr #39
0xac,0x01,0x0e,0x2b = adds w12, w13, w14
0xac,0x01,0x0e,0xab = adds x12, x13, x14
0xac,0x31,0x0e,0x2b = adds w12, w13, w14, lsl #12
0xac,0x31,0x0e,0xab = adds x12, x13, x14, lsl #12
0xac,0xa9,0x4e,0xab = adds x12, x13, x14, lsr #42
0xac,0x9d,0x8e,0xab = adds x12, x13, x14, asr #39
0xac,0x01,0x0e,0x6b = subs w12, w13, w14
0xac,0x01,0x0e,0xeb = subs x12, x13, x14
0xac,0x31,0x0e,0x6b = subs w12, w13, w14, lsl #12
0xac,0x31,0x0e,0xeb = subs x12, x13, x14, lsl #12
0xac,0xa9,0x4e,0xeb = subs x12, x13, x14, lsr #42
0xac,0x9d,0x8e,0xeb = subs x12, x13, x14, asr #39
0x42,0x00,0x02,0x8b = add x2, x2, x2
0x41,0x00,0x23,0x0b = add w1, w2, w3, uxtb
0x41,0x20,0x23,0x0b = add w1, w2, w3, uxth
0x41,0x40,0x23,0x0b = add w1, w2, w3, uxtw
0x41,0x60,0x23,0x0b = add w1, w2, w3, uxtx
0x41,0x80,0x23,0x0b = add w1, w2, w3, sxtb
0x41,0xa0,0x23,0x0b = add w1, w2, w3, sxth
0x41,0xc0,0x23,0x0b = add w1, w2, w3, sxtw
0x41,0xe0,0x23,0x0b = add w1, w2, w3, sxtx
0x41,0x00,0x23,0x8b = add x1, x2, w3, uxtb
0x41,0x20,0x23,0x8b = add x1, x2, w3, uxth
0x41,0x40,0x23,0x8b = add x1, x2, w3, uxtw
0x41,0x80,0x23,0x8b = add x1, x2, w3, sxtb
0x41,0xa0,0x23,0x8b = add x1, x2, w3, sxth
0x41,0xc0,0x23,0x8b = add x1, x2, w3, sxtw
0xe1,0x43,0x23,0x0b = add w1, wsp, w3
0xe1,0x43,0x23,0x0b = add w1, wsp, w3
0xe2,0x47,0x23,0x0b = add w2, wsp, w3, lsl #1
0x5f,0x60,0x23,0x8b = add sp, x2, x3
0x5f,0x60,0x23,0x8b = add sp, x2, x3
0x41,0x00,0x23,0x4b = sub w1, w2, w3, uxtb
0x41,0x20,0x23,0x4b = sub w1, w2, w3, uxth
0x41,0x40,0x23,0x4b = sub w1, w2, w3, uxtw
0x41,0x60,0x23,0x4b = sub w1, w2, w3, uxtx
0x41,0x80,0x23,0x4b = sub w1, w2, w3, sxtb
0x41,0xa0,0x23,0x4b = sub w1, w2, w3, sxth
0x41,0xc0,0x23,0x4b = sub w1, w2, w3, sxtw
0x41,0xe0,0x23,0x4b = sub w1, w2, w3, sxtx
0x41,0x00,0x23,0xcb = sub x1, x2, w3, uxtb
0x41,0x20,0x23,0xcb = sub x1, x2, w3, uxth
0x41,0x40,0x23,0xcb = sub x1, x2, w3, uxtw
0x41,0x80,0x23,0xcb = sub x1, x2, w3, sxtb
0x41,0xa0,0x23,0xcb = sub x1, x2, w3, sxth
0x41,0xc0,0x23,0xcb = sub x1, x2, w3, sxtw
0xe1,0x43,0x23,0x4b = sub w1, wsp, w3
0xe1,0x43,0x23,0x4b = sub w1, wsp, w3
0x5f,0x60,0x23,0xcb = sub sp, x2, x3
0x5f,0x60,0x23,0xcb = sub sp, x2, x3
0x7f,0x70,0x27,0xcb = sub sp, x3, x7, lsl #4
0x41,0x00,0x23,0x2b = adds w1, w2, w3, uxtb
0x41,0x20,0x23,0x2b = adds w1, w2, w3, uxth
0x41,0x40,0x23,0x2b = adds w1, w2, w3, uxtw
0x41,0x60,0x23,0x2b = adds w1, w2, w3, uxtx
0x41,0x80,0x23,0x2b = adds w1, w2, w3, sxtb
0x41,0xa0,0x23,0x2b = adds w1, w2, w3, sxth
0x41,0xc0,0x23,0x2b = adds w1, w2, w3, sxtw
0x41,0xe0,0x23,0x2b = adds w1, w2, w3, sxtx
0x41,0x00,0x23,0xab = adds x1, x2, w3, uxtb
0x41,0x20,0x23,0xab = adds x1, x2, w3, uxth
0x41,0x40,0x23,0xab = adds x1, x2, w3, uxtw
0x41,0x60,0x23,0xab = adds x1, x2, x3, uxtx
0x41,0x80,0x23,0xab = adds x1, x2, w3, sxtb
0x41,0xa0,0x23,0xab = adds x1, x2, w3, sxth
0x41,0xc0,0x23,0xab = adds x1, x2, w3, sxtw
0x41,0xe0,0x23,0xab = adds x1, x2, x3, sxtx
0xe1,0x43,0x23,0x2b = adds w1, wsp, w3
0xe1,0x43,0x23,0x2b = adds w1, wsp, w3
0xff,0x53,0x23,0x2b = cmn wsp, w3, lsl #4
0x41,0x00,0x23,0x6b = subs w1, w2, w3, uxtb
0x41,0x20,0x23,0x6b = subs w1, w2, w3, uxth
0x41,0x40,0x23,0x6b = subs w1, w2, w3, uxtw
0x41,0x60,0x23,0x6b = subs w1, w2, w3, uxtx
0x41,0x80,0x23,0x6b = subs w1, w2, w3, sxtb
0x41,0xa0,0x23,0x6b = subs w1, w2, w3, sxth
0x41,0xc0,0x23,0x6b = subs w1, w2, w3, sxtw
0x41,0xe0,0x23,0x6b = subs w1, w2, w3, sxtx
0x41,0x00,0x23,0xeb = subs x1, x2, w3, uxtb
0x41,0x20,0x23,0xeb = subs x1, x2, w3, uxth
0x41,0x40,0x23,0xeb = subs x1, x2, w3, uxtw
0x41,0x60,0x23,0xeb = subs x1, x2, x3, uxtx
0x41,0x80,0x23,0xeb = subs x1, x2, w3, sxtb
0x41,0xa0,0x23,0xeb = subs x1, x2, w3, sxth
0x41,0xc0,0x23,0xeb = subs x1, x2, w3, sxtw
0x41,0xe0,0x23,0xeb = subs x1, x2, x3, sxtx
0xe1,0x43,0x23,0x6b = subs w1, wsp, w3
0xe1,0x43,0x23,0x6b = subs w1, wsp, w3
0xff,0x43,0x29,0x6b = cmp wsp, w9
0xe3,0x6b,0x29,0xeb = subs x3, sp, x9, lsl #2
0xff,0x43,0x28,0x6b = cmp wsp, w8
0xff,0x43,0x28,0x6b = cmp wsp, w8
0xff,0x43,0x28,0xeb = cmp sp, w8, uxtw
0xff,0x43,0x28,0xeb = cmp sp, w8, uxtw
0x3f,0x41,0x28,0x4b = sub wsp, w9, w8
0xe1,0x43,0x28,0x4b = sub w1, wsp, w8
0xff,0x43,0x28,0x4b = sub wsp, wsp, w8
0x3f,0x41,0x28,0xcb = sub sp, x9, w8, uxtw
0xe1,0x43,0x28,0xcb = sub x1, sp, w8, uxtw
0xff,0x43,0x28,0xcb = sub sp, sp, w8, uxtw
0xe1,0x43,0x28,0x6b = subs w1, wsp, w8
0xe1,0x43,0x28,0xeb = subs x1, sp, w8, uxtw
0x41,0x0c,0xc3,0x1a = sdiv w1, w2, w3
0x41,0x0c,0xc3,0x9a = sdiv x1, x2, x3
0x41,0x08,0xc3,0x1a = udiv w1, w2, w3
0x41,0x08,0xc3,0x9a = udiv x1, x2, x3
0x41,0x28,0xc3,0x1a = asr w1, w2, w3
0x41,0x28,0xc3,0x9a = asr x1, x2, x3
0x41,0x28,0xc3,0x1a = asr w1, w2, w3
0x41,0x28,0xc3,0x9a = asr x1, x2, x3
0x41,0x20,0xc3,0x1a = lsl w1, w2, w3
0x41,0x20,0xc3,0x9a = lsl x1, x2, x3
0x41,0x20,0xc3,0x1a = lsl w1, w2, w3
0x41,0x20,0xc3,0x9a = lsl x1, x2, x3
0x41,0x24,0xc3,0x1a = lsr w1, w2, w3
0x41,0x24,0xc3,0x9a = lsr x1, x2, x3
0x41,0x24,0xc3,0x1a = lsr w1, w2, w3
0x41,0x24,0xc3,0x9a = lsr x1, x2, x3
0x41,0x2c,0xc3,0x1a = ror w1, w2, w3
0x41,0x2c,0xc3,0x9a = ror x1, x2, x3
0x41,0x2c,0xc3,0x1a = ror w1, w2, w3
0x41,0x2c,0xc3,0x9a = ror x1, x2, x3
0x41,0x14,0xc0,0x5a = cls w1, w2
0x41,0x14,0xc0,0xda = cls x1, x2
0x41,0x10,0xc0,0x5a = clz w1, w2
0x41,0x10,0xc0,0xda = clz x1, x2
0x41,0x00,0xc0,0x5a = rbit w1, w2
0x41,0x00,0xc0,0xda = rbit x1, x2
0x41,0x08,0xc0,0x5a = rev w1, w2
0x41,0x0c,0xc0,0xda = rev x1, x2
0x41,0x04,0xc0,0x5a = rev16 w1, w2
0x41,0x04,0xc0,0xda = rev16 x1, x2
0x41,0x08,0xc0,0xda = rev32 x1, x2
0x41,0x10,0x03,0x1b = madd w1, w2, w3, w4
0x41,0x10,0x03,0x9b = madd x1, x2, x3, x4
0x41,0x90,0x03,0x1b = msub w1, w2, w3, w4
0x41,0x90,0x03,0x9b = msub x1, x2, x3, x4
0x41,0x10,0x23,0x9b = smaddl x1, w2, w3, x4
0x41,0x90,0x23,0x9b = smsubl x1, w2, w3, x4
0x41,0x10,0xa3,0x9b = umaddl x1, w2, w3, x4
0x41,0x90,0xa3,0x9b = umsubl x1, w2, w3, x4
0x41,0x7c,0x43,0x9b = smulh x1, x2, x3
0x41,0x7c,0xc3,0x9b = umulh x1, x2, x3
0x20,0x00,0x80,0x52 = mov w0, #1
0x20,0x00,0x80,0xd2 = mov x0, #1
0x20,0x00,0xa0,0x52 = mov w0, #65536
0x20,0x00,0xa0,0xd2 = mov x0, #65536
0x40,0x00,0x80,0x12 = mov w0, #-3
0x40,0x00,0x80,0x92 = mov x0, #-3
0x40,0x00,0xa0,0x12 = mov w0, #-131073
0x40,0x00,0xa0,0x92 = mov x0, #-131073
0x20,0x00,0x80,0x72 = movk w0, #1
0x20,0x00,0x80,0xf2 = movk x0, #1
0x20,0x00,0xa0,0x72 = movk w0, #1, lsl #16
0x20,0x00,0xa0,0xf2 = movk x0, #1, lsl #16
0x23,0x08,0x42,0x3a = ccmn w1, #2, #3, eq
0x23,0x08,0x42,0xba = ccmn x1, #2, #3, eq
0x23,0x08,0x42,0x7a = ccmp w1, #2, #3, eq
0x23,0x08,0x42,0xfa = ccmp x1, #2, #3, eq
0x23,0x00,0x42,0x3a = ccmn w1, w2, #3, eq
0x23,0x00,0x42,0xba = ccmn x1, x2, #3, eq
0x23,0x00,0x42,0x7a = ccmp w1, w2, #3, eq
0x23,0x00,0x42,0xfa = ccmp x1, x2, #3, eq
0x41,0x00,0x83,0x1a = csel w1, w2, w3, eq
0x41,0x00,0x83,0x9a = csel x1, x2, x3, eq
0x41,0x04,0x83,0x1a = csinc w1, w2, w3, eq
0x41,0x04,0x83,0x9a = csinc x1, x2, x3, eq
0x41,0x00,0x83,0x5a = csinv w1, w2, w3, eq
0x41,0x00,0x83,0xda = csinv x1, x2, x3, eq
0x41,0x04,0x83,0x5a = csneg w1, w2, w3, eq
0x41,0x04,0x83,0xda = csneg x1, x2, x3, eq
0xf0,0x00,0x9b,0x1a = csel w16, w7, w27, eq
0xcf,0x10,0x9a,0x1a = csel w15, w6, w26, ne
0xae,0x20,0x99,0x1a = csel w14, w5, w25, hs
0x8d,0x20,0x98,0x1a = csel w13, w4, w24, hs
0x6c,0x30,0x97,0x1a = csel w12, w3, w23, lo
0x4b,0x30,0x96,0x1a = csel w11, w2, w22, lo
0x2a,0x40,0x95,0x1a = csel w10, w1, w21, mi
0x29,0x51,0x81,0x9a = csel x9, x9, x1, pl
0x08,0x61,0x82,0x9a = csel x8, x8, x2, vs
0xe7,0x70,0x83,0x9a = csel x7, x7, x3, vc
0xe6,0x80,0x84,0x9a = csel x6, x7, x4, hi
0xc5,0x90,0x85,0x9a = csel x5, x6, x5, ls
0xa4,0xa0,0x86,0x9a = csel x4, x5, x6, ge
0x83,0xb0,0x87,0x9a = csel x3, x4, x7, lt
0x62,0xc0,0x88,0x9a = csel x2, x3, x8, gt
0x41,0xd0,0x89,0x9a = csel x1, x2, x9, le
0x2a,0xe0,0x94,0x9a = csel x10, x1, x20, al
0x44,0x48,0x21,0x7e = uqxtn b4, h2
0x62,0x48,0x61,0x7e = uqxtn h2, s3
0x49,0x48,0xa1,0x7e = uqxtn s9, d2

9
suite/MC/AArch64/arm64-basic-a64-instructions.s.cs Normal file
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# CS_ARCH_AARCH64, 0, None
0xe5,0x40,0xd4,0x1a = crc32b w5, w7, w20
0xfc,0x47,0xde,0x1a = crc32h w28, wzr, w30
0x20,0x48,0xc2,0x1a = crc32w w0, w1, w2
0x27,0x4d,0xd4,0x9a = crc32x w7, w9, x20
0xa9,0x50,0xc4,0x1a = crc32cb w9, w5, w4
0x2d,0x56,0xd9,0x1a = crc32ch w13, w17, w25
0x7f,0x58,0xc5,0x1a = crc32cw wzr, w3, w5
0x12,0x5e,0xdf,0x9a = crc32cx w18, w16, xzr

13
suite/MC/AArch64/arm64-bitfield-encoding.s.cs Normal file
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# CS_ARCH_AARCH64, 0, None
0x41,0x3c,0x01,0x33 = bfxil w1, w2, #1, #15
0x41,0x3c,0x41,0xb3 = bfxil x1, x2, #1, #15
0x41,0x3c,0x01,0x13 = sbfx w1, w2, #1, #15
0x41,0x3c,0x41,0x93 = sbfx x1, x2, #1, #15
0x41,0x3c,0x01,0x53 = ubfx w1, w2, #1, #15
0x41,0x3c,0x41,0xd3 = ubfx x1, x2, #1, #15
0x1f,0x00,0x01,0x13 = sbfiz wzr, w0, #31, #1
0x1f,0x00,0x61,0x93 = sbfiz xzr, x0, #31, #1
0x1f,0x00,0x01,0x53 = lsl wzr, w0, #31
0x1f,0x00,0x61,0xd3 = ubfiz xzr, x0, #31, #1
0x41,0x3c,0x83,0x13 = extr w1, w2, w3, #15
0x62,0x04,0xc4,0x93 = extr x2, x3, x4, #1

25
suite/MC/AArch64/arm64-branch-encoding.s.cs Normal file
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# CS_ARCH_AARCH64, 0, None
0xc0,0x03,0x5f,0xd6 = ret
0x20,0x00,0x5f,0xd6 = ret x1
0xe0,0x03,0xbf,0xd6 = drps
0xe0,0x03,0x9f,0xd6 = eret
0xa0,0x00,0x1f,0xd6 = br x5
0x20,0x01,0x3f,0xd6 = blr x9
0xe3,0xff,0x7f,0x54 = b.lo #1048572
0xff,0xff,0xff,0x15 = b #134217724
0x00,0x00,0x00,0x16 = b #-134217728
0xf4,0xff,0x7f,0x34 = cbz w20, #1048572
0x02,0x00,0x80,0xb5 = cbnz x2, #-1048576
0xe3,0xff,0x2b,0x36 = tbz w3, #5, #32764
0x03,0x00,0x44,0x37 = tbnz w3, #8, #-32768
0x20,0x00,0x20,0xd4 = brk #0x1
0x41,0x00,0xa0,0xd4 = dcps1 #0x2
0x62,0x00,0xa0,0xd4 = dcps2 #0x3
0x83,0x00,0xa0,0xd4 = dcps3 #0x4
0xa0,0x00,0x40,0xd4 = hlt #0x5
0xc2,0x00,0x00,0xd4 = hvc #0x6
0xe3,0x00,0x00,0xd4 = smc #0x7
0x01,0x01,0x00,0xd4 = svc #0x8
0x01,0x00,0xa0,0xd4 = dcps1
0x02,0x00,0xa0,0xd4 = dcps2
0x03,0x00,0xa0,0xd4 = dcps3

29
suite/MC/AArch64/arm64-crypto.s.cs Normal file
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# CS_ARCH_AARCH64, 0, None
0x20,0x48,0x28,0x4e = aese v0.16b, v1.16b
0x20,0x58,0x28,0x4e = aesd v0.16b, v1.16b
0x20,0x68,0x28,0x4e = aesmc v0.16b, v1.16b
0x20,0x78,0x28,0x4e = aesimc v0.16b, v1.16b
0x20,0x00,0x02,0x5e = sha1c q0, s1, v2.4s
0x20,0x10,0x02,0x5e = sha1p q0, s1, v2.4s
0x20,0x20,0x02,0x5e = sha1m q0, s1, v2.4s
0x20,0x30,0x02,0x5e = sha1su0 v0.4s, v1.4s, v2.4s
0x20,0x40,0x02,0x5e = sha256h q0, q1, v2.4s
0x20,0x50,0x02,0x5e = sha256h2 q0, q1, v2.4s
0x20,0x60,0x02,0x5e = sha256su1 v0.4s, v1.4s, v2.4s
0x20,0x08,0x28,0x5e = sha1h s0, s1
0x20,0x18,0x28,0x5e = sha1su1 v0.4s, v1.4s
0x20,0x28,0x28,0x5e = sha256su0 v0.4s, v1.4s
0x62,0x48,0x28,0x4e = aese v2.16b, v3.16b
0xe5,0x58,0x28,0x4e = aesd v5.16b, v7.16b
0xab,0x69,0x28,0x4e = aesmc v11.16b, v13.16b
0x71,0x7a,0x28,0x4e = aesimc v17.16b, v19.16b
0xb7,0x03,0x03,0x5e = sha1c q23, s29, v3.4s
0xee,0x11,0x09,0x5e = sha1p q14, s15, v9.4s
0xc2,0x20,0x05,0x5e = sha1m q2, s6, v5.4s
0xa3,0x30,0x09,0x5e = sha1su0 v3.4s, v5.4s, v9.4s
0xe2,0x40,0x12,0x5e = sha256h q2, q7, v18.4s
0x5c,0x52,0x1c,0x5e = sha256h2 q28, q18, v28.4s
0xa4,0x60,0x09,0x5e = sha256su1 v4.4s, v5.4s, v9.4s
0x1e,0x08,0x28,0x5e = sha1h s30, s0
0xaa,0x1a,0x28,0x5e = sha1su1 v10.4s, v21.4s
0xe2,0x2b,0x28,0x5e = sha256su0 v2.4s, v31.4s

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suite/MC/AArch64/arm64-fp-encoding.s.cs Normal file
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# CS_ARCH_AARCH64, 0, None
0x41,0xc0,0xe0,0x1e = fabs h1, h2
0x41,0xc0,0x20,0x1e = fabs s1, s2
0x41,0xc0,0x60,0x1e = fabs d1, d2
0x41,0x28,0xe3,0x1e = fadd h1, h2, h3
0x41,0x28,0x23,0x1e = fadd s1, s2, s3
0x41,0x28,0x63,0x1e = fadd d1, d2, d3
0x41,0x18,0xe3,0x1e = fdiv h1, h2, h3
0x41,0x18,0x23,0x1e = fdiv s1, s2, s3
0x41,0x18,0x63,0x1e = fdiv d1, d2, d3
0x41,0x10,0xc3,0x1f = fmadd h1, h2, h3, h4
0x41,0x10,0x03,0x1f = fmadd s1, s2, s3, s4
0x41,0x10,0x43,0x1f = fmadd d1, d2, d3, d4
0x41,0x48,0xe3,0x1e = fmax h1, h2, h3
0x41,0x48,0x23,0x1e = fmax s1, s2, s3
0x41,0x48,0x63,0x1e = fmax d1, d2, d3
0x41,0x68,0xe3,0x1e = fmaxnm h1, h2, h3
0x41,0x68,0x23,0x1e = fmaxnm s1, s2, s3
0x41,0x68,0x63,0x1e = fmaxnm d1, d2, d3
0x41,0x58,0xe3,0x1e = fmin h1, h2, h3
0x41,0x58,0x23,0x1e = fmin s1, s2, s3
0x41,0x58,0x63,0x1e = fmin d1, d2, d3
0x41,0x78,0xe3,0x1e = fminnm h1, h2, h3
0x41,0x78,0x23,0x1e = fminnm s1, s2, s3
0x41,0x78,0x63,0x1e = fminnm d1, d2, d3
0x41,0x90,0xc3,0x1f = fmsub h1, h2, h3, h4
0x41,0x90,0x03,0x1f = fmsub s1, s2, s3, s4
0x41,0x90,0x43,0x1f = fmsub d1, d2, d3, d4
0x41,0x08,0xe3,0x1e = fmul h1, h2, h3
0x41,0x08,0x23,0x1e = fmul s1, s2, s3
0x41,0x08,0x63,0x1e = fmul d1, d2, d3
0x41,0x40,0xe1,0x1e = fneg h1, h2
0x41,0x40,0x21,0x1e = fneg s1, s2
0x41,0x40,0x61,0x1e = fneg d1, d2
0x41,0x10,0xe3,0x1f = fnmadd h1, h2, h3, h4
0x41,0x10,0x23,0x1f = fnmadd s1, s2, s3, s4
0x41,0x10,0x63,0x1f = fnmadd d1, d2, d3, d4
0x41,0x90,0xe3,0x1f = fnmsub h1, h2, h3, h4
0x41,0x90,0x23,0x1f = fnmsub s1, s2, s3, s4
0x41,0x90,0x63,0x1f = fnmsub d1, d2, d3, d4
0x41,0x88,0xe3,0x1e = fnmul h1, h2, h3
0x41,0x88,0x23,0x1e = fnmul s1, s2, s3
0x41,0x88,0x63,0x1e = fnmul d1, d2, d3
0x41,0xc0,0xe1,0x1e = fsqrt h1, h2
0x41,0xc0,0x21,0x1e = fsqrt s1, s2
0x41,0xc0,0x61,0x1e = fsqrt d1, d2
0x41,0x38,0xe3,0x1e = fsub h1, h2, h3
0x41,0x38,0x23,0x1e = fsub s1, s2, s3
0x41,0x38,0x63,0x1e = fsub d1, d2, d3
0x20,0x04,0xe2,0x1e = fccmp h1, h2, #0, eq
0x20,0x04,0x22,0x1e = fccmp s1, s2, #0, eq
0x20,0x04,0x62,0x1e = fccmp d1, d2, #0, eq
0x30,0x04,0xe2,0x1e = fccmpe h1, h2, #0, eq
0x30,0x04,0x22,0x1e = fccmpe s1, s2, #0, eq
0x30,0x04,0x62,0x1e = fccmpe d1, d2, #0, eq
0x20,0x20,0xe2,0x1e = fcmp h1, h2
0x20,0x20,0x22,0x1e = fcmp s1, s2
0x20,0x20,0x62,0x1e = fcmp d1, d2
0x28,0x20,0xe0,0x1e = fcmp h1, #0.0
0x28,0x20,0x20,0x1e = fcmp s1, #0.0
0x28,0x20,0x60,0x1e = fcmp d1, #0.0
0x30,0x20,0xe2,0x1e = fcmpe h1, h2
0x30,0x20,0x22,0x1e = fcmpe s1, s2
0x30,0x20,0x62,0x1e = fcmpe d1, d2
0x38,0x20,0xe0,0x1e = fcmpe h1, #0.0
0x38,0x20,0x20,0x1e = fcmpe s1, #0.0
0x38,0x20,0x60,0x1e = fcmpe d1, #0.0
0x41,0x0c,0xe3,0x1e = fcsel h1, h2, h3, eq
0x41,0x0c,0x23,0x1e = fcsel s1, s2, s3, eq
0x41,0x0c,0x63,0x1e = fcsel d1, d2, d3, eq
0x41,0xc0,0x63,0x1e = fcvt h1, d2
0x41,0x40,0x62,0x1e = fcvt s1, d2
0x41,0xc0,0xe2,0x1e = fcvt d1, h2
0x41,0x40,0xe2,0x1e = fcvt s1, h2
0x41,0xc0,0x22,0x1e = fcvt d1, s2
0x41,0xc0,0x23,0x1e = fcvt h1, s2
0x41,0x00,0x64,0x1e = fcvtas w1, d2
0x41,0x00,0x64,0x9e = fcvtas x1, d2
0x41,0x00,0x24,0x1e = fcvtas w1, s2
0x41,0x00,0x24,0x9e = fcvtas x1, s2
0x41,0x00,0xe4,0x1e = fcvtas w1, h2
0x41,0x00,0xe4,0x9e = fcvtas x1, h2
0x41,0x00,0xe5,0x1e = fcvtau w1, h2
0x41,0x00,0x25,0x1e = fcvtau w1, s2
0x41,0x00,0x65,0x1e = fcvtau w1, d2
0x41,0x00,0xe5,0x9e = fcvtau x1, h2
0x41,0x00,0x25,0x9e = fcvtau x1, s2
0x41,0x00,0x65,0x9e = fcvtau x1, d2
0x41,0x00,0xf0,0x1e = fcvtms w1, h2
0x41,0x00,0x30,0x1e = fcvtms w1, s2
0x41,0x00,0x70,0x1e = fcvtms w1, d2
0x41,0x00,0xf0,0x9e = fcvtms x1, h2
0x41,0x00,0x30,0x9e = fcvtms x1, s2
0x41,0x00,0x70,0x9e = fcvtms x1, d2
0x41,0x00,0xf1,0x1e = fcvtmu w1, h2
0x41,0x00,0x31,0x1e = fcvtmu w1, s2
0x41,0x00,0x71,0x1e = fcvtmu w1, d2
0x41,0x00,0xf1,0x9e = fcvtmu x1, h2
0x41,0x00,0x31,0x9e = fcvtmu x1, s2
0x41,0x00,0x71,0x9e = fcvtmu x1, d2
0x41,0x00,0xe0,0x1e = fcvtns w1, h2
0x41,0x00,0x20,0x1e = fcvtns w1, s2
0x41,0x00,0x60,0x1e = fcvtns w1, d2
0x41,0x00,0xe0,0x9e = fcvtns x1, h2
0x41,0x00,0x20,0x9e = fcvtns x1, s2
0x41,0x00,0x60,0x9e = fcvtns x1, d2
0x41,0x00,0xe1,0x1e = fcvtnu w1, h2
0x41,0x00,0x21,0x1e = fcvtnu w1, s2
0x41,0x00,0x61,0x1e = fcvtnu w1, d2
0x41,0x00,0xe1,0x9e = fcvtnu x1, h2
0x41,0x00,0x21,0x9e = fcvtnu x1, s2
0x41,0x00,0x61,0x9e = fcvtnu x1, d2
0x41,0x00,0xe8,0x1e = fcvtps w1, h2
0x41,0x00,0x28,0x1e = fcvtps w1, s2
0x41,0x00,0x68,0x1e = fcvtps w1, d2
0x41,0x00,0xe8,0x9e = fcvtps x1, h2
0x41,0x00,0x28,0x9e = fcvtps x1, s2
0x41,0x00,0x68,0x9e = fcvtps x1, d2
0x41,0x00,0xe9,0x1e = fcvtpu w1, h2
0x41,0x00,0x29,0x1e = fcvtpu w1, s2
0x41,0x00,0x69,0x1e = fcvtpu w1, d2
0x41,0x00,0xe9,0x9e = fcvtpu x1, h2
0x41,0x00,0x29,0x9e = fcvtpu x1, s2
0x41,0x00,0x69,0x9e = fcvtpu x1, d2
0x41,0x00,0xf8,0x1e = fcvtzs w1, h2
0x41,0xfc,0xd8,0x1e = fcvtzs w1, h2, #1
0x41,0x00,0x38,0x1e = fcvtzs w1, s2
0x41,0xfc,0x18,0x1e = fcvtzs w1, s2, #1
0x41,0x00,0x78,0x1e = fcvtzs w1, d2
0x41,0xfc,0x58,0x1e = fcvtzs w1, d2, #1
0x41,0x00,0xf8,0x9e = fcvtzs x1, h2
0x41,0xfc,0xd8,0x9e = fcvtzs x1, h2, #1
0x41,0x00,0x38,0x9e = fcvtzs x1, s2
0x41,0xfc,0x18,0x9e = fcvtzs x1, s2, #1
0x41,0x00,0x78,0x9e = fcvtzs x1, d2
0x41,0xfc,0x58,0x9e = fcvtzs x1, d2, #1
0x41,0x00,0xf9,0x1e = fcvtzu w1, h2
0x41,0xfc,0xd9,0x1e = fcvtzu w1, h2, #1
0x41,0x00,0x39,0x1e = fcvtzu w1, s2
0x41,0xfc,0x19,0x1e = fcvtzu w1, s2, #1
0x41,0x00,0x79,0x1e = fcvtzu w1, d2
0x41,0xfc,0x59,0x1e = fcvtzu w1, d2, #1
0x41,0x00,0xf9,0x9e = fcvtzu x1, h2
0x41,0xfc,0xd9,0x9e = fcvtzu x1, h2, #1
0x41,0x00,0x39,0x9e = fcvtzu x1, s2
0x41,0xfc,0x19,0x9e = fcvtzu x1, s2, #1
0x41,0x00,0x79,0x9e = fcvtzu x1, d2
0x41,0xfc,0x59,0x9e = fcvtzu x1, d2, #1
0x41,0x00,0xe2,0x1e = scvtf h1, w2
0x41,0xfc,0xc2,0x1e = scvtf h1, w2, #1
0x41,0x00,0x22,0x1e = scvtf s1, w2
0x41,0xfc,0x02,0x1e = scvtf s1, w2, #1
0x41,0x00,0x62,0x1e = scvtf d1, w2
0x41,0xfc,0x42,0x1e = scvtf d1, w2, #1
0x41,0x00,0xe2,0x9e = scvtf h1, x2
0x41,0xfc,0xc2,0x9e = scvtf h1, x2, #1
0x41,0x00,0x22,0x9e = scvtf s1, x2
0x41,0xfc,0x02,0x9e = scvtf s1, x2, #1
0x41,0x00,0x62,0x9e = scvtf d1, x2
0x41,0xfc,0x42,0x9e = scvtf d1, x2, #1
0x41,0x00,0xe3,0x1e = ucvtf h1, w2
0x41,0xfc,0xc3,0x1e = ucvtf h1, w2, #1
0x41,0x00,0x23,0x1e = ucvtf s1, w2
0x41,0xfc,0x03,0x1e = ucvtf s1, w2, #1
0x41,0x00,0x63,0x1e = ucvtf d1, w2
0x41,0xfc,0x43,0x1e = ucvtf d1, w2, #1
0x41,0x00,0xe3,0x9e = ucvtf h1, x2
0x41,0xfc,0xc3,0x9e = ucvtf h1, x2, #1
0x41,0x00,0x23,0x9e = ucvtf s1, x2
0x41,0xfc,0x03,0x9e = ucvtf s1, x2, #1
0x41,0x00,0x63,0x9e = ucvtf d1, x2
0x41,0xfc,0x43,0x9e = ucvtf d1, x2, #1
0x41,0x00,0xe7,0x1e = fmov h1, w2
0x41,0x00,0xe6,0x1e = fmov w1, h2
0x41,0x00,0xe7,0x9e = fmov h1, x2
0x41,0x00,0xe6,0x9e = fmov x1, h2
0x41,0x00,0x27,0x1e = fmov s1, w2
0x41,0x00,0x26,0x1e = fmov w1, s2
0x41,0x00,0x67,0x9e = fmov d1, x2
0x41,0x00,0x66,0x9e = fmov x1, d2
0x01,0x10,0xe8,0x1e = fmov h1, #0.12500000
0x01,0x10,0xe8,0x1e = fmov h1, #0.12500000
0x01,0x10,0x28,0x1e = fmov s1, #0.12500000
0x01,0x10,0x28,0x1e = fmov s1, #0.12500000
0x01,0x10,0x68,0x1e = fmov d1, #0.12500000
0x01,0x10,0x68,0x1e = fmov d1, #0.12500000
0x01,0xf0,0x7b,0x1e = fmov d1, #-0.48437500
0x01,0xf0,0x6b,0x1e = fmov d1, #0.48437500
0x03,0x10,0x61,0x1e = fmov d3, #3.00000000
0xe2,0x03,0xe7,0x1e = fmov h2, wzr
0xe2,0x03,0x27,0x1e = fmov s2, wzr
0xe2,0x03,0x67,0x9e = fmov d2, xzr
0x41,0x40,0xe0,0x1e = fmov h1, h2
0x41,0x40,0x20,0x1e = fmov s1, s2
0x41,0x40,0x60,0x1e = fmov d1, d2
0xa2,0x00,0xae,0x9e = fmov x2, v5.d[1]
0xe9,0x00,0xae,0x9e = fmov x9, v7.d[1]
0x21,0x00,0xaf,0x9e = fmov v1.d[1], x1
0xc8,0x00,0xaf,0x9e = fmov v8.d[1], x6
0x41,0x40,0xe6,0x1e = frinta h1, h2
0x41,0x40,0x26,0x1e = frinta s1, s2
0x41,0x40,0x66,0x1e = frinta d1, d2
0x41,0xc0,0xe7,0x1e = frinti h1, h2
0x41,0xc0,0x27,0x1e = frinti s1, s2
0x41,0xc0,0x67,0x1e = frinti d1, d2
0x41,0x40,0xe5,0x1e = frintm h1, h2
0x41,0x40,0x25,0x1e = frintm s1, s2
0x41,0x40,0x65,0x1e = frintm d1, d2
0x41,0x40,0xe4,0x1e = frintn h1, h2
0x41,0x40,0x24,0x1e = frintn s1, s2
0x41,0x40,0x64,0x1e = frintn d1, d2
0x41,0xc0,0xe4,0x1e = frintp h1, h2
0x41,0xc0,0x24,0x1e = frintp s1, s2
0x41,0xc0,0x64,0x1e = frintp d1, d2
0x41,0x40,0xe7,0x1e = frintx h1, h2
0x41,0x40,0x27,0x1e = frintx s1, s2
0x41,0x40,0x67,0x1e = frintx d1, d2
0x41,0xc0,0xe5,0x1e = frintz h1, h2
0x41,0xc0,0x25,0x1e = frintz s1, s2
0x41,0xc0,0x65,0x1e = frintz d1, d2
0x00,0x3c,0xe0,0x7e = cmhs d0, d0, d0
0x00,0x8c,0xe0,0x5e = cmtst d0, d0, d0
0x44,0x48,0x21,0x5e = sqxtn b4, h2
0x62,0x48,0x61,0x5e = sqxtn h2, s3
0x49,0x48,0xa1,0x5e = sqxtn s9, d2
0x44,0x28,0x21,0x7e = sqxtun b4, h2
0x62,0x28,0x61,0x7e = sqxtun h2, s3
0x49,0x28,0xa1,0x7e = sqxtun s9, d2
0x44,0x48,0x21,0x7e = uqxtn b4, h2
0x62,0x48,0x61,0x7e = uqxtn h2, s3
0x49,0x48,0xa1,0x7e = uqxtn s9, d2

96
suite/MC/AArch64/arm64-logical-encoding.s.cs Normal file
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# CS_ARCH_AARCH64, 0, None
0x00,0x00,0x00,0x12 = and w0, w0, #0x1
0x00,0x00,0x40,0x92 = and x0, x0, #0x1
0x41,0x0c,0x00,0x12 = and w1, w2, #0xf
0x41,0x0c,0x40,0x92 = and x1, x2, #0xf
0xbf,0xec,0x7c,0x92 = and sp, x5, #0xfffffffffffffff0
0x00,0x00,0x00,0x72 = ands w0, w0, #0x1
0x00,0x00,0x40,0xf2 = ands x0, x0, #0x1
0x41,0x0c,0x00,0x72 = ands w1, w2, #0xf
0x41,0x0c,0x40,0xf2 = ands x1, x2, #0xf
0x41,0x00,0x12,0x52 = eor w1, w2, #0x4000
0x41,0x00,0x71,0xd2 = eor x1, x2, #0x8000
0x41,0x00,0x12,0x32 = orr w1, w2, #0x4000
0x41,0x00,0x71,0xb2 = orr x1, x2, #0x8000
0xe8,0x03,0x00,0x32 = orr w8, wzr, #0x1
0xe8,0x03,0x40,0xb2 = orr x8, xzr, #0x1
0x41,0x00,0x03,0x0a = and w1, w2, w3
0x41,0x00,0x03,0x8a = and x1, x2, x3
0x41,0x08,0x03,0x0a = and w1, w2, w3, lsl #2
0x41,0x08,0x03,0x8a = and x1, x2, x3, lsl #2
0x41,0x08,0x43,0x0a = and w1, w2, w3, lsr #2
0x41,0x08,0x43,0x8a = and x1, x2, x3, lsr #2
0x41,0x08,0x83,0x0a = and w1, w2, w3, asr #2
0x41,0x08,0x83,0x8a = and x1, x2, x3, asr #2
0x41,0x08,0xc3,0x0a = and w1, w2, w3, ror #2
0x41,0x08,0xc3,0x8a = and x1, x2, x3, ror #2
0x41,0x00,0x03,0x6a = ands w1, w2, w3
0x41,0x00,0x03,0xea = ands x1, x2, x3
0x41,0x08,0x03,0x6a = ands w1, w2, w3, lsl #2
0x41,0x08,0x03,0xea = ands x1, x2, x3, lsl #2
0x41,0x08,0x43,0x6a = ands w1, w2, w3, lsr #2
0x41,0x08,0x43,0xea = ands x1, x2, x3, lsr #2
0x41,0x08,0x83,0x6a = ands w1, w2, w3, asr #2
0x41,0x08,0x83,0xea = ands x1, x2, x3, asr #2
0x41,0x08,0xc3,0x6a = ands w1, w2, w3, ror #2
0x41,0x08,0xc3,0xea = ands x1, x2, x3, ror #2
0x41,0x00,0x23,0x0a = bic w1, w2, w3
0x41,0x00,0x23,0x8a = bic x1, x2, x3
0x41,0x0c,0x23,0x0a = bic w1, w2, w3, lsl #3
0x41,0x0c,0x23,0x8a = bic x1, x2, x3, lsl #3
0x41,0x0c,0x63,0x0a = bic w1, w2, w3, lsr #3
0x41,0x0c,0x63,0x8a = bic x1, x2, x3, lsr #3
0x41,0x0c,0xa3,0x0a = bic w1, w2, w3, asr #3
0x41,0x0c,0xa3,0x8a = bic x1, x2, x3, asr #3
0x41,0x0c,0xe3,0x0a = bic w1, w2, w3, ror #3
0x41,0x0c,0xe3,0x8a = bic x1, x2, x3, ror #3
0x41,0x00,0x23,0x6a = bics w1, w2, w3
0x41,0x00,0x23,0xea = bics x1, x2, x3
0x41,0x0c,0x23,0x6a = bics w1, w2, w3, lsl #3
0x41,0x0c,0x23,0xea = bics x1, x2, x3, lsl #3
0x41,0x0c,0x63,0x6a = bics w1, w2, w3, lsr #3
0x41,0x0c,0x63,0xea = bics x1, x2, x3, lsr #3
0x41,0x0c,0xa3,0x6a = bics w1, w2, w3, asr #3
0x41,0x0c,0xa3,0xea = bics x1, x2, x3, asr #3
0x41,0x0c,0xe3,0x6a = bics w1, w2, w3, ror #3
0x41,0x0c,0xe3,0xea = bics x1, x2, x3, ror #3
0x41,0x00,0x23,0x4a = eon w1, w2, w3
0x41,0x00,0x23,0xca = eon x1, x2, x3
0x41,0x10,0x23,0x4a = eon w1, w2, w3, lsl #4
0x41,0x10,0x23,0xca = eon x1, x2, x3, lsl #4
0x41,0x10,0x63,0x4a = eon w1, w2, w3, lsr #4
0x41,0x10,0x63,0xca = eon x1, x2, x3, lsr #4
0x41,0x10,0xa3,0x4a = eon w1, w2, w3, asr #4
0x41,0x10,0xa3,0xca = eon x1, x2, x3, asr #4
0x41,0x10,0xe3,0x4a = eon w1, w2, w3, ror #4
0x41,0x10,0xe3,0xca = eon x1, x2, x3, ror #4
0x41,0x00,0x03,0x4a = eor w1, w2, w3
0x41,0x00,0x03,0xca = eor x1, x2, x3
0x41,0x14,0x03,0x4a = eor w1, w2, w3, lsl #5
0x41,0x14,0x03,0xca = eor x1, x2, x3, lsl #5
0x41,0x14,0x43,0x4a = eor w1, w2, w3, lsr #5
0x41,0x14,0x43,0xca = eor x1, x2, x3, lsr #5
0x41,0x14,0x83,0x4a = eor w1, w2, w3, asr #5
0x41,0x14,0x83,0xca = eor x1, x2, x3, asr #5
0x41,0x14,0xc3,0x4a = eor w1, w2, w3, ror #5
0x41,0x14,0xc3,0xca = eor x1, x2, x3, ror #5
0x41,0x00,0x03,0x2a = orr w1, w2, w3
0x41,0x00,0x03,0xaa = orr x1, x2, x3
0x41,0x18,0x03,0x2a = orr w1, w2, w3, lsl #6
0x41,0x18,0x03,0xaa = orr x1, x2, x3, lsl #6
0x41,0x18,0x43,0x2a = orr w1, w2, w3, lsr #6
0x41,0x18,0x43,0xaa = orr x1, x2, x3, lsr #6
0x41,0x18,0x83,0x2a = orr w1, w2, w3, asr #6
0x41,0x18,0x83,0xaa = orr x1, x2, x3, asr #6
0x41,0x18,0xc3,0x2a = orr w1, w2, w3, ror #6
0x41,0x18,0xc3,0xaa = orr x1, x2, x3, ror #6
0x41,0x00,0x23,0x2a = orn w1, w2, w3
0x41,0x00,0x23,0xaa = orn x1, x2, x3
0x41,0x1c,0x23,0x2a = orn w1, w2, w3, lsl #7
0x41,0x1c,0x23,0xaa = orn x1, x2, x3, lsl #7
0x41,0x1c,0x63,0x2a = orn w1, w2, w3, lsr #7
0x41,0x1c,0x63,0xaa = orn x1, x2, x3, lsr #7
0x41,0x1c,0xa3,0x2a = orn w1, w2, w3, asr #7
0x41,0x1c,0xa3,0xaa = orn x1, x2, x3, asr #7
0x41,0x1c,0xe3,0x2a = orn w1, w2, w3, ror #7
0x41,0x1c,0xe3,0xaa = orn x1, x2, x3, ror #7

248
suite/MC/AArch64/arm64-memory.s.cs Normal file
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# CS_ARCH_AARCH64, 0, None
0x85,0x14,0x40,0xb9 = ldr w5, [x4, #20]
0x64,0x00,0x40,0xf9 = ldr x4, [x3]
0xe2,0x13,0x40,0xf9 = ldr x2, [sp, #32]
0xe5,0x07,0x40,0x3d = ldr b5, [sp, #1]
0xe6,0x07,0x40,0x7d = ldr h6, [sp, #2]
0xe7,0x07,0x40,0xbd = ldr s7, [sp, #4]
0xe8,0x07,0x40,0xfd = ldr d8, [sp, #8]
0xe9,0x07,0xc0,0x3d = ldr q9, [sp, #16]
0x64,0x00,0x40,0x39 = ldrb w4, [x3]
0x85,0x50,0x40,0x39 = ldrb w5, [x4, #20]
0x69,0x00,0xc0,0x39 = ldrsb w9, [x3]
0xe2,0x03,0x82,0x39 = ldrsb x2, [sp, #128]
0xe2,0x43,0x40,0x79 = ldrh w2, [sp, #32]
0xe3,0x43,0xc0,0x79 = ldrsh w3, [sp, #32]
0x25,0x31,0x80,0x79 = ldrsh x5, [x9, #24]
0xe9,0x03,0x82,0xb9 = ldrsw x9, [sp, #512]
0xe5,0x13,0x80,0xf9 = prfm pldl3strm, [sp, #32]
0xff,0x13,0x80,0xf9 = prfm #31, [sp, #32]
0x40,0x00,0x80,0xf9 = prfm pldl1keep, [x2]
0x41,0x00,0x80,0xf9 = prfm pldl1strm, [x2]
0x42,0x00,0x80,0xf9 = prfm pldl2keep, [x2]
0x43,0x00,0x80,0xf9 = prfm pldl2strm, [x2]
0x44,0x00,0x80,0xf9 = prfm pldl3keep, [x2]
0x45,0x00,0x80,0xf9 = prfm pldl3strm, [x2]
0x50,0x00,0x80,0xf9 = prfm pstl1keep, [x2]
0x51,0x00,0x80,0xf9 = prfm pstl1strm, [x2]
0x52,0x00,0x80,0xf9 = prfm pstl2keep, [x2]
0x53,0x00,0x80,0xf9 = prfm pstl2strm, [x2]
0x54,0x00,0x80,0xf9 = prfm pstl3keep, [x2]
0x55,0x00,0x80,0xf9 = prfm pstl3strm, [x2]
0x95,0x78,0xa5,0xf8 = prfm pstl3strm, [x4, x5, lsl #3]
0x64,0x00,0x00,0xf9 = str x4, [x3]
0xe2,0x13,0x00,0xf9 = str x2, [sp, #32]
0x85,0x14,0x00,0xb9 = str w5, [x4, #20]
0xe5,0x07,0x00,0x3d = str b5, [sp, #1]
0xe6,0x07,0x00,0x7d = str h6, [sp, #2]
0xe7,0x07,0x00,0xbd = str s7, [sp, #4]
0xe8,0x07,0x00,0xfd = str d8, [sp, #8]
0xe9,0x07,0x80,0x3d = str q9, [sp, #16]
0x64,0x00,0x00,0x39 = strb w4, [x3]
0x85,0x50,0x00,0x39 = strb w5, [x4, #20]
0xe2,0x43,0x00,0x79 = strh w2, [sp, #32]
0x62,0x00,0x40,0xb8 = ldur w2, [x3]
0xe2,0x83,0x41,0xb8 = ldur w2, [sp, #24]
0x62,0x00,0x40,0xf8 = ldur x2, [x3]
0xe2,0x83,0x41,0xf8 = ldur x2, [sp, #24]
0xe5,0x13,0x40,0x3c = ldur b5, [sp, #1]
0xe6,0x23,0x40,0x7c = ldur h6, [sp, #2]
0xe7,0x43,0x40,0xbc = ldur s7, [sp, #4]
0xe8,0x83,0x40,0xfc = ldur d8, [sp, #8]
0xe9,0x03,0xc1,0x3c = ldur q9, [sp, #16]
0x69,0x00,0xc0,0x38 = ldursb w9, [x3]
0xe2,0x03,0x88,0x38 = ldursb x2, [sp, #128]
0xe3,0x03,0xc2,0x78 = ldursh w3, [sp, #32]
0x25,0x81,0x81,0x78 = ldursh x5, [x9, #24]
0xe9,0x03,0x98,0xb8 = ldursw x9, [sp, #-128]
0x64,0x00,0x00,0xb8 = stur w4, [x3]
0xe2,0x03,0x02,0xb8 = stur w2, [sp, #32]
0x64,0x00,0x00,0xf8 = stur x4, [x3]
0xe2,0x03,0x02,0xf8 = stur x2, [sp, #32]
0x85,0x40,0x01,0xb8 = stur w5, [x4, #20]
0xe5,0x13,0x00,0x3c = stur b5, [sp, #1]
0xe6,0x23,0x00,0x7c = stur h6, [sp, #2]
0xe7,0x43,0x00,0xbc = stur s7, [sp, #4]
0xe8,0x83,0x00,0xfc = stur d8, [sp, #8]
0xe9,0x03,0x81,0x3c = stur q9, [sp, #16]
0x64,0x00,0x00,0x38 = sturb w4, [x3]
0x85,0x40,0x01,0x38 = sturb w5, [x4, #20]
0xe2,0x03,0x02,0x78 = sturh w2, [sp, #32]
0xe5,0x03,0x82,0xf8 = prfum pldl3strm, [sp, #32]
0x83,0x08,0x41,0xb8 = ldtr w3, [x4, #16]
0x83,0x08,0x41,0xf8 = ldtr x3, [x4, #16]
0x83,0x08,0x41,0x38 = ldtrb w3, [x4, #16]
0x69,0x08,0xc0,0x38 = ldtrsb w9, [x3]
0xe2,0x0b,0x88,0x38 = ldtrsb x2, [sp, #128]
0x83,0x08,0x41,0x78 = ldtrh w3, [x4, #16]
0xe3,0x0b,0xc2,0x78 = ldtrsh w3, [sp, #32]
0x25,0x89,0x81,0x78 = ldtrsh x5, [x9, #24]
0xe9,0x0b,0x98,0xb8 = ldtrsw x9, [sp, #-128]
0x85,0x48,0x01,0xb8 = sttr w5, [x4, #20]
0x64,0x08,0x00,0xf8 = sttr x4, [x3]
0xe2,0x0b,0x02,0xf8 = sttr x2, [sp, #32]
0x64,0x08,0x00,0x38 = sttrb w4, [x3]
0x85,0x48,0x01,0x38 = sttrb w5, [x4, #20]
0xe2,0x0b,0x02,0x78 = sttrh w2, [sp, #32]
0xfd,0x8c,0x40,0xf8 = ldr x29, [x7, #8]!
0xfe,0x8c,0x40,0xf8 = ldr x30, [x7, #8]!
0x05,0x1c,0x40,0x3c = ldr b5, [x0, #1]!
0x06,0x2c,0x40,0x7c = ldr h6, [x0, #2]!
0x07,0x4c,0x40,0xbc = ldr s7, [x0, #4]!
0x08,0x8c,0x40,0xfc = ldr d8, [x0, #8]!
0x09,0x0c,0xc1,0x3c = ldr q9, [x0, #16]!
0xfe,0x8c,0x1f,0xf8 = str x30, [x7, #-8]!
0xfd,0x8c,0x1f,0xf8 = str x29, [x7, #-8]!
0x05,0xfc,0x1f,0x3c = str b5, [x0, #-1]!
0x06,0xec,0x1f,0x7c = str h6, [x0, #-2]!
0x07,0xcc,0x1f,0xbc = str s7, [x0, #-4]!
0x08,0x8c,0x1f,0xfc = str d8, [x0, #-8]!
0x09,0x0c,0x9f,0x3c = str q9, [x0, #-16]!
0xfe,0x84,0x1f,0xf8 = str x30, [x7], #-8
0xfd,0x84,0x1f,0xf8 = str x29, [x7], #-8
0x05,0xf4,0x1f,0x3c = str b5, [x0], #-1
0x06,0xe4,0x1f,0x7c = str h6, [x0], #-2
0x07,0xc4,0x1f,0xbc = str s7, [x0], #-4
0x08,0x84,0x1f,0xfc = str d8, [x0], #-8
0x09,0x04,0x9f,0x3c = str q9, [x0], #-16
0xfd,0x84,0x40,0xf8 = ldr x29, [x7], #8
0xfe,0x84,0x40,0xf8 = ldr x30, [x7], #8
0x05,0x14,0x40,0x3c = ldr b5, [x0], #1
0x06,0x24,0x40,0x7c = ldr h6, [x0], #2
0x07,0x44,0x40,0xbc = ldr s7, [x0], #4
0x08,0x84,0x40,0xfc = ldr d8, [x0], #8
0x09,0x04,0xc1,0x3c = ldr q9, [x0], #16
0xe3,0x09,0x42,0x29 = ldp w3, w2, [x15, #16]
0xe4,0x27,0x7f,0xa9 = ldp x4, x9, [sp, #-16]
0xc2,0x0d,0x42,0x69 = ldpsw x2, x3, [x14, #16]
0xe2,0x0f,0x7e,0x69 = ldpsw x2, x3, [sp, #-16]
0x4a,0x04,0x48,0x2d = ldp s10, s1, [x2, #64]
0x4a,0x04,0x40,0x6d = ldp d10, d1, [x2]
0x02,0x0c,0x41,0xad = ldp q2, q3, [x0, #32]
0xe3,0x09,0x02,0x29 = stp w3, w2, [x15, #16]
0xe4,0x27,0x3f,0xa9 = stp x4, x9, [sp, #-16]
0x4a,0x04,0x08,0x2d = stp s10, s1, [x2, #64]
0x4a,0x04,0x00,0x6d = stp d10, d1, [x2]
0x02,0x0c,0x01,0xad = stp q2, q3, [x0, #32]
0xe3,0x09,0xc2,0x29 = ldp w3, w2, [x15, #16]!
0xe4,0x27,0xff,0xa9 = ldp x4, x9, [sp, #-16]!
0xc2,0x0d,0xc2,0x69 = ldpsw x2, x3, [x14, #16]!
0xe2,0x0f,0xfe,0x69 = ldpsw x2, x3, [sp, #-16]!
0x4a,0x04,0xc8,0x2d = ldp s10, s1, [x2, #64]!
0x4a,0x04,0xc1,0x6d = ldp d10, d1, [x2, #16]!
0xe3,0x09,0x82,0x29 = stp w3, w2, [x15, #16]!
0xe4,0x27,0xbf,0xa9 = stp x4, x9, [sp, #-16]!
0x4a,0x04,0x88,0x2d = stp s10, s1, [x2, #64]!
0x4a,0x04,0x81,0x6d = stp d10, d1, [x2, #16]!
0xe3,0x09,0xc2,0x28 = ldp w3, w2, [x15], #16
0xe4,0x27,0xff,0xa8 = ldp x4, x9, [sp], #-16
0xc2,0x0d,0xc2,0x68 = ldpsw x2, x3, [x14], #16
0xe2,0x0f,0xfe,0x68 = ldpsw x2, x3, [sp], #-16
0x4a,0x04,0xc8,0x2c = ldp s10, s1, [x2], #64
0x4a,0x04,0xc1,0x6c = ldp d10, d1, [x2], #16
0xe3,0x09,0x82,0x28 = stp w3, w2, [x15], #16
0xe4,0x27,0xbf,0xa8 = stp x4, x9, [sp], #-16
0x4a,0x04,0x88,0x2c = stp s10, s1, [x2], #64
0x4a,0x04,0x81,0x6c = stp d10, d1, [x2], #16
0xe3,0x09,0x42,0x28 = ldnp w3, w2, [x15, #16]
0xe4,0x27,0x7f,0xa8 = ldnp x4, x9, [sp, #-16]
0x4a,0x04,0x48,0x2c = ldnp s10, s1, [x2, #64]
0x4a,0x04,0x40,0x6c = ldnp d10, d1, [x2]
0xe3,0x09,0x02,0x28 = stnp w3, w2, [x15, #16]
0xe4,0x27,0x3f,0xa8 = stnp x4, x9, [sp, #-16]
0x4a,0x04,0x08,0x2c = stnp s10, s1, [x2, #64]
0x4a,0x04,0x00,0x6c = stnp d10, d1, [x2]
0x00,0x68,0x60,0xb8 = ldr w0, [x0, x0]
0x00,0x78,0x60,0xb8 = ldr w0, [x0, x0, lsl #2]
0x00,0x68,0x60,0xf8 = ldr x0, [x0, x0]
0x00,0x78,0x60,0xf8 = ldr x0, [x0, x0, lsl #3]
0x00,0xe8,0x60,0xf8 = ldr x0, [x0, x0, sxtx]
0x21,0x68,0x62,0x3c = ldr b1, [x1, x2]
0x21,0x78,0x62,0x3c = ldr b1, [x1, x2, lsl #0]
0x21,0x68,0x62,0x7c = ldr h1, [x1, x2]
0x21,0x78,0x62,0x7c = ldr h1, [x1, x2, lsl #1]
0x21,0x68,0x62,0xbc = ldr s1, [x1, x2]
0x21,0x78,0x62,0xbc = ldr s1, [x1, x2, lsl #2]
0x21,0x68,0x62,0xfc = ldr d1, [x1, x2]
0x21,0x78,0x62,0xfc = ldr d1, [x1, x2, lsl #3]
0x21,0x68,0xe2,0x3c = ldr q1, [x1, x2]
0x21,0x78,0xe2,0x3c = ldr q1, [x1, x2, lsl #4]
0xe1,0x6b,0x23,0xfc = str d1, [sp, x3]
0xe1,0x5b,0x23,0xfc = str d1, [sp, w3, uxtw #3]
0xe1,0x6b,0xa3,0x3c = str q1, [sp, x3]
0xe1,0x5b,0xa3,0x3c = str q1, [sp, w3, uxtw #4]
0x26,0x7c,0x5f,0x08 = ldxrb w6, [x1]
0x26,0x7c,0x5f,0x48 = ldxrh w6, [x1]
0x27,0x0d,0x7f,0x88 = ldxp w7, w3, [x9]
0x27,0x0d,0x7f,0xc8 = ldxp x7, x3, [x9]
0x64,0x7c,0x01,0xc8 = stxr w1, x4, [x3]
0x64,0x7c,0x01,0x88 = stxr w1, w4, [x3]
0x64,0x7c,0x01,0x08 = stxrb w1, w4, [x3]
0x64,0x7c,0x01,0x48 = stxrh w1, w4, [x3]
0xe2,0x18,0x21,0xc8 = stxp w1, x2, x6, [x7]
0x22,0x19,0x21,0x88 = stxp w1, w2, w6, [x9]
0xe4,0xff,0xdf,0x88 = ldar w4, [sp]
0xe4,0xff,0xdf,0xc8 = ldar x4, [sp]
0xe4,0xff,0xdf,0x08 = ldarb w4, [sp]
0xe4,0xff,0xdf,0x48 = ldarh w4, [sp]
0xc3,0xfc,0x9f,0x88 = stlr w3, [x6]
0xc3,0xfc,0x9f,0xc8 = stlr x3, [x6]
0xc3,0xfc,0x9f,0x08 = stlrb w3, [x6]
0xc3,0xfc,0x9f,0x48 = stlrh w3, [x6]
0xc3,0xfc,0x9f,0x88 = stlr w3, [x6]
0xc3,0xfc,0x9f,0xc8 = stlr x3, [x6]
0xe3,0xff,0x9f,0x08 = stlrb w3, [sp]
0xe3,0xff,0x9f,0x08 = stlrb w3, [sp]
0xe3,0xff,0x9f,0x08 = stlrb w3, [sp]
0x82,0xfc,0x5f,0x88 = ldaxr w2, [x4]
0x82,0xfc,0x5f,0xc8 = ldaxr x2, [x4]
0x82,0xfc,0x5f,0x08 = ldaxrb w2, [x4]
0x82,0xfc,0x5f,0x48 = ldaxrh w2, [x4]
0x22,0x98,0x7f,0x88 = ldaxp w2, w6, [x1]
0x22,0x98,0x7f,0xc8 = ldaxp x2, x6, [x1]
0x27,0xfc,0x08,0xc8 = stlxr w8, x7, [x1]
0x27,0xfc,0x08,0x88 = stlxr w8, w7, [x1]
0x27,0xfc,0x08,0x08 = stlxrb w8, w7, [x1]
0x27,0xfc,0x08,0x48 = stlxrh w8, w7, [x1]
0xe2,0x98,0x21,0xc8 = stlxp w1, x2, x6, [x7]
0x22,0x99,0x21,0x88 = stlxp w1, w2, w6, [x9]
0xab,0x83,0x5f,0xf8 = ldur x11, [x29, #-8]
0xab,0x73,0x40,0xf8 = ldur x11, [x29, #7]
0x00,0x20,0x40,0xb8 = ldur w0, [x0, #2]
0x00,0x00,0x50,0xb8 = ldur w0, [x0, #-256]
0x22,0xe0,0x5f,0x3c = ldur b2, [x1, #-2]
0x43,0x30,0x40,0x7c = ldur h3, [x2, #3]
0x63,0xc0,0x5f,0x7c = ldur h3, [x3, #-4]
0x83,0x30,0x40,0xbc = ldur s3, [x4, #3]
0xa3,0xc0,0x5f,0xbc = ldur s3, [x5, #-4]
0xc4,0x40,0x40,0xfc = ldur d4, [x6, #4]
0xe4,0x80,0x5f,0xfc = ldur d4, [x7, #-8]
0x05,0x81,0xc0,0x3c = ldur q5, [x8, #8]
0x25,0x01,0xdf,0x3c = ldur q5, [x9, #-16]
0xab,0x83,0x1f,0xf8 = stur x11, [x29, #-8]
0xab,0x73,0x00,0xf8 = stur x11, [x29, #7]
0x00,0x20,0x00,0xb8 = stur w0, [x0, #2]
0x00,0x00,0x10,0xb8 = stur w0, [x0, #-256]
0x22,0xe0,0x1f,0x3c = stur b2, [x1, #-2]
0x43,0x30,0x00,0x7c = stur h3, [x2, #3]
0x63,0xc0,0x1f,0x7c = stur h3, [x3, #-4]
0x83,0x30,0x00,0xbc = stur s3, [x4, #3]
0xa3,0xc0,0x1f,0xbc = stur s3, [x5, #-4]
0xc4,0x40,0x00,0xfc = stur d4, [x6, #4]
0xe4,0x80,0x1f,0xfc = stur d4, [x7, #-8]
0x05,0x81,0x80,0x3c = stur q5, [x8, #8]
0x25,0x01,0x9f,0x3c = stur q5, [x9, #-16]
0x23,0xf0,0x5f,0x38 = ldurb w3, [x1, #-1]
0x44,0x10,0x40,0x78 = ldurh w4, [x2, #1]
0x65,0xf0,0x5f,0x78 = ldurh w5, [x3, #-1]
0x86,0xf0,0xdf,0x38 = ldursb w6, [x4, #-1]
0xa7,0xf0,0x9f,0x38 = ldursb x7, [x5, #-1]
0xc8,0x10,0xc0,0x78 = ldursh w8, [x6, #1]
0xe9,0xf0,0xdf,0x78 = ldursh w9, [x7, #-1]
0x01,0x11,0x80,0x78 = ldursh x1, [x8, #1]
0x22,0xf1,0x9f,0x78 = ldursh x2, [x9, #-1]
0x43,0xa1,0x80,0xb8 = ldursw x3, [x10, #10]
0x64,0xf1,0x9f,0xb8 = ldursw x4, [x11, #-1]
0x23,0xf0,0x1f,0x38 = sturb w3, [x1, #-1]
0x44,0x10,0x00,0x78 = sturh w4, [x2, #1]
0x65,0xf0,0x1f,0x78 = sturh w5, [x3, #-1]

5
suite/MC/AArch64/arm64-nv-cond.s.cs Normal file
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# CS_ARCH_AARCH64, 0, None
0xfc,0xff,0x7f,0x1e = fcsel d28, d31, d31, nv
0x00,0xf0,0x80,0x9a = csel x0, x0, x0, nv
0x00,0xf0,0x40,0xfa = ccmp x0, x0, #0, nv
0x0f,0x00,0x00,0x54 = b.nv #0

8
suite/MC/AArch64/arm64-optional-hash.s.cs Normal file
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# CS_ARCH_AARCH64, 0, None
0xff,0x83,0x00,0x91 = add sp, sp, #32
0x83,0x00,0x50,0xb1 = adds x3, x4, #1024, lsl #12
0x5f,0x60,0x23,0x8b = add sp, x2, x3
0x01,0x10,0x28,0x1e = fmov s1, #0.12500000
0xbf,0x33,0x03,0xd5 = dmb osh
0xe3,0x09,0x42,0x28 = ldnp w3, w2, [x15, #16]
0x95,0x78,0xa5,0xf8 = prfm pstl3strm, [x4, x5, lsl #3]

1043
suite/MC/AArch64/arm64-simd-ldst.s.cs Normal file
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File diff suppressed because it is too large Load Diff

7
suite/MC/AArch64/arm64-spsel-sysreg.s.cs Normal file
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# CS_ARCH_AARCH64, 0, None
0xbf,0x40,0x00,0xd5 = msr SPSel, #0
0x00,0x42,0x18,0xd5 = msr SPSel, x0
0xdf,0x40,0x03,0xd5 = msr DAIFSet, #0
0x00,0x52,0x18,0xd5 = msr ESR_EL1, x0
0x00,0x42,0x38,0xd5 = mrs x0, SPSel
0x00,0x52,0x38,0xd5 = mrs x0, ESR_EL1

362
suite/MC/AArch64/arm64-system-encoding.s.cs Normal file
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# CS_ARCH_AARCH64, 0, None
0x1f,0x20,0x03,0xd5 = nop
0x9f,0x20,0x03,0xd5 = sev
0xbf,0x20,0x03,0xd5 = sevl
0x5f,0x20,0x03,0xd5 = wfe
0x7f,0x20,0x03,0xd5 = wfi
0x3f,0x20,0x03,0xd5 = yield
0x5f,0x3a,0x03,0xd5 = clrex #10
0xdf,0x3f,0x03,0xd5 = isb
0xdf,0x3f,0x03,0xd5 = isb
0xbf,0x33,0x03,0xd5 = dmb osh
0xbf,0x33,0x03,0xd5 = dmb osh
0x9f,0x37,0x03,0xd5 = dsb nsh
0x9f,0x37,0x03,0xd5 = dsb nsh
0xff,0x05,0x0a,0xd5 = sys #2, c0, c5, #7
0xe7,0x6a,0x0f,0xd5 = sys #7, c6, c10, #7, x7
0xf4,0x3f,0x2e,0xd5 = sysl x20, #6, c3, c15, #7
0x23,0x10,0x18,0xd5 = msr ACTLR_EL1, x3
0x23,0x10,0x1c,0xd5 = msr ACTLR_EL2, x3
0x23,0x10,0x1e,0xd5 = msr ACTLR_EL3, x3
0x03,0x51,0x18,0xd5 = msr AFSR0_EL1, x3
0x03,0x51,0x1c,0xd5 = msr AFSR0_EL2, x3
0x03,0x51,0x1e,0xd5 = msr AFSR0_EL3, x3
0x23,0x51,0x18,0xd5 = msr AFSR1_EL1, x3
0x23,0x51,0x1c,0xd5 = msr AFSR1_EL2, x3
0x23,0x51,0x1e,0xd5 = msr AFSR1_EL3, x3
0x03,0xa3,0x18,0xd5 = msr AMAIR_EL1, x3
0x03,0xa3,0x1c,0xd5 = msr AMAIR_EL2, x3
0x03,0xa3,0x1e,0xd5 = msr AMAIR_EL3, x3
0x03,0xe0,0x1b,0xd5 = msr CNTFRQ_EL0, x3
0x03,0xe1,0x1c,0xd5 = msr CNTHCTL_EL2, x3
0x23,0xe2,0x1c,0xd5 = msr CNTHP_CTL_EL2, x3
0x43,0xe2,0x1c,0xd5 = msr CNTHP_CVAL_EL2, x3
0x03,0xe2,0x1c,0xd5 = msr CNTHP_TVAL_EL2, x3
0x03,0xe1,0x18,0xd5 = msr CNTKCTL_EL1, x3
0x23,0xe2,0x1b,0xd5 = msr CNTP_CTL_EL0, x3
0x43,0xe2,0x1b,0xd5 = msr CNTP_CVAL_EL0, x3
0x03,0xe2,0x1b,0xd5 = msr CNTP_TVAL_EL0, x3
0x63,0xe0,0x1c,0xd5 = msr CNTVOFF_EL2, x3
0x23,0xe3,0x1b,0xd5 = msr CNTV_CTL_EL0, x3
0x43,0xe3,0x1b,0xd5 = msr CNTV_CVAL_EL0, x3
0x03,0xe3,0x1b,0xd5 = msr CNTV_TVAL_EL0, x3
0x23,0xd0,0x18,0xd5 = msr CONTEXTIDR_EL1, x3
0x43,0x10,0x18,0xd5 = msr CPACR_EL1, x3
0x43,0x11,0x1c,0xd5 = msr CPTR_EL2, x3
0x43,0x11,0x1e,0xd5 = msr CPTR_EL3, x3
0x03,0x00,0x1a,0xd5 = msr CSSELR_EL1, x3
0x03,0x30,0x1c,0xd5 = msr DACR32_EL2, x3
0x03,0x52,0x18,0xd5 = msr ESR_EL1, x3
0x03,0x52,0x1c,0xd5 = msr ESR_EL2, x3
0x03,0x52,0x1e,0xd5 = msr ESR_EL3, x3
0x03,0x60,0x18,0xd5 = msr FAR_EL1, x3
0x03,0x60,0x1c,0xd5 = msr FAR_EL2, x3
0x03,0x60,0x1e,0xd5 = msr FAR_EL3, x3
0x03,0x53,0x1c,0xd5 = msr FPEXC32_EL2, x3
0xe3,0x11,0x1c,0xd5 = msr HACR_EL2, x3
0x03,0x11,0x1c,0xd5 = msr HCR_EL2, x3
0x83,0x60,0x1c,0xd5 = msr HPFAR_EL2, x3
0x63,0x11,0x1c,0xd5 = msr HSTR_EL2, x3
0x23,0x50,0x1c,0xd5 = msr IFSR32_EL2, x3
0x03,0xa2,0x18,0xd5 = msr MAIR_EL1, x3
0x03,0xa2,0x1c,0xd5 = msr MAIR_EL2, x3
0x03,0xa2,0x1e,0xd5 = msr MAIR_EL3, x3
0x23,0x11,0x1c,0xd5 = msr MDCR_EL2, x3
0x23,0x13,0x1e,0xd5 = msr MDCR_EL3, x3
0x03,0x74,0x18,0xd5 = msr PAR_EL1, x3
0x03,0x11,0x1e,0xd5 = msr SCR_EL3, x3
0x03,0x10,0x18,0xd5 = msr SCTLR_EL1, x3
0x03,0x10,0x1c,0xd5 = msr SCTLR_EL2, x3
0x03,0x10,0x1e,0xd5 = msr SCTLR_EL3, x3
0x23,0x11,0x1e,0xd5 = msr SDER32_EL3, x3
0x43,0x20,0x18,0xd5 = msr TCR_EL1, x3
0x43,0x20,0x1c,0xd5 = msr TCR_EL2, x3
0x43,0x20,0x1e,0xd5 = msr TCR_EL3, x3
0x03,0x00,0x12,0xd5 = msr TEECR32_EL1, x3
0x03,0x10,0x12,0xd5 = msr TEEHBR32_EL1, x3
0x63,0xd0,0x1b,0xd5 = msr TPIDRRO_EL0, x3
0x43,0xd0,0x1b,0xd5 = msr TPIDR_EL0, x3
0x83,0xd0,0x18,0xd5 = msr TPIDR_EL1, x3
0x43,0xd0,0x1c,0xd5 = msr TPIDR_EL2, x3
0x43,0xd0,0x1e,0xd5 = msr TPIDR_EL3, x3
0x03,0x20,0x18,0xd5 = msr TTBR0_EL1, x3
0x03,0x20,0x1c,0xd5 = msr TTBR0_EL2, x3
0x03,0x20,0x1e,0xd5 = msr TTBR0_EL3, x3
0x23,0x20,0x18,0xd5 = msr TTBR1_EL1, x3
0x03,0xc0,0x18,0xd5 = msr VBAR_EL1, x3
0x03,0xc0,0x1c,0xd5 = msr VBAR_EL2, x3
0x03,0xc0,0x1e,0xd5 = msr VBAR_EL3, x3
0xa3,0x00,0x1c,0xd5 = msr VMPIDR_EL2, x3
0x03,0x00,0x1c,0xd5 = msr VPIDR_EL2, x3
0x43,0x21,0x1c,0xd5 = msr VTCR_EL2, x3
0x03,0x21,0x1c,0xd5 = msr VTTBR_EL2, x3
0x03,0x42,0x18,0xd5 = msr SPSel, x3
0x23,0xa3,0x18,0xd5 = msr AMAIR2_EL1, x3
0x23,0xa3,0x1d,0xd5 = msr AMAIR2_EL12, x3
0x23,0xa3,0x1c,0xd5 = msr AMAIR2_EL2, x3
0x23,0xa3,0x1e,0xd5 = msr AMAIR2_EL3, x3
0x23,0xa2,0x18,0xd5 = msr MAIR2_EL1, x3
0x23,0xa2,0x1d,0xd5 = msr MAIR2_EL12, x3
0x23,0xa1,0x1c,0xd5 = msr MAIR2_EL2, x3
0x23,0xa1,0x1e,0xd5 = msr MAIR2_EL3, x3
0x43,0xa2,0x18,0xd5 = msr PIRE0_EL1, x3
0x43,0xa2,0x1d,0xd5 = msr PIRE0_EL12, x3
0x43,0xa2,0x1c,0xd5 = msr PIRE0_EL2, x3
0x63,0xa2,0x18,0xd5 = msr PIR_EL1, x3
0x63,0xa2,0x1d,0xd5 = msr PIR_EL12, x3
0x63,0xa2,0x1c,0xd5 = msr PIR_EL2, x3
0x63,0xa2,0x1e,0xd5 = msr PIR_EL3, x3
0xa3,0xa2,0x1c,0xd5 = msr S2PIR_EL2, x3
0x83,0xa2,0x1b,0xd5 = msr POR_EL0, x3
0x83,0xa2,0x18,0xd5 = msr POR_EL1, x3
0x83,0xa2,0x1d,0xd5 = msr POR_EL12, x3
0x83,0xa2,0x1c,0xd5 = msr POR_EL2, x3
0x83,0xa2,0x1e,0xd5 = msr POR_EL3, x3
0xa3,0xa2,0x18,0xd5 = msr S2POR_EL1, x3
0x63,0x10,0x18,0xd5 = msr SCTLR2_EL1, x3
0x63,0x10,0x1d,0xd5 = msr SCTLR2_EL12, x3
0x63,0x10,0x1c,0xd5 = msr SCTLR2_EL2, x3
0x63,0x10,0x1e,0xd5 = msr SCTLR2_EL3, x3
0x63,0x20,0x18,0xd5 = msr TCR2_EL1, x3
0x63,0x20,0x1d,0xd5 = msr TCR2_EL12, x3
0x63,0x20,0x1c,0xd5 = msr TCR2_EL2, x3
0x81,0xb6,0x1a,0xd5 = msr S3_2_C11_C6_4, x1
0x00,0x00,0x00,0xd5 = msr S0_0_C0_C0_0, x0
0xa2,0x34,0x0a,0xd5 = sys #2, c3, c4, #5, x2
0x23,0x10,0x38,0xd5 = mrs x3, ACTLR_EL1
0x23,0x10,0x3c,0xd5 = mrs x3, ACTLR_EL2
0x23,0x10,0x3e,0xd5 = mrs x3, ACTLR_EL3
0x03,0x51,0x38,0xd5 = mrs x3, AFSR0_EL1
0x03,0x51,0x3c,0xd5 = mrs x3, AFSR0_EL2
0x03,0x51,0x3e,0xd5 = mrs x3, AFSR0_EL3
0xe3,0x00,0x39,0xd5 = mrs x3, AIDR_EL1
0x23,0x51,0x38,0xd5 = mrs x3, AFSR1_EL1
0x23,0x51,0x3c,0xd5 = mrs x3, AFSR1_EL2
0x23,0x51,0x3e,0xd5 = mrs x3, AFSR1_EL3
0x03,0xa3,0x38,0xd5 = mrs x3, AMAIR_EL1
0x03,0xa3,0x3c,0xd5 = mrs x3, AMAIR_EL2
0x03,0xa3,0x3e,0xd5 = mrs x3, AMAIR_EL3
0x03,0x00,0x39,0xd5 = mrs x3, CCSIDR_EL1
0x23,0x00,0x39,0xd5 = mrs x3, CLIDR_EL1
0x43,0x00,0x39,0xd5 = mrs x3, CCSIDR2_EL1
0x03,0xe0,0x3b,0xd5 = mrs x3, CNTFRQ_EL0
0x03,0xe1,0x3c,0xd5 = mrs x3, CNTHCTL_EL2
0x23,0xe2,0x3c,0xd5 = mrs x3, CNTHP_CTL_EL2
0x43,0xe2,0x3c,0xd5 = mrs x3, CNTHP_CVAL_EL2
0x03,0xe2,0x3c,0xd5 = mrs x3, CNTHP_TVAL_EL2
0x03,0xe1,0x38,0xd5 = mrs x3, CNTKCTL_EL1
0x23,0xe0,0x3b,0xd5 = mrs x3, CNTPCT_EL0
0x23,0xe2,0x3b,0xd5 = mrs x3, CNTP_CTL_EL0
0x43,0xe2,0x3b,0xd5 = mrs x3, CNTP_CVAL_EL0
0x03,0xe2,0x3b,0xd5 = mrs x3, CNTP_TVAL_EL0
0x43,0xe0,0x3b,0xd5 = mrs x3, CNTVCT_EL0
0x63,0xe0,0x3c,0xd5 = mrs x3, CNTVOFF_EL2
0x23,0xe3,0x3b,0xd5 = mrs x3, CNTV_CTL_EL0
0x43,0xe3,0x3b,0xd5 = mrs x3, CNTV_CVAL_EL0
0x03,0xe3,0x3b,0xd5 = mrs x3, CNTV_TVAL_EL0
0x23,0xd0,0x38,0xd5 = mrs x3, CONTEXTIDR_EL1
0x43,0x10,0x38,0xd5 = mrs x3, CPACR_EL1
0x43,0x11,0x3c,0xd5 = mrs x3, CPTR_EL2
0x43,0x11,0x3e,0xd5 = mrs x3, CPTR_EL3
0x03,0x00,0x3a,0xd5 = mrs x3, CSSELR_EL1
0x23,0x00,0x3b,0xd5 = mrs x3, CTR_EL0
0x43,0x42,0x38,0xd5 = mrs x3, CurrentEL
0x03,0x30,0x3c,0xd5 = mrs x3, DACR32_EL2
0xe3,0x00,0x3b,0xd5 = mrs x3, DCZID_EL0
0xc3,0x00,0x38,0xd5 = mrs x3, REVIDR_EL1
0x03,0x52,0x38,0xd5 = mrs x3, ESR_EL1
0x03,0x52,0x3c,0xd5 = mrs x3, ESR_EL2
0x03,0x52,0x3e,0xd5 = mrs x3, ESR_EL3
0x03,0x60,0x38,0xd5 = mrs x3, FAR_EL1
0x03,0x60,0x3c,0xd5 = mrs x3, FAR_EL2
0x03,0x60,0x3e,0xd5 = mrs x3, FAR_EL3
0x03,0x53,0x3c,0xd5 = mrs x3, FPEXC32_EL2
0xe3,0x11,0x3c,0xd5 = mrs x3, HACR_EL2
0x03,0x11,0x3c,0xd5 = mrs x3, HCR_EL2
0x83,0x60,0x3c,0xd5 = mrs x3, HPFAR_EL2
0x63,0x11,0x3c,0xd5 = mrs x3, HSTR_EL2
0x03,0x05,0x38,0xd5 = mrs x3, ID_AA64DFR0_EL1
0x23,0x05,0x38,0xd5 = mrs x3, ID_AA64DFR1_EL1
0x03,0x06,0x38,0xd5 = mrs x3, ID_AA64ISAR0_EL1
0x23,0x06,0x38,0xd5 = mrs x3, ID_AA64ISAR1_EL1
0x43,0x06,0x38,0xd5 = mrs x3, ID_AA64ISAR2_EL1
0x03,0x07,0x38,0xd5 = mrs x3, ID_AA64MMFR0_EL1
0x23,0x07,0x38,0xd5 = mrs x3, ID_AA64MMFR1_EL1
0x43,0x07,0x38,0xd5 = mrs x3, ID_AA64MMFR2_EL1
0x63,0x07,0x38,0xd5 = mrs x3, ID_AA64MMFR3_EL1
0x83,0x07,0x38,0xd5 = mrs x3, ID_AA64MMFR4_EL1
0x03,0x04,0x38,0xd5 = mrs x3, ID_AA64PFR0_EL1
0x23,0x04,0x38,0xd5 = mrs x3, ID_AA64PFR1_EL1
0x43,0x04,0x38,0xd5 = mrs x3, ID_AA64PFR2_EL1
0x23,0x50,0x3c,0xd5 = mrs x3, IFSR32_EL2
0x03,0xc1,0x38,0xd5 = mrs x3, ISR_EL1
0x03,0xa2,0x38,0xd5 = mrs x3, MAIR_EL1
0x03,0xa2,0x3c,0xd5 = mrs x3, MAIR_EL2
0x03,0xa2,0x3e,0xd5 = mrs x3, MAIR_EL3
0x23,0x11,0x3c,0xd5 = mrs x3, MDCR_EL2
0x23,0x13,0x3e,0xd5 = mrs x3, MDCR_EL3
0x03,0x00,0x38,0xd5 = mrs x3, MIDR_EL1
0xa3,0x00,0x38,0xd5 = mrs x3, MPIDR_EL1
0x03,0x03,0x38,0xd5 = mrs x3, MVFR0_EL1
0x23,0x03,0x38,0xd5 = mrs x3, MVFR1_EL1
0x03,0x74,0x38,0xd5 = mrs x3, PAR_EL1
0x23,0xc0,0x38,0xd5 = mrs x3, RVBAR_EL1
0x23,0xc0,0x3c,0xd5 = mrs x3, RVBAR_EL2
0x23,0xc0,0x3e,0xd5 = mrs x3, RVBAR_EL3
0x03,0x11,0x3e,0xd5 = mrs x3, SCR_EL3
0x03,0x10,0x38,0xd5 = mrs x3, SCTLR_EL1
0x03,0x10,0x3c,0xd5 = mrs x3, SCTLR_EL2
0x03,0x10,0x3e,0xd5 = mrs x3, SCTLR_EL3
0x23,0x11,0x3e,0xd5 = mrs x3, SDER32_EL3
0x43,0x20,0x38,0xd5 = mrs x3, TCR_EL1
0x43,0x20,0x3c,0xd5 = mrs x3, TCR_EL2
0x43,0x20,0x3e,0xd5 = mrs x3, TCR_EL3
0x03,0x00,0x32,0xd5 = mrs x3, TEECR32_EL1
0x03,0x10,0x32,0xd5 = mrs x3, TEEHBR32_EL1
0x63,0xd0,0x3b,0xd5 = mrs x3, TPIDRRO_EL0
0x43,0xd0,0x3b,0xd5 = mrs x3, TPIDR_EL0
0x83,0xd0,0x38,0xd5 = mrs x3, TPIDR_EL1
0x43,0xd0,0x3c,0xd5 = mrs x3, TPIDR_EL2
0x43,0xd0,0x3e,0xd5 = mrs x3, TPIDR_EL3
0x03,0x20,0x38,0xd5 = mrs x3, TTBR0_EL1
0x03,0x20,0x3c,0xd5 = mrs x3, TTBR0_EL2
0x03,0x20,0x3e,0xd5 = mrs x3, TTBR0_EL3
0x23,0x20,0x38,0xd5 = mrs x3, TTBR1_EL1
0x03,0xc0,0x38,0xd5 = mrs x3, VBAR_EL1
0x03,0xc0,0x3c,0xd5 = mrs x3, VBAR_EL2
0x03,0xc0,0x3e,0xd5 = mrs x3, VBAR_EL3
0xa3,0x00,0x3c,0xd5 = mrs x3, VMPIDR_EL2
0x03,0x00,0x3c,0xd5 = mrs x3, VPIDR_EL2
0x43,0x21,0x3c,0xd5 = mrs x3, VTCR_EL2
0x03,0x21,0x3c,0xd5 = mrs x3, VTTBR_EL2
0x03,0x01,0x33,0xd5 = mrs x3, MDCCSR_EL0
0x03,0x02,0x30,0xd5 = mrs x3, MDCCINT_EL1
0x03,0x04,0x33,0xd5 = mrs x3, DBGDTR_EL0
0x03,0x05,0x33,0xd5 = mrs x3, DBGDTRRX_EL0
0x03,0x07,0x34,0xd5 = mrs x3, DBGVCR32_EL2
0x43,0x00,0x30,0xd5 = mrs x3, OSDTRRX_EL1
0x43,0x02,0x30,0xd5 = mrs x3, MDSCR_EL1
0x43,0x03,0x30,0xd5 = mrs x3, OSDTRTX_EL1
0x43,0x06,0x30,0xd5 = mrs x3, OSECCR_EL1
0x83,0x00,0x30,0xd5 = mrs x3, DBGBVR0_EL1
0x83,0x01,0x30,0xd5 = mrs x3, DBGBVR1_EL1
0x83,0x02,0x30,0xd5 = mrs x3, DBGBVR2_EL1
0x83,0x03,0x30,0xd5 = mrs x3, DBGBVR3_EL1
0x83,0x04,0x30,0xd5 = mrs x3, DBGBVR4_EL1
0x83,0x05,0x30,0xd5 = mrs x3, DBGBVR5_EL1
0x83,0x06,0x30,0xd5 = mrs x3, DBGBVR6_EL1
0x83,0x07,0x30,0xd5 = mrs x3, DBGBVR7_EL1
0x83,0x08,0x30,0xd5 = mrs x3, DBGBVR8_EL1
0x83,0x09,0x30,0xd5 = mrs x3, DBGBVR9_EL1
0x83,0x0a,0x30,0xd5 = mrs x3, DBGBVR10_EL1
0x83,0x0b,0x30,0xd5 = mrs x3, DBGBVR11_EL1
0x83,0x0c,0x30,0xd5 = mrs x3, DBGBVR12_EL1
0x83,0x0d,0x30,0xd5 = mrs x3, DBGBVR13_EL1
0x83,0x0e,0x30,0xd5 = mrs x3, DBGBVR14_EL1
0x83,0x0f,0x30,0xd5 = mrs x3, DBGBVR15_EL1
0xa3,0x00,0x30,0xd5 = mrs x3, DBGBCR0_EL1
0xa3,0x01,0x30,0xd5 = mrs x3, DBGBCR1_EL1
0xa3,0x02,0x30,0xd5 = mrs x3, DBGBCR2_EL1
0xa3,0x03,0x30,0xd5 = mrs x3, DBGBCR3_EL1
0xa3,0x04,0x30,0xd5 = mrs x3, DBGBCR4_EL1
0xa3,0x05,0x30,0xd5 = mrs x3, DBGBCR5_EL1
0xa3,0x06,0x30,0xd5 = mrs x3, DBGBCR6_EL1
0xa3,0x07,0x30,0xd5 = mrs x3, DBGBCR7_EL1
0xa3,0x08,0x30,0xd5 = mrs x3, DBGBCR8_EL1
0xa3,0x09,0x30,0xd5 = mrs x3, DBGBCR9_EL1
0xa3,0x0a,0x30,0xd5 = mrs x3, DBGBCR10_EL1
0xa3,0x0b,0x30,0xd5 = mrs x3, DBGBCR11_EL1
0xa3,0x0c,0x30,0xd5 = mrs x3, DBGBCR12_EL1
0xa3,0x0d,0x30,0xd5 = mrs x3, DBGBCR13_EL1
0xa3,0x0e,0x30,0xd5 = mrs x3, DBGBCR14_EL1
0xa3,0x0f,0x30,0xd5 = mrs x3, DBGBCR15_EL1
0xc3,0x00,0x30,0xd5 = mrs x3, DBGWVR0_EL1
0xc3,0x01,0x30,0xd5 = mrs x3, DBGWVR1_EL1
0xc3,0x02,0x30,0xd5 = mrs x3, DBGWVR2_EL1
0xc3,0x03,0x30,0xd5 = mrs x3, DBGWVR3_EL1
0xc3,0x04,0x30,0xd5 = mrs x3, DBGWVR4_EL1
0xc3,0x05,0x30,0xd5 = mrs x3, DBGWVR5_EL1
0xc3,0x06,0x30,0xd5 = mrs x3, DBGWVR6_EL1
0xc3,0x07,0x30,0xd5 = mrs x3, DBGWVR7_EL1
0xc3,0x08,0x30,0xd5 = mrs x3, DBGWVR8_EL1
0xc3,0x09,0x30,0xd5 = mrs x3, DBGWVR9_EL1
0xc3,0x0a,0x30,0xd5 = mrs x3, DBGWVR10_EL1
0xc3,0x0b,0x30,0xd5 = mrs x3, DBGWVR11_EL1
0xc3,0x0c,0x30,0xd5 = mrs x3, DBGWVR12_EL1
0xc3,0x0d,0x30,0xd5 = mrs x3, DBGWVR13_EL1
0xc3,0x0e,0x30,0xd5 = mrs x3, DBGWVR14_EL1
0xc3,0x0f,0x30,0xd5 = mrs x3, DBGWVR15_EL1
0xe3,0x00,0x30,0xd5 = mrs x3, DBGWCR0_EL1
0xe3,0x01,0x30,0xd5 = mrs x3, DBGWCR1_EL1
0xe3,0x02,0x30,0xd5 = mrs x3, DBGWCR2_EL1
0xe3,0x03,0x30,0xd5 = mrs x3, DBGWCR3_EL1
0xe3,0x04,0x30,0xd5 = mrs x3, DBGWCR4_EL1
0xe3,0x05,0x30,0xd5 = mrs x3, DBGWCR5_EL1
0xe3,0x06,0x30,0xd5 = mrs x3, DBGWCR6_EL1
0xe3,0x07,0x30,0xd5 = mrs x3, DBGWCR7_EL1
0xe3,0x08,0x30,0xd5 = mrs x3, DBGWCR8_EL1
0xe3,0x09,0x30,0xd5 = mrs x3, DBGWCR9_EL1
0xe3,0x0a,0x30,0xd5 = mrs x3, DBGWCR10_EL1
0xe3,0x0b,0x30,0xd5 = mrs x3, DBGWCR11_EL1
0xe3,0x0c,0x30,0xd5 = mrs x3, DBGWCR12_EL1
0xe3,0x0d,0x30,0xd5 = mrs x3, DBGWCR13_EL1
0xe3,0x0e,0x30,0xd5 = mrs x3, DBGWCR14_EL1
0xe3,0x0f,0x30,0xd5 = mrs x3, DBGWCR15_EL1
0x03,0x10,0x30,0xd5 = mrs x3, MDRAR_EL1
0x83,0x11,0x30,0xd5 = mrs x3, OSLSR_EL1
0x83,0x13,0x30,0xd5 = mrs x3, OSDLR_EL1
0x83,0x14,0x30,0xd5 = mrs x3, DBGPRCR_EL1
0xc3,0x78,0x30,0xd5 = mrs x3, DBGCLAIMSET_EL1
0xc3,0x79,0x30,0xd5 = mrs x3, DBGCLAIMCLR_EL1
0xc3,0x7e,0x30,0xd5 = mrs x3, DBGAUTHSTATUS_EL1
0x23,0xa3,0x38,0xd5 = mrs x3, AMAIR2_EL1
0x23,0xa3,0x3d,0xd5 = mrs x3, AMAIR2_EL12
0x23,0xa3,0x3c,0xd5 = mrs x3, AMAIR2_EL2
0x23,0xa3,0x3e,0xd5 = mrs x3, AMAIR2_EL3
0x23,0xa2,0x38,0xd5 = mrs x3, MAIR2_EL1
0x23,0xa2,0x3d,0xd5 = mrs x3, MAIR2_EL12
0x23,0xa1,0x3c,0xd5 = mrs x3, MAIR2_EL2
0x23,0xa1,0x3e,0xd5 = mrs x3, MAIR2_EL3
0x43,0xa2,0x38,0xd5 = mrs x3, PIRE0_EL1
0x43,0xa2,0x3d,0xd5 = mrs x3, PIRE0_EL12
0x43,0xa2,0x3c,0xd5 = mrs x3, PIRE0_EL2
0x63,0xa2,0x38,0xd5 = mrs x3, PIR_EL1
0x63,0xa2,0x3d,0xd5 = mrs x3, PIR_EL12
0x63,0xa2,0x3c,0xd5 = mrs x3, PIR_EL2
0x63,0xa2,0x3e,0xd5 = mrs x3, PIR_EL3
0xa3,0xa2,0x3c,0xd5 = mrs x3, S2PIR_EL2
0x83,0xa2,0x3b,0xd5 = mrs x3, POR_EL0
0x83,0xa2,0x38,0xd5 = mrs x3, POR_EL1
0x83,0xa2,0x3d,0xd5 = mrs x3, POR_EL12
0x83,0xa2,0x3c,0xd5 = mrs x3, POR_EL2
0x83,0xa2,0x3e,0xd5 = mrs x3, POR_EL3
0xa3,0xa2,0x38,0xd5 = mrs x3, S2POR_EL1
0x63,0x10,0x38,0xd5 = mrs x3, SCTLR2_EL1
0x63,0x10,0x3d,0xd5 = mrs x3, SCTLR2_EL12
0x63,0x10,0x3c,0xd5 = mrs x3, SCTLR2_EL2
0x63,0x10,0x3e,0xd5 = mrs x3, SCTLR2_EL3
0x63,0x20,0x38,0xd5 = mrs x3, TCR2_EL1
0x63,0x20,0x3d,0xd5 = mrs x3, TCR2_EL12
0x63,0x20,0x3c,0xd5 = mrs x3, TCR2_EL2
0x81,0xf6,0x3a,0xd5 = mrs x1, S3_2_C15_C6_4
0x83,0xb1,0x3b,0xd5 = mrs x3, S3_3_C11_C1_4
0x83,0xb1,0x3b,0xd5 = mrs x3, S3_3_C11_C1_4
0x40,0xc0,0x1e,0xd5 = msr RMR_EL3, x0
0x40,0xc0,0x1c,0xd5 = msr RMR_EL2, x0
0x40,0xc0,0x18,0xd5 = msr RMR_EL1, x0
0x83,0x10,0x10,0xd5 = msr OSLAR_EL1, x3
0x03,0x05,0x13,0xd5 = msr DBGDTRTX_EL0, x3
0x00,0x01,0x38,0xd5 = mrs x0, ID_PFR0_EL1
0x20,0x01,0x38,0xd5 = mrs x0, ID_PFR1_EL1
0x40,0x01,0x38,0xd5 = mrs x0, ID_DFR0_EL1
0xa0,0x03,0x38,0xd5 = mrs x0, ID_DFR1_EL1
0x60,0x01,0x38,0xd5 = mrs x0, ID_AFR0_EL1
0x00,0x02,0x38,0xd5 = mrs x0, ID_ISAR0_EL1
0x20,0x02,0x38,0xd5 = mrs x0, ID_ISAR1_EL1
0x40,0x02,0x38,0xd5 = mrs x0, ID_ISAR2_EL1
0x60,0x02,0x38,0xd5 = mrs x0, ID_ISAR3_EL1
0x80,0x02,0x38,0xd5 = mrs x0, ID_ISAR4_EL1
0xa0,0x02,0x38,0xd5 = mrs x0, ID_ISAR5_EL1
0x20,0x51,0x38,0xd5 = mrs x0, AFSR1_EL1
0x00,0x51,0x38,0xd5 = mrs x0, AFSR0_EL1
0xc0,0x00,0x38,0xd5 = mrs x0, REVIDR_EL1

2
suite/MC/AArch64/arm64-target-specific-sysreg.s.cs Normal file
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@ -0,0 +1,2 @@
# CS_ARCH_AARCH64, 0, None
0x00,0xf2,0x1f,0xd5 = msr CPM_IOACC_CTL_EL3, x0

3
suite/MC/AArch64/arm64-vector-lists.s.cs Normal file
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@ -0,0 +1,3 @@
# CS_ARCH_AARCH64, 0, None
0x00,0x00,0x00,0x0c = st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]
0x00,0x04,0x00,0x0c = st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x0]

9
suite/MC/AArch64/arm64-verbose-vector-case.s.cs Normal file
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@ -0,0 +1,9 @@
# CS_ARCH_AARCH64, 0, None
0x08,0xe1,0x28,0x0e = pmull v8.8h, v8.8b, v8.8b
0x08,0xe1,0x28,0x4e = pmull2 v8.8h, v8.16b, v8.16b
0x08,0xe1,0xe8,0x0e = pmull v8.1q, v8.1d, v8.1d
0x08,0xe1,0xe8,0x4e = pmull2 v8.1q, v8.2d, v8.2d
0x08,0xe1,0x28,0x0e = pmull v8.8h, v8.8b, v8.8b
0x08,0xe1,0x28,0x4e = pmull2 v8.8h, v8.16b, v8.16b
0x08,0xe1,0xe8,0x0e = pmull v8.1q, v8.1d, v8.1d
0x08,0xe1,0xe8,0x4e = pmull2 v8.1q, v8.2d, v8.2d

2
suite/MC/AArch64/arm64e.s.cs Normal file
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@ -0,0 +1,2 @@
# CS_ARCH_AARCH64, 0, None
0x20,0x00,0xc1,0xda = pacia x0, x1

41
suite/MC/AArch64/armv8.1a-atomic.s.cs Normal file
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@ -0,0 +1,41 @@
# CS_ARCH_AARCH64, 0, None
0x41,0x7c,0xa0,0x08 = casb w0, w1, [x2]
0x41,0x7c,0xe0,0x08 = casab w0, w1, [x2]
0x41,0xfc,0xa0,0x08 = caslb w0, w1, [x2]
0x41,0xfc,0xe0,0x08 = casalb w0, w1, [x2]
0x41,0x7c,0xa0,0x48 = cash w0, w1, [x2]
0x41,0x7c,0xe0,0x48 = casah w0, w1, [x2]
0x41,0xfc,0xa0,0x48 = caslh w0, w1, [x2]
0x41,0xfc,0xe0,0x48 = casalh w0, w1, [x2]
0x41,0x7c,0xa0,0x88 = cas w0, w1, [x2]
0x41,0x7c,0xe0,0x88 = casa w0, w1, [x2]
0x41,0xfc,0xa0,0x88 = casl w0, w1, [x2]
0x41,0xfc,0xe0,0x88 = casal w0, w1, [x2]
0x41,0x7c,0xa0,0xc8 = cas x0, x1, [x2]
0x41,0x7c,0xe0,0xc8 = casa x0, x1, [x2]
0x41,0xfc,0xa0,0xc8 = casl x0, x1, [x2]
0x41,0xfc,0xe0,0xc8 = casal x0, x1, [x2]
0x41,0x00,0xa0,0xf8 = ldadda x0, x1, [x2]
0x41,0x10,0x60,0xf8 = ldclrl x0, x1, [x2]
0x41,0x20,0xe0,0xf8 = ldeoral x0, x1, [x2]
0x41,0x30,0x20,0xf8 = ldset x0, x1, [x2]
0x41,0x40,0xa0,0xb8 = ldsmaxa w0, w1, [x2]
0x41,0x50,0x60,0x38 = ldsminlb w0, w1, [x2]
0x41,0x60,0xe0,0x78 = ldumaxalh w0, w1, [x2]
0x41,0x70,0x20,0xb8 = ldumin w0, w1, [x2]
0xa3,0x50,0x22,0x38 = ldsminb w2, w3, [x5]
0x5f,0x00,0x60,0x38 = staddlb w0, [x2]
0x5f,0x10,0x60,0x78 = stclrlh w0, [x2]
0x5f,0x20,0x60,0xb8 = steorl w0, [x2]
0x5f,0x30,0x60,0xf8 = stsetl x0, [x2]
0x5f,0x40,0x20,0x38 = stsmaxb w0, [x2]
0x5f,0x50,0x20,0x78 = stsminh w0, [x2]
0x5f,0x60,0x20,0xb8 = stumax w0, [x2]
0x5f,0x70,0x20,0xf8 = stumin x0, [x2]
0xff,0x53,0x7d,0xf8 = stsminl x29, [sp]
0x41,0x80,0x20,0xf8 = swp x0, x1, [x2]
0x41,0x80,0x20,0x38 = swpb w0, w1, [x2]
0x41,0x80,0x60,0x78 = swplh w0, w1, [x2]
0xe1,0x83,0xe0,0xf8 = swpal x0, x1, [sp]
0x82,0x7c,0x20,0x48 = casp x0, x1, x2, x3, [x4]
0x82,0x7c,0x20,0x08 = casp w0, w1, w2, w3, [x4]

14
suite/MC/AArch64/armv8.1a-lor.s.cs Normal file
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@ -0,0 +1,14 @@
# CS_ARCH_AARCH64, 0, None
0x20,0x7c,0xdf,0x08 = ldlarb w0, [x1]
0x20,0x7c,0xdf,0x48 = ldlarh w0, [x1]
0x20,0x7c,0xdf,0x88 = ldlar w0, [x1]
0x20,0x7c,0xdf,0xc8 = ldlar x0, [x1]
0x20,0x7c,0x9f,0x08 = stllrb w0, [x1]
0x20,0x7c,0x9f,0x48 = stllrh w0, [x1]
0x20,0x7c,0x9f,0x88 = stllr w0, [x1]
0x20,0x7c,0x9f,0xc8 = stllr x0, [x1]
0x00,0xa4,0x18,0xd5 = msr LORSA_EL1, x0
0x20,0xa4,0x18,0xd5 = msr LOREA_EL1, x0
0x40,0xa4,0x18,0xd5 = msr LORN_EL1, x0
0x60,0xa4,0x18,0xd5 = msr LORC_EL1, x0
0xe0,0xa4,0x38,0xd5 = mrs x0, LORID_EL1

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