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Merge branch 'next' into pip

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This commit is contained in:
Nguyen Anh Quynh 2014-11-18 10:43:46 +08:00
commit f32d08a7ec
10 changed files with 34 additions and 15 deletions
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13
arch/AArch64/AArch64InstPrinter.c
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@ -1252,13 +1252,18 @@ static void printAdrpLabel(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNum);
// If the label has already been resolved to an immediate offset (say, when
// we're running the disassembler), just print the immediate.
if (MCOperand_isImm(Op)) {
printInt64Bang(O, MCOperand_getImm(Op) << 12);
// ADRP sign extends a 21-bit offset, shifts it left by 12
// and adds it to the value of the PC with its bottom 12 bits cleared
uint64_t imm = (MCOperand_getImm(Op) << 12) + (MI->address & ~0xfff);
if (imm > HEX_THRESHOLD)
SStream_concat(O, "#0x%"PRIx64, imm);
else
SStream_concat(O, "#%"PRIu64, imm);
if (MI->csh->detail) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)MCOperand_getImm(Op) << 12;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm;
MI->flat_insn->detail->arm64.op_count++;
}
return;

10
arch/Mips/MipsInstPrinter.c
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@ -169,8 +169,9 @@ void Mips_printInst(MCInst *MI, SStream *O, void *info)
mnem = printAliasInstr(MI, O, info);
if (!mnem) {
mnem = printAlias(MI, O);
if (!mnem)
if (!mnem) {
printInstruction(MI, O, NULL);
}
}
if (mnem) {
@ -182,7 +183,12 @@ void Mips_printInst(MCInst *MI, SStream *O, void *info)
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNo);
MCOperand *Op;
if (OpNo >= MI->size)
return;
Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(Op)) {
unsigned int reg = MCOperand_getReg(Op);
printRegName(O, reg);

3
arch/XCore/XCoreInstPrinter.c
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@ -237,6 +237,9 @@ static void _printOperand(MCInst *MI, MCOperand *MO, SStream *O)
static void printOperand(MCInst *MI, int OpNum, SStream *O)
{
if (OpNum >= MI->size)
return;
_printOperand(MI, MCInst_getOperand(MI, OpNum), O);
}

2
bindings/java/capstone/Arm64.java
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@ -26,7 +26,7 @@ public class Arm64 {
public static class OpValue extends Union {
public int reg;
public int imm;
public long imm;
public double fp;
public MemType mem;
public int pstate;

2
bindings/python/capstone/arm64.py
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@ -20,7 +20,7 @@ class Arm64OpShift(ctypes.Structure):
class Arm64OpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_int32),
('imm', ctypes.c_int64),
('fp', ctypes.c_double),
('mem', Arm64OpMem),
('pstate', ctypes.c_int),

2
include/arm64.h
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@ -364,7 +364,7 @@ typedef struct cs_arm64_op {
arm64_op_type type; // operand type
union {
unsigned int reg; // register value for REG operand
int32_t imm; // immediate value, or index for C-IMM or IMM operand
int64_t imm; // immediate value, or index for C-IMM or IMM operand
double fp; // floating point value for FP operand
arm64_op_mem mem; // base/index/scale/disp value for MEM operand
arm64_pstate pstate; // PState field of MSR instruction.

4
suite/benchmark.py
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@ -28,8 +28,8 @@ all_tests = (
(CS_ARCH_X86, CS_MODE_64, "X86-64 (Intel syntax)", 0),
(CS_ARCH_ARM, CS_MODE_ARM, "ARM", 0),
(CS_ARCH_ARM, CS_MODE_THUMB, "THUMB (ARM)", 0),
(CS_ARCH_MIPS, CS_MODE_32 + CS_MODE_BIG_ENDIAN, "MIPS-32 (Big-endian)", 0),
(CS_ARCH_MIPS, CS_MODE_64 + CS_MODE_LITTLE_ENDIAN, "MIPS-64-EL (Little-endian)", 0),
(CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, "MIPS-32 (Big-endian)", 0),
(CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, "MIPS-64-EL (Little-endian)", 0),
(CS_ARCH_ARM64, CS_MODE_ARM, "ARM-64 (AArch64)", 0),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, "PPC", 0),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, "PPC, print register with number only", CS_OPT_SYNTAX_NOREGNAME),

4
suite/fuzz.py
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@ -34,8 +34,8 @@ all_tests = (
(CS_ARCH_X86, CS_MODE_64, "X86-64 (ATT syntax)", CS_OPT_SYNTAX_ATT),
(CS_ARCH_ARM, CS_MODE_ARM, "ARM", 0),
(CS_ARCH_ARM, CS_MODE_THUMB, "THUMB (ARM)", 0),
(CS_ARCH_MIPS, CS_MODE_32 + CS_MODE_BIG_ENDIAN, "MIPS-32 (Big-endian)", 0),
(CS_ARCH_MIPS, CS_MODE_64 + CS_MODE_LITTLE_ENDIAN, "MIPS-64-EL (Little-endian)", 0),
(CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, "MIPS-32 (Big-endian)", 0),
(CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, "MIPS-64-EL (Little-endian)", 0),
(CS_ARCH_ARM64, CS_MODE_ARM, "ARM-64 (AArch64)", 0),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, "PPC", 0),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, "PPC, print register with number only", CS_OPT_SYNTAX_NOREGNAME),

5
suite/x86odd.py
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@ -34,6 +34,11 @@ CODE32 += b"\x0f\x23\x00" # mov dr0, eax
CODE32 += b"\x0f\x23\x40" # mov dr0, eax
CODE32 += b"\x0f\x23\x80" # mov dr0, eax
CODE32 += b"\x66\x2e\x0f\x58\xc0" # addpd xmm0, xmm0
CODE32 += b"\x2e\x66\x0f\x58\xc0" # addpd xmm0, xmm0
CODE32 += b"\x66\xf2\x0f\x38\xf1\xc3" # crc32w %bx, %eax
CODE32 += b"\xf2\x0f\x38\xf1\x8c\xcb\xef\xbe\xad\xde" # crc32l -0x21524111(%ebx, %ecx, 8), %ecx
CODE32_MEMREF = b"\x8b\x84\x91\x23\x01\x00\x00"
CODE32_MEMREF += b"\x8b\x04\x95\x23\x01\x00\x00"
CODE32_MEMREF += b"\x8b\x04\x95\xdd\xfe\xff\xff"

4
tests/test_arm64.c
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@ -51,7 +51,7 @@ static void print_insn_detail(cs_insn *ins)
printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
break;
case ARM64_OP_IMM:
printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm);
printf("\t\toperands[%u].type: IMM = 0x%"PRIx64 "\n", i, op->imm);
break;
case ARM64_OP_FP:
printf("\t\toperands[%u].type: FP = %f\n", i, op->fp);
@ -67,7 +67,7 @@ static void print_insn_detail(cs_insn *ins)
break;
case ARM64_OP_CIMM:
printf("\t\toperands[%u].type: C-IMM = %u\n", i, op->imm);
printf("\t\toperands[%u].type: C-IMM = %u\n", i, (int)op->imm);
break;
case ARM64_OP_REG_MRS:
printf("\t\toperands[%u].type: REG_MRS = 0x%x\n", i, op->reg);