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MUL* NAND* NE* NOP NOR OR
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billow
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@ -302,6 +302,10 @@ class IRC<bits<8> op1, bits<7> op2, string asmstr>
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: RC<op1, op2, (outs), (ins s9imm:$const9),
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asmstr # " $const9", []>;
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class IRC_R<bits<8> op1, bits<7> op2, string asmstr, RegisterClass rcd>
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: RC<op1, op2, (outs rcd:$d), (ins DataRegs:$s1, s9imm:$const9),
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asmstr # " $d, $s1, $const9", []>;
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class IRC_2<bits<8> op1, bits<7> op2, string asmstr>
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: RC<op1, op2, (outs DataRegs:$d), (ins DataRegs:$s1, s9imm:$const9),
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asmstr # " $d, $s1, $const9", []>;
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@ -1398,6 +1402,93 @@ def MSUBRS_H_rrr1_DcEdDaDbUL
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defm MSUBR_Q : mIRRR1_label2_LL_UU<0x63, 0x07, 0x06, "msubr.q">;
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defm MSUBRS_Q : mIRRR1_label2_LL_UU<0x63, 0x27, 0x26, "msubrs.q">;
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class IRLC_CR<bits<8> op1, string asmstr, RegisterClass rc>
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: RLC<op1, (outs), (ins s16imm:$const16, rc:$d),
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asmstr # " $const16, $d", []>;
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// TODO: CSFR
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// def MTCR_rlc : IRLC_CR<0xCD, "mtcr", CRRegs>;
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class IRR2<bits<8> op1, bits<12> op2, string asmstr, RegisterClass rcd, RegisterClass rca, RegisterClass rcb>
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: RR2<op1, op2, (outs rcd:$d), (ins rca:$s1, rcb:$s2), asmstr # " $d, $s1, $s2", []>;
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class IRR2_RcDaDb<bits<8> op1, bits<12> op2, string asmstr, RegisterClass rcd>
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: IRR2<op1, op2, asmstr, rcd, DataRegs, DataRegs>;
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def MUL_rc : RC<0x53, 0x01, (outs DataRegs:$d), (ins DataRegs:$s1, s9imm:$const9),
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"mul $d, $s1, $const9", []>;
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def MUL_rc_e : RC<0x53, 0x03, (outs ExtRegs:$d), (ins DataRegs:$s1, s9imm:$const9),
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"mul $d, $s1, $const9", []>;
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def MUL_rr2 : IRR2_RcDaDb<0x73, 0x0A, "mul", DataRegs>;
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def MUL_rr2_e : IRR2_RcDaDb<0x73, 0x6A, "mul", ExtRegs>;
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def MUL_srr : ISRR<0xE2, "mul">;
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multiclass mIRC_RR2_RcDaDb<bits<8> rc1, bits<7> rc2, bits<8> op1, bits<12> op2, string asmstr, RegisterClass rcd>{
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def _rc : IRC_R<rc1, rc2, asmstr, rcd>;
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def _rr2 : IRR2_RcDaDb<op1, op2, asmstr, rcd>;
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}
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defm MULS : mIRC_RR2_RcDaDb<0x53, 0x05, 0x73, 0x8A, "muls", DataRegs>;
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class IRR1<bits<8> op1, bits<10> op2, string asmstr,
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RegisterClass rcd, string labela, string labelb>
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: RR1<op1, op2, (outs rcd:$d), (ins DataRegs:$s1, DataRegs:$s2, u2imm:$n),
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asmstr # " $d, ${s1}" # labela # ", ${s2}" # labelb # ", $n", []>;
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multiclass mIRR1_LU2e<bits<8> op1, bits<10> op2, bits<10> op3, bits<10> op4, bits<10> op5, string asmstr>{
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def _rr1_LL2e : IRR1<op1, op2, asmstr, ExtRegs, "", "LL">;
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def _rr1_LU2e : IRR1<op1, op3, asmstr, ExtRegs, "", "LU">;
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def _rr1_UL2e : IRR1<op1, op4, asmstr, ExtRegs, "", "UL">;
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def _rr1_UU2e : IRR1<op1, op5, asmstr, ExtRegs, "", "UU">;
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}
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defm MUL_H : mIRR1_LU2e<0xB3, 0x1A, 0x19, 0x18, 0x1B, "mul.h">;
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multiclass mIRR1_mulq<bits<8> op, bits<10> op1, bits<10> op2, bits<10> op3, bits<10> op4,
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bits<10> op5, bits<10> op6, bits<10> op7, bits<10> op8, string asmstr>{
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def _rr1_2__ : IRR1<op, op1, asmstr, DataRegs, "", "">;
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def _rr1_2__e : IRR1<op, op2, asmstr, ExtRegs, "", "">;
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def _rr1_2_L : IRR1<op, op3, asmstr, DataRegs, "", "L">;
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def _rr1_2_Le : IRR1<op, op4, asmstr, ExtRegs, "", "L">;
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def _rr1_2_U : IRR1<op, op5, asmstr, DataRegs, "", "U">;
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def _rr1_2_Ue : IRR1<op, op6, asmstr, ExtRegs, "", "U">;
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def _rr1_2LL : IRR1<op, op7, asmstr, DataRegs, "L", "L">;
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def _rr1_2UU : IRR1<op, op8, asmstr, DataRegs, "U", "U">;
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}
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defm MUL_Q : mIRR1_mulq<0x93, 0x02, 0x1B, 0x01, 0x19, 0x00, 0x18, 0x05, 0x04, "mul.q">;
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defm MUL_U : mIRC_RR2_RcDaDb<0x53, 0x02, 0x73, 0x68, "mul.u", ExtRegs>;
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defm MULS_U : mIRC_RR2_RcDaDb<0x53, 0x04, 0x73, 0x88, "muls.u", ExtRegs>;
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defm MULM_H : mIRR1_LU2e<0xB3, 0x1E, 0x1D, 0x1C, 0x1F, "mulm.h">;
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defm MULR_H : mIRR1_LU2e<0xB3, 0x0E, 0x0D, 0x0C, 0x0F, "mulr.h">;
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def MULR_Q_rr1_2LL : IRR1<0x93, 0x07, "mulr.q", DataRegs, "L", "L">;
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def MULR_Q_rr1_2UU : IRR1<0x93, 0x06, "mulr.q", DataRegs, "U", "U">;
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defm NAND : mIRR_RC<0x0F, 0x09, 0x8F, 0x09, "nand">;
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def NAND_T : IBIT<0x07, 0x00, "nand.t">;
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defm NE : mIRR_RC<0x0B, 0x11, 0x8B, 0x11, "ne">;
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def NE_A : IRR_DcAaAb<0x01, 0x41, "ne.a">;
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def NEZ_A : IRR_DcAa<0x01, 0x49, "nez.a">;
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def NOP_sr : ISR_0<0x00, 0x00, "nop">;
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def NOP_sys : ISYS_0<0x00, 0x0D, "nop">;
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defm NOR : mIRR_RC<0x0F, 0x0B, 0x8F, 0x0B, "nor">;
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def NOR_T : IBIT<0x87, 0x02, "nor.t">;
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def NOT_sr : ISR_1<0x46, 0x00, "not">;
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defm OR : mIRR_RC<0x0F, 0x0A, 0x8F, 0x0A, "or">;
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def OR_sc : ISC<0x96, "or">;
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def OR_srr : ISRR<0xA6, "or">;
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let Defs = [PSW], Uses = [PSW] in {
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def SUBCrr : RR<0x0B, 0x0D, (outs DataRegs:$d),
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(ins DataRegs:$s1, DataRegs:$s2),
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@ -1460,21 +1551,21 @@ let Constraints="$d = $s1" in
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def RSUBsr : SR<0x32, 0x05, (outs DataRegs:$d), (ins DataRegs:$s1),
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"rsub $d", [(set DataRegs:$d, (sub (i32 0), DataRegs:$s1)) ]>;
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let Defs=[PSW] in {
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// let Defs=[PSW] in {
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let Constraints="$d = $fksrc" in
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def MULsrr : SRR<0xE2, (outs DataRegs:$d),
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(ins DataRegs:$fksrc, DataRegs:$s2), "mul $d, $s2",
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[(set DataRegs:$d, (mul DataRegs:$fksrc, DataRegs:$s2) )]>;
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// let Constraints="$d = $fksrc" in
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// def MULsrr : SRR<0xE2, (outs DataRegs:$d),
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// (ins DataRegs:$fksrc, DataRegs:$s2), "mul $d, $s2",
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// [(set DataRegs:$d, (mul DataRegs:$fksrc, DataRegs:$s2) )]>;
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def MULrr2 : RR2<0x73, 0x00A, (outs DataRegs:$d),
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(ins DataRegs:$s1, DataRegs:$s2), "mul $d, $s1, $s2",
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[(set DataRegs:$d, (mul DataRegs:$s1, DataRegs:$s2) )]>;
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// def MULrr2 : RR2<0x73, 0x00A, (outs DataRegs:$d),
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// (ins DataRegs:$s1, DataRegs:$s2), "mul $d, $s1, $s2",
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// [(set DataRegs:$d, (mul DataRegs:$s1, DataRegs:$s2) )]>;
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def MULrc : RC<0x53, 0x001, (outs DataRegs:$d),
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(ins DataRegs:$s1, s9imm:$const9), "mul $d, $s1, $const9",
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[(set DataRegs:$d, (mul DataRegs:$s1, immSExt9:$const9) )]>;
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}
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// def MULrc : RC<0x53, 0x001, (outs DataRegs:$d),
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// (ins DataRegs:$s1, s9imm:$const9), "mul $d, $s1, $const9",
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// [(set DataRegs:$d, (mul DataRegs:$s1, immSExt9:$const9) )]>;
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// }
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// Logical Instructions
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multiclass Logical32_0<bits<8> opcode1, string asmstring,
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