mirror of
https://github.com/capstone-engine/capstone.git
synced 2024-11-23 13:39:46 +00:00
add:
- `CALL*` - `CL*` - `CMOV*` - `CMPSWAP_W` - `CRC*` - `CSUB*` - `DEBUG*`
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billow
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f7175332ba
commit
f8c7dc474f
@ -759,7 +759,7 @@ class RRRW<bits<8> op1, bits<3> op2 , dag outs, dag ins, string asmstr,
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//===----------------------------------------------------------------------===//
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// 32-bit SYS Instruction Format: <-|op2|-|s1/d|op1>
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//===----------------------------------------------------------------------===//
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class SYS<bits<8> op1, bits<6> op2 , dag outs, dag ins, string asmstr,
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class SYS<bits<8> op1, bits<6> op2, dag outs, dag ins, string asmstr,
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list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
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bits<4> s1_d;
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@ -303,16 +303,38 @@ class IBinRC_<bits<8> op1, bits<7> op2, string asmstr>
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asmstr # " $d, $s1, $const9", []>;
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/// RR
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/// op D[c], D[a]
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class IUnaryRR_a<bits<8> op1, bits<8> op2, string asmstr>
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: RR<op1, op2, (outs DataRegs:$d), (ins DataRegs:$s1),
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asmstr # " $d, $s1", []>;
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/// op D[c], D[b]
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class IUnaryRR_b<bits<8> op1, bits<8> op2, string asmstr>
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: RR<op1, op2, (outs DataRegs:$d), (ins DataRegs:$s2),
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asmstr # " $d, $s2", []>;
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/// op A[a]
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class IUnaryRR_Aa<bits<8> op1, bits<8> op2, string asmstr>
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: RR<op1, op2, (outs), (ins AddrRegs:$s1),
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asmstr # " $s1", []>;
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/// op E[c], D[a]
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class IUnaryRR_E<bits<8> op1, bits<8> op2, string asmstr>
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: RR<op1, op2, (outs ExtRegs:$d), (ins DataRegs:$s1),
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asmstr # " $d, $s1", []>;
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/// op D[c], D[a], D[b]
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class IBinRR<bits<8> op1, bits<8> op2, string asmstr, SDNode node>
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: RR<op1, op2, (outs DataRegs:$d), (ins DataRegs:$s1, DataRegs:$s2),
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asmstr # " $d, $s1, $s2",
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[(set DataRegs:$d, (node DataRegs:$s1, DataRegs:$s2))]>;
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/// op D[c], D[b], D[a]
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class IBinRR_cba<bits<8> op1, bits<8> op2, string asmstr>
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: RR<op1, op2, (outs DataRegs:$d), (ins DataRegs:$s1, DataRegs:$s2),
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asmstr # " $d, $s2, $s1",
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[]>;
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class IBinRR_<bits<8> op1, bits<8> op2, string asmstr>
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: RR<op1, op2, (outs DataRegs:$d), (ins DataRegs:$s1, DataRegs:$s2),
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asmstr # " $d, $s1, $s2", []>;
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@ -552,19 +574,19 @@ multiclass mIBO_b<bits<8> op11, bits<6> op12,
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def _bo_c : IBO_circular<op21, op22, asmstr>;
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}
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multiclass mIBO_ab<bits<8> op11, bits<6> op12,//_bso
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bits<8> op21, bits<6> op22,//_r
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bits<8> op31, bits<6> op32,//_c
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bits<8> op41, bits<6> op42,//post
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bits<8> op51, bits<6> op52,//pre
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string asmstr>{
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multiclass mIBO_ab<bits<8> op11, bits<6> op12, ///_bso
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bits<8> op21, bits<6> op22, ///_r
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bits<8> op31, bits<6> op32, ///_c
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bits<8> op41, bits<6> op42, ///_post
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bits<8> op51, bits<6> op52, ///_pre
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string asmstr>{
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defm "" : mIBO_a<op11,op12,
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op41,op42,
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op51,op52,
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asmstr>,
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op41,op42,
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op51,op52,
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asmstr>,
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mIBO_b<op21,op22,
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op31,op32,
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asmstr>;
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op31,op32,
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asmstr>;
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}
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/// CACHEA.* Instructions
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@ -645,19 +667,93 @@ def CADDN_rcr : IRCR<0xAB, 0x01, "caddn">;
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def CADDN_rrr : IRRR<0x2B, 0x01, "caddn">;
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def CADDN_src : ISRC_a15<0xCA, "caddn">;
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// Call Instructions
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class IB<bits<8> op1, string asmstr, SDNode node>
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: B<op1, (outs), (ins i32imm:$disp24),
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asmstr # " $disp24", [(node imm:$disp24)]>;
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// The target of a 24-bit call instruction.
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def call_target : Operand<i32> {
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let EncoderMethod = "encodeCallTarget";
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}
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let isCall = 1,
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Defs = [A11],
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Uses = [A10] in {
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def CALL_b : IB<0x6D, "call", TriCoreCall>;
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def CALLA_b : IB<0xED, "calla", TriCoreCall>;
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def CALLI_rr : IUnaryRR_Aa<0x2D, 0x00, "calli">;
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}
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multiclass mI_H<bits<8> op1,bits<8> op2,bits<8> op3,bits<8> op4,
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string asmstr> {
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def _rr : IUnaryRR_a<op1, op2, asmstr>;
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def _H_rr : IUnaryRR_a<op3, op4, asmstr # ".h">;
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}
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defm CLO : mI_H<0x0F, 0x1C, 0x0F, 0x7D, "clo">;
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defm CLS : mI_H<0x0F, 0x1D, 0x0F, 0x7E, "cls">;
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defm CLZ : mI_H<0x0F, 0x1B, 0x0F, 0x7C, "clz">;
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def CMOV_src : ISRC_a15<0xAA, "cmov">;
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def CMOV_srr : ISRR_a15<0x2A, "cmov">;
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def CMOVN_src : ISRC_a15<0xEA, "cmovn">;
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def CMOVN_srr : ISRR_a15<0x6A, "cmovn">;
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defm CMPSWAP_W : mIBO_ab<0x49, 0x23, 0x69, 0x03,
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0x69, 0x13, 0x49,0x03,
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0x49, 0x13, "CMPSWAP.W">;
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def CRC32_B_rr : IBinRR_cba<0x4B, 0x06, "crc32.b">;
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def CRC32B_W_rr : IBinRR_cba<0x4B, 0x03, "crc32b.w">;
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def CRC32L_W_rr : IBinRR_cba<0x4B, 0x07, "crc32l.w">;
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def CRCN_rrr : IRRR<0x6B, 0x01, "crcn">;
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def CSUB_rrr : IRRR<0x2B, 0x02, "csub">;
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def CSUBN_rrr : IRRR<0x2B, 0x03, "csub">;
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class ISR_0<bits<8> op1, bits<4> op2, string asmstr>
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: SR<op1, op2, (outs), (ins),
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asmstr, []>;
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let Constraints = "$s1 = $d" in
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class ISR_1<bits<8> op1, bits<4> op2, string asmstr>
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: SR<op1, op2, (outs DataRegs:$d), (ins DataRegs:$s1),
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asmstr # " $s1", []>;
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class ISYS_0<bits<8> op1, bits<6> op2, string asmstr>
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: SYS<op1, op2, (outs), (ins),
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asmstr, []>;
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class ISYS_1<bits<8> op1, bits<6> op2, string asmstr>
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: SYS<op1, op2, (outs), (ins DataRegs:$s1),
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asmstr # " $s1", []>;
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def DEBUG_sr : ISR_0<0x00, 0x0A, "debug">;
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def DEBUG_sys : ISYS_0<0x0D, 0x04, "debug">;
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// class IRRPW<> : RRPW<>;
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// class IRRRR<> : RRRR<>;
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// class IRRRW<> : RRRW<>;
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// class IRCPW<> : RRPW<>;
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// class IRCRR<> : RRPW<>;
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// class IRCRW<> : RCRW<>;
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// def DEXTR;
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let Defs = [PSW], Uses = [PSW] in {
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def SUBCrr : RR<0x0B, 0x0D, (outs DataRegs:$d),
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(ins DataRegs:$s1, DataRegs:$s2),
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"subc $d, $s1, $s2",
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[(set DataRegs:$d, (subc DataRegs:$s1, DataRegs:$s2)),
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(implicit PSW)]>;
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def SUBCrr : RR<0x0B, 0x0D, (outs DataRegs:$d),
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(ins DataRegs:$s1, DataRegs:$s2),
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"subc $d, $s1, $s2",
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[(set DataRegs:$d, (subc DataRegs:$s1, DataRegs:$s2)),
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(implicit PSW)]>;
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def SUBXrr : RR<0x0B, 0x0C, (outs DataRegs:$d),
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(ins DataRegs:$s1, DataRegs:$s2),
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"subx $d, $s1, $s2",
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[(set DataRegs:$d, (sube DataRegs:$s1, DataRegs:$s2)),
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(implicit PSW)]>;
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def SUBXrr : RR<0x0B, 0x0C, (outs DataRegs:$d),
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(ins DataRegs:$s1, DataRegs:$s2),
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"subx $d, $s1, $s2",
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[(set DataRegs:$d, (sube DataRegs:$s1, DataRegs:$s2)),
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(implicit PSW)]>;
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} // let Defs = [PSW], Uses = [PSW]
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@ -1245,24 +1341,10 @@ let isTerminator = 1, isReturn = 1, isBarrier = 1 in
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// let Inst{15-12} = 0x9;
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// }
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// Call Instructions
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// The target of a 24-bit call instruction.
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def call_target : Operand<i32>
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{
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let EncoderMethod = "encodeCallTarget";
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}
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let isCall = 1, Defs = [A11], Uses = [A10] in
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def CALLb : B<0x6D, (outs), (ins i32imm:$disp24),
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"call $disp24", [(TriCoreCall imm:$disp24)]>;
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def : Pat<(TriCoreCall (i32 tglobaladdr:$dst)),
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(CALLb tglobaladdr:$dst)>;
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(CALL_b tglobaladdr:$dst)>;
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def : Pat<(i32 (TriCoreWrapper tglobaladdr:$dst)),
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(MOVi32 tglobaladdr:$dst)>;
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(MOVi32 tglobaladdr:$dst)>;
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// Tentative Call Instructions
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