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Undefined shifts (#1154)

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* Fix undefined shifts

uint8 gets promoted to signed integer

in ARM, MIPS, Sparc
in AArch64, PPC and Xcore

* fix undefined shift in powerpc

* Fix undefined shift in Mips

use mulitply instead
This commit is contained in:
Catena cyber 2018-06-02 10:49:36 +02:00 committed by Nguyen Anh Quynh
parent e8cb987ead
commit fb798d3f9b
10 changed files with 18 additions and 18 deletions
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2
LEB128.h
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@ -27,7 +27,7 @@ static inline uint64_t decodeULEB128(const uint8_t *p, unsigned *n)
uint64_t Value = 0;
unsigned Shift = 0;
do {
Value += (*p & 0x7f) << Shift;
Value += (uint64_t)(*p & 0x7f) << Shift;
Shift += 7;
} while (*p++ >= 128);
if (n)

2
arch/AArch64/AArch64AddressingModes.h
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@ -198,7 +198,7 @@ static inline float AArch64_AM_getFPImmFloat(unsigned Imm)
// where B = NOT(b);
FPUnion.I = 0;
FPUnion.I |= Sign << 31;
FPUnion.I |= (uint32_t) Sign << 31;
FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
FPUnion.I |= (Exp & 0x3) << 23;

4
arch/AArch64/AArch64Disassembler.c
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@ -240,9 +240,9 @@ static DecodeStatus _getInstruction(cs_struct *ud, MCInst *MI,
if (ud->big_endian)
insn = (code[3] << 0) | (code[2] << 8) |
(code[1] << 16) | (code[0] << 24);
(code[1] << 16) | ((uint32_t) code[0] << 24);
else
insn = (code[3] << 24) | (code[2] << 16) |
insn = ((uint32_t) code[3] << 24) | (code[2] << 16) |
(code[1] << 8) | (code[0] << 0);
// Calling the auto-generated decoder function.

2
arch/ARM/ARMAddressingModes.h
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@ -658,7 +658,7 @@ static inline float getFPImmFloat(unsigned Imm)
// where B = NOT(b);
FPUnion.I = 0;
FPUnion.I |= Sign << 31;
FPUnion.I |= (uint32_t) Sign << 31;
FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
FPUnion.I |= (Exp & 0x3) << 23;

8
arch/ARM/ARMDisassembler.c
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@ -486,9 +486,9 @@ static DecodeStatus _ARM_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t
insn = (code[3] << 0) |
(code[2] << 8) |
(code[1] << 16) |
(code[0] << 24);
((uint32_t) code[0] << 24);
else
insn = (code[3] << 24) |
insn = ((uint32_t) code[3] << 24) |
(code[2] << 16) |
(code[1] << 8) |
(code[0] << 0);
@ -780,11 +780,11 @@ static DecodeStatus _Thumb_getInstruction(cs_struct *ud, MCInst *MI, const uint8
insn32 = (code[3] << 0) |
(code[2] << 8) |
(code[1] << 16) |
(code[0] << 24);
((uint32_t) code[0] << 24);
else
insn32 = (code[3] << 8) |
(code[2] << 0) |
(code[1] << 24) |
((uint32_t) code[1] << 24) |
(code[0] << 16);
MCInst_clear(MI);

8
arch/Mips/MipsDisassembler.c
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@ -391,14 +391,14 @@ static void readInstruction32(unsigned char *code, uint32_t *insn, bool isBigEnd
if (isBigEndian) {
// Encoded as a big-endian 32-bit word in the stream.
*insn =
(code[3] << 0) | (code[2] << 8) | (code[1] << 16) | (code[0] << 24);
(code[3] << 0) | (code[2] << 8) | (code[1] << 16) | ((uint32_t) code[0] << 24);
} else {
if (isMicroMips) {
*insn = (code[2] << 0) | (code[3] << 8) | (code[0] << 16) |
(code[1] << 24);
((uint32_t) code[1] << 24);
} else {
*insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) |
(code[3] << 24);
((uint32_t) code[3] << 24);
}
}
}
@ -1786,7 +1786,7 @@ static DecodeStatus DecodeMovePRegPair(MCInst *Inst, unsigned Insn,
static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, unsigned Insn,
uint64_t Address, MCRegisterInfo *Decoder)
{
MCOperand_CreateImm0(Inst, SignExtend32(Insn, 23) << 2);
MCOperand_CreateImm0(Inst, SignExtend32(Insn, 23) * 4);
return MCDisassembler_Success;
}

4
arch/PowerPC/PPCDisassembler.c
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@ -364,10 +364,10 @@ static DecodeStatus getInstruction(MCInst *MI,
// The instruction is big-endian encoded.
if (MI->csh->mode & CS_MODE_BIG_ENDIAN)
insn = (code[0] << 24) | (code[1] << 16) |
insn = ((uint32_t) code[0] << 24) | (code[1] << 16) |
(code[2] << 8) | (code[3] << 0);
else
insn = (code[3] << 24) | (code[2] << 16) |
insn = ((uint32_t) code[3] << 24) | (code[2] << 16) |
(code[1] << 8) | (code[0] << 0);
if (MI->flat_insn->detail) {

2
arch/PowerPC/PPCInstPrinter.c
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@ -567,7 +567,7 @@ static void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O)
return;
}
imm = MCOperand_getImm(MCInst_getOperand(MI, OpNo)) << 2;
imm = MCOperand_getImm(MCInst_getOperand(MI, OpNo)) * 4;
if (!PPC_abs_branch(MI->csh, MCInst_getOpcode(MI))) {
imm = MI->address + imm;

2
arch/Sparc/SparcDisassembler.c
View File

@ -212,7 +212,7 @@ static DecodeStatus readInstruction32(const uint8_t *code, size_t len, uint32_t
*Insn = (code[3] << 0) |
(code[2] << 8) |
(code[1] << 16) |
(code[0] << 24);
((uint32_t) code[0] << 24);
return MCDisassembler_Success;
}

2
arch/XCore/XCoreDisassembler.c
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@ -50,7 +50,7 @@ static bool readInstruction32(const uint8_t *code, size_t code_len, uint32_t *in
return false;
// Encoded as a little-endian 32-bit word in the stream.
*insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) | (code[3] << 24);
*insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) | ((uint32_t) code[3] << 24);
return true;
}