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x86: add UD0 instruction
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parent
093ebf0646
commit
fcaf7d9a6f
1
MCInst.c
1
MCInst.c
@ -23,6 +23,7 @@ void MCInst_Init(MCInst *inst)
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inst->writeback = false;
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inst->ac_idx = 0;
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inst->popcode_adjust = 0;
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inst->assembly[0] = '\0';
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}
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void MCInst_clear(MCInst *inst)
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1
MCInst.h
1
MCInst.h
@ -108,6 +108,7 @@ struct MCInst {
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// operand access index for list of registers sharing the same access right (for ARM)
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uint8_t ac_idx;
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uint8_t popcode_adjust; // Pseudo X86 instruction adjust
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char assembly[8]; // for special instruction, so that we dont need printer
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};
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void MCInst_Init(MCInst *inst);
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@ -342,8 +342,13 @@ static void _printOperand(MCInst *MI, unsigned OpNo, SStream *O)
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// convert Intel access info to AT&T access info
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static void get_op_access(cs_struct *h, unsigned int id, uint8_t *access, uint64_t *eflags)
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{
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uint8_t *arr = X86_get_op_access(h, id, eflags);
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uint8_t count, i;
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uint8_t *arr = X86_get_op_access(h, id, eflags);
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if (!arr) {
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access[0] = 0;
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return;
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}
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// find the non-zero last entry
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for(count = 0; arr[count]; count++);
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@ -874,6 +879,12 @@ void X86_ATT_printInst(MCInst *MI, SStream *OS, void *info)
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enum cs_ac_type access1, access2;
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int i;
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// perhaps this instruction does not need printer
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if (MI->assembly[0]) {
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strncpy(OS->buffer, MI->assembly, sizeof(MI->assembly));
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return;
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}
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// Output CALLpcrel32 as "callq" in 64-bit mode.
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// In Intel annotation it's always emitted as "call".
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//
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@ -946,6 +946,25 @@ bool X86_getInstruction(csh ud, const uint8_t *code, size_t code_len,
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if (ret) {
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*size = (uint16_t)(insn.readerCursor - address);
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// handle some special cases here.
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// FIXME: fix this in the next major update.
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if (*size == 2) {
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unsigned char b1, b2;
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reader(&info, &b1, address);
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reader(&info, &b2, address + 1);
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if (b1 == 0x0f && b2 == 0xff) {
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instr->OpcodePub = X86_INS_UD0;
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strncpy(instr->assembly, "ud0", 4);
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if (instr->flat_insn->detail) {
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instr->flat_insn->detail->x86.opcode[0] = b1;
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instr->flat_insn->detail->x86.opcode[1] = b2;
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}
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return true;
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}
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return false;
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}
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return false;
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} else {
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@ -453,8 +453,13 @@ static void _printOperand(MCInst *MI, unsigned OpNo, SStream *O)
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static void get_op_access(cs_struct *h, unsigned int id, uint8_t *access, uint64_t *eflags)
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{
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#ifndef CAPSTONE_DIET
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uint8_t *arr = X86_get_op_access(h, id, eflags);
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uint8_t i;
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uint8_t *arr = X86_get_op_access(h, id, eflags);
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if (!arr) {
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access[0] = 0;
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return;
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}
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// copy to access but zero out CS_AC_IGNORE
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for(i = 0; arr[i]; i++) {
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@ -723,6 +728,12 @@ void X86_Intel_printInst(MCInst *MI, SStream *O, void *Info)
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x86_reg reg, reg2;
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enum cs_ac_type access1, access2;
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// perhaps this instruction does not need printer
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if (MI->assembly[0]) {
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strncpy(O->buffer, MI->assembly, sizeof(MI->assembly));
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return;
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}
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// Try to print any aliases first.
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mnem = printAliasInstr(MI, O, Info);
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if (mnem)
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@ -2346,6 +2346,8 @@ static name_map insn_name_maps[] = {
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{ X86_INS_VCMPGE_OQPD, "vcmpge_oqpd" },
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{ X86_INS_VCMPGT_OQPD, "vcmpgt_oqpd" },
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{ X86_INS_VCMPTRUE_USPD, "vcmptrue_uspd" },
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{ X86_INS_UD0, "ud0" },
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};
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#endif
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@ -1894,7 +1894,8 @@ public class X86_const {
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public static final int X86_INS_VCMPGE_OQPD = 1495;
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public static final int X86_INS_VCMPGT_OQPD = 1496;
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public static final int X86_INS_VCMPTRUE_USPD = 1497;
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public static final int X86_INS_ENDING = 1498;
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public static final int X86_INS_UD0 = 1498;
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public static final int X86_INS_ENDING = 1499;
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// Group of X86 instructions
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@ -1891,7 +1891,8 @@ let _X86_INS_VCMPNEQ_OSPD = 1494;;
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let _X86_INS_VCMPGE_OQPD = 1495;;
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let _X86_INS_VCMPGT_OQPD = 1496;;
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let _X86_INS_VCMPTRUE_USPD = 1497;;
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let _X86_INS_ENDING = 1498;;
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let _X86_INS_UD0 = 1498;;
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let _X86_INS_ENDING = 1499;;
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(* Group of X86 instructions *)
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@ -1891,7 +1891,8 @@ X86_INS_VCMPNEQ_OSPD = 1494
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X86_INS_VCMPGE_OQPD = 1495
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X86_INS_VCMPGT_OQPD = 1496
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X86_INS_VCMPTRUE_USPD = 1497
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X86_INS_ENDING = 1498
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X86_INS_UD0 = 1498
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X86_INS_ENDING = 1499
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# Group of X86 instructions
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@ -1836,6 +1836,8 @@ typedef enum x86_insn {
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X86_INS_VCMPGT_OQPD,
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X86_INS_VCMPTRUE_USPD,
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X86_INS_UD0,
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X86_INS_ENDING, // mark the end of the list of insn
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} x86_insn;
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