Commit Graph

1850 Commits

Author SHA1 Message Date
Rot127
7d01d7e7a9
Auto-Sync reproducability + ARM update (#2532)
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2024-11-22 00:31:27 +08:00
billow
abbf32b431
fix coverity (#2546)
- cid 514642

- cid 514643

- cid 514644

- cid 514645
2024-11-13 22:05:18 +08:00
billow
1ecfb5b042
xtensa: update to espressif/llvm-project (#2533)
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2024-11-10 21:55:40 +08:00
billow
f6f967961b
tricore: fixes #2474 (#2523)
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* tricore: fix auto-sync tricore

* tricore: fixes TriCoreGenCSMappingInsnName.inc

* tricore: fixes

* tricore: try fix ld.a SC

* tricore: fixes all

* Add TriCore to .github/workflows/auto-sync.yaml

* Add TriCore details tests(a15, d15, a10|sp)
2024-11-01 17:30:42 +08:00
Rot127
306d5716d8
Fix endianess issue during assignment. (#2528)
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2024-10-28 16:12:25 +08:00
Rot127
5026c2c4e9
Merge pull request #2507 from thestr4ng3r/no-varargs-aarch64
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AArch64: Replace vararg add_cs_detail by multiple concrete functions
2024-10-22 13:11:33 +00:00
billow
f97e2705da
xtensa: Fix Branch Target (#2516)
* xtensa: Fix Branch Target

* auto-sync: fix byte pattern

* xtensa: add branch insn tests

* Revert "auto-sync: fix byte pattern"

This reverts commit cf8e870f77.
2024-10-22 16:20:37 +08:00
Florian Märkl
1d13a12fbc AArch64: Replace vararg add_cs_detail by multiple concrete functions
Fixes UB caused by various mismatches on how these arguments are passed
and read. This became visible when running on PowerPC hosts with e.g.
`cstool -d aarch64 204862f8`.
Apart from the UB fix, this is meant to be a pure refactor.

Partially addresses #2458
2024-10-21 22:03:00 +02:00
Rot127
ea081286bc
Tricore EA calculation (#2504) 2024-10-19 12:05:02 +08:00
Rot127
52b54ee32d
Fixing UB santizer, LITBASE and assert errors. (#2499)
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2024-10-06 08:45:13 +08:00
Rot127
5dffa75bdb
Fix LDR not assigning immediate as memory offset. (#2487)
See: https://github.com/capstone-engine/capstone/issues/2015#issuecomment-2373660217
2024-09-30 17:31:34 +08:00
billow
21f7bc85f9
Xtensa Support (#2380)
* Fix leaks

* Remove unnecessary new lines

* Add checks for actual buffer length before attempting reading it.

* Xtensa: add xtensa support

* Xtensa fixes

- fix MCExpr
- fix Xtensa_add_cs_detail
- add `add_cs_detail`
- add `MCExpr *MCOperand_getExpr(const MCOperand *MC)` `void printExpr(const MCExpr *E, SStream *O)`

autosync fix

- fix StreamOperation.py
- replace `report_fatal_error` with `CS_ASSERT`
- fix patch StreamOperation.py
- replace `assert` with `CS_ASSERT`
- fix AddCSDetail.py
- fix QualifiedIdentifier

* Xtensa fix

* Xtensa fix .py

* add Xtensa to the fuzzer

* Xtensa `LITBASE`: add a basic implementation

* Xtensa `LITBASE`: add a integration test

* Xtensa: fix cs_v6_release_guide.md

* Xtensa: fix `XTENSA_OP_GROUP_MEMOPERAND`

* Xtensa: fix

* Xtensa: fix Targets.py

* Use isUint and isInt all over Xtensa

* Add documentation about LITBASE functionality

* Fix typo

* Replace hard with Capstone assert

* Xtensa: fix arch_config.json

* Xtensa: fix

---------

Co-authored-by: Rot127 <unisono@quyllur.org>
2024-09-30 11:35:51 +08:00
Rot127
29d8773417
Several small fixups (#2489)
* Remove internal code from API

* Fix compatibility headers and test the generation of them

* Cancel all previous test workflows on new push.

* Add valgrind test
2024-09-30 11:33:31 +08:00
Giovanni
3120932d9e
Fix Coverity CID 509730: overflow before widen (#2486) 2024-09-25 15:34:48 +08:00
Rot127
1014864d3f
Rename CS_OPT_NO_BRANCH_OFFSET and corresponding flag to better name. (#2482) 2024-09-25 15:33:45 +08:00
Rot127
0c90fe13f5
Replace assert with CS_ASSERT in modules (#2478)
* Replace asserts with macros for AArch64, Alpha, LoongArch, Mips, SystemZ inc files.

* Add missing clearing of MCInst

* Ensure correct dir name is used.

* Replace asserts in inc files for PPC, ARM, TriCore

* Replace all asserts in modules with CS_ASSERT.

Also enable the CS_ASSERTs if CMAKE_BUILD_TYPE=Debug

* Formatting
2024-09-25 14:58:06 +08:00
Rot127
823bfd53e3
AArch64 issues (#2473)
* Fix Pn was printed as register, not predicate.

* Fix: is_alias must be an int to allow for -1 as false.

* Fix, shift immediate was casted to incorrect width.

* Store theexact float also in fp field for convenience.

* Fix: MRS has no implicit write of NCVZ

* Fix signs of Imm8 shifted operands.

* Fix another MRS test

* Fix: Src operand of CASAL had write flag set.

* Fix sysop access in Python data structures.
2024-09-24 12:32:10 +08:00
Rot127
5430745e96
ARM fixes (#2477)
* Fix #2381

* Fix #2382

* Fix post-index correction only for pop with single register

* Fix missing memory index register scale

* Remove faulty and duplicated lshift field.

* Add shift information to shift alias instructions and add several tests.

* Fix scale tests

---------

Co-authored-by: Wu ChenXu <kabeor00@gmail.com>
2024-09-23 11:30:33 +08:00
Giovanni
e9b9b649cd
Fix jumps and branches on a non-zero PC (#2479)
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* Fix ASAN shift runtime check

* Fix jumps and branches addresses when applying a PC address

* Add tests for branches and jumps
2024-09-19 22:41:46 +08:00
david942j
10db5f4f8c
[next][SuperH] Fix missing setting detail->sh (#2466)
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* [next][SuperH] Fix missing setting detail->sh

detail->sh is never set. Which makes the detailed output related to operands is always missing.

Signed-off-by: david942j <david942j@gmail.com>

* Fix merge commit

---------

Signed-off-by: david942j <david942j@gmail.com>
2024-09-19 19:03:29 +08:00
Lucas Azevedo
67d975662e
[next] SH: Use bitwise OR with mask for sign extension (#2389)
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* Use bitwise OR with mask for sign extension

Sign extend using bitwise OR with mask, instead of unary minus.
Fixes error when building for UWP with Security Development Lifecycle (SDL).
See https://learn.microsoft.com/en-us/cpp/build/reference/sdl-enable-additional-security-checks?view=msvc-170

* Remove unused store

Remove unused store caught by clang-tidy.

* Suppress clang-tidy false positive

Ignore an unitialized va_list false positive emitted by clang-tidy

---------

Co-authored-by: Wu ChenXu <kabeor00@gmail.com>
2024-09-19 01:09:54 +08:00
Rot127
3a2cd3c331
Coverity defects (#2469)
* Fix CID 508418 - Uninitialized struct

* Fix CID 509089 - Fix OOB read and write

* Fix CID 509088 - OOB.

Also adds tests and to ensure no OOB access.

* Fix CID 509085 - Resource leak.

* Fix CID 508414 and companions - Using undefined values.

* Fix CID 508405 - Use of uninitialized value

* Remove unnecessary and badly implemented dev fuzz code.

* Fix CID 508396 - Uninitialzied variable.

* Fix CID 508393, 508365 -- OOB read.

* Fix CID 432207 - OVerlapping memory access.

* Remove unused functions

* Fix CID 432170 - Overlapping memory access.

* Fix CID 166022 - Check for negative index

* Let strncat not depend n src operand.

* Fix 509083 and 509084 - NULL dereference

* Remove duplicated code.

* Initialize sysop

* Fix resource leak

* Remove unreachable code.

* Remove duplicate code.

* Add assert to check return value of cmoack

* Fixed: d should be a signed value, since it is checked against < 0

* Add missing break.

* Add NULL check

* Fix signs of binary search comparisons.

* Add explicit cast of or result

* Fix correct scope of case.

* Handle invalid integer type.

* Return UINT_MAX instead of implicitly casted -1

* Remove dead code

* Fix type of im

* Fix type of d

* Remove duplicated code.

* Add returns after CS_ASSERTS

* Check for len == 0 case.

* Ensure shift operates on uint64

* Replace strcpy with strncpy.

* Handle edge cases for 32bit rotate

* Fix some out of enum warnings

* Replace a strcpy with strncpy.

* Fix increment of address

* Skip some linting

* Fix: set instruction id

* Remove unused enum

* Replace the last usages of strcpy with SStream functions.

* Increase number of allowed AArch64 operands.

* Check safety of incrementing t the next operand.

* Fix naming of operand

* Update python constants

* Fix option setup of CS_OPT_DETAIL_REAL

* Document DETAIL_REAL has to be used with CS_OPT_ON.

* Run Coverity scan every Monday.

* Remove dead code

* Fix OOB read

* Rename macro to reflect it is only used with sstreams

* Fix rebase issues
2024-09-18 21:19:42 +08:00
Rot127
af1ed2fb3d
SystemZ Auto-Sync refactor (#2462)
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2024-09-14 16:57:54 +08:00
Giovanni
6a7fef60ea
Auto-Sync Mips (#2410) 2024-09-07 22:30:47 +08:00
Giovanni
e6da49d549
Some small fixes for capstone-next (#2460) 2024-09-03 09:22:47 +08:00
Rot127
191db14531
Modern Testing (#2456) 2024-08-31 21:33:38 +08:00
david942j
4c629d9be1
[next] Fix unintended zero set in Sparc printInst (#2421) 2024-08-04 18:46:43 +08:00
Sahil Siddiq
4f964a264e
Fix incorrect operand in disassembled instruction (#2401) (#2403)
Disassembling the "slwi", "srwi" and "rldicr" PowerPC instructions
with the "-d" option displays the wrong operands in the detailed
view. This is due to an incorrect break condition in the
"PPC_insert_detail_op_imm_at" function.

This patch fixes #2401.
2024-07-24 14:19:39 +08:00
Richard Henderson
de5120ed0c
Constify three ARM and AArch64 variables (#2399)
* arm: Constify arm_flag_regs

* aarch64: Constify aarch64_flag_regs and aarch64_flag_sys_regs
2024-07-16 17:20:10 +08:00
wxrdnx
404912f068
Add access support for RISC-V (#2393)
* resolve conflict for loongarch and RISCV in Mapping.c and Mapping.h

* Use RISCV_get_detail for simplicity

Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com>

* Use detail_is_set for simplicity

Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com>

* Change comment style

Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com>

* remove redundant add_str

* fix bug for RISCV_add_detail

* fix operands for csr instructions

* add python binding and tester for RISC-V

* add more test cases for RISC-V (M,A,F,D,C instructions)

* fix incorrect operand and access for sc.w and sc.d

* fix incorrect operand for fence and sfence.vma

* assert -> CS_ASSERT

* some instructions in test_riscv.c should be RISCV64

* add cs details test

* update python testers

---------

Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com>
2024-07-10 11:36:39 +08:00
Rot127
9c5b48b57f
AArch64 update to LLVM 18 (#2298)
* Run clang-format

* Remove arm.h header from AArch64 files

* Update all AArch64 module files to LLVM-18.

* Add check if the differs save file is up-to-date with the current files.

* Add new generator for MC test trnaslation.

* Fix warnings

* Update generated AsmWriter files

* Remove unused variable

* Change MCPhysReg type to int16_t as LLVM 18 dictates.

With LLVM 18 the MCPhysReg value's type is changed to int16_t.
If we update modules to LLVM 18, they will generate
compiler warnings that uint16_t* should not be casted to int16_t*.

This makes changing the all tables to int16_t necessary, because the alternative is
to duplicate all MCPhysReg related code. Which is even worse.

* Assign enum values to raw_struct member

* Add printAdrAdrpLabel def

* Add header to regression test files.

* Write files to build dir and ignore more parsing errors.

* Fix parsing of MC test files.

* Reset parser after every block

* Add write and patch header step.

* Add and update MC tests for AArch64

* Fix clang-tidy warnings

* Don't warn about padding issues.

They break automatically initialized structs we can not change easily.

* Fix: Incorrect access of LLVM instruction descriptions.

* Initialize DecoderComplete flag

* Add more mapping and flag details

* Add function to get MCInstDesc from table

* Fix incorrect memory operand access types.

* Fix test where memory was not written, ut only read.

* Attempt to fix Windows build

* Fix 2268

The enum values were different and hence lead to different decoding.

* Refactor SME operands.

- Splits SME operands in Matrix and Predicate operands.
- Fixes general problems of incorrect detections with
the vector select/index operands of predicate registers.
- Simplifies code.

* Fix up typo in WRITE

* Print actual path to struct fields

* Add Registers of SME operands to the reg-read list

* Add tests for SME operands.

* Use Capstone reg enum for comparison

* Fix tests: 'Vector arra...' to 'operands[x].vas'

* Add the developer fuzz option.

* Fix Python bindings for SME operands

* Fix variable shadowing.

* Fix clang-tidy warnings

* Add missing break.

* Fix varg usage

* Brackets for case

* Handle AArch64_OP_GROUP_AdrAdrpLabel

* Fix endian issue with fuzzing start bytes

* Move previous sme.pred to it's own operand type.

* Fix calculation for imm ranges

* Print list member flag

* Fix up operand strings for cstest

* Do only a shallow clone of the cmocka stable branch

* Fix: Don't categorize ZT0 as a SME matrix operand.

* Remove unused code.

* Add flag to distinguish Vn and Qn registers.

* Add all registers to detail struct, even if emitted in the asm text

* Fix: Increment op count after each list member is added.

* Remove implicit write to NZCV for MSR Imm instructions.

* Handle several alias operands.

* Add details for zero alias with za0.h

* Add SME tile to write list if written

* Add write access flags to operands which are zeroed.

* Add SME tests of #2285

* Fix tests with latest syntax changes.

* Fix segfault if memory operand is only a label without register.

* Fix python bindings

* Attempt to fix clang-tidy warning for some configurations.

* Add missing test file (accidentially blocked by gitignore.)

* Print clang-tidy version before linting.

* Update differ save file

* Formatting

* Use clang-tidy-15 as if possible.

* Remove search patterns for MC tests, since they need to be reworked anyways.

* Enum to upper case change

* Add information to read the OSS fuzz result.

* Fix special case of SVE2 operands.

Apparently ZT0 registers can an index attached,
get which is BOUND to it. We have no "index for reg" field.
So it is simply saved as an immediate.

* Handle LLVM expressions without asserts.

* Ensure choices are always saved.

* OP_GROUP enums can't be all upper case because they contain type information.

* Fix compatibility header patching

* Update saved_choices.json

* Allow mode == None in test_corpus
2024-07-08 10:28:54 +08:00
Chen
95966a1393
Initial auto-sync LoongArch support (#2349)
* Initial auto-sync LoongArch support

- Accompanied llvm changes: https://github.com/capstone-engine/llvm-capstone/pull/45
- MC Tests are generated from llvm
- Instruction groups are implemented
- Register accesses are implemented
- Memory operands are handled for memory instructions
- Code are formatted using clang-format of LLVM 17
- Import tests from LLVM MC
- Collect operand type and access
- Collect registers read/modified
---------
Co-authored-by: CoA <1109673069@qq.com>

* Ensure same indent for all patched lines.
* Emit upper case OP_GROUP enum
* Spell all enum values in capital letters.
* Capticalize enums in loongarch_detail.c
* Add test which contains now a tab.
* Run clang-format on test_loongarch.c
---------
Co-authored-by: CoA <1109673069@qq.com>
Co-authored-by: Rot127 <unisono@quyllur.org>
2024-06-26 14:47:44 +08:00
RainRat
33f24cd074
fix typos (#2387) 2024-06-19 18:54:05 +08:00
Rot127
0a67596f70
Add test with ASAN enabled. (#2313)
* Add test with ASAN enabled.

* Fix leaks in cstool and cs.c

* Add work around so ASAN binaries don't DEADSIGNAL due to too many randomized address bits.

* Add ASAN build arguments to cstest

* Fix leaks in cstest

* Use cstest binary build by the main build.

* Add clonging step for cmocka when cstest is build

* Skip Python tests for ASAN

* Remove make build from CI

* Fix leaks in cstest.

- Rewrite split to remove leaks and improve runtime by 6%
- Add free()

* Fix cmocka external project to stable branch.

* Revert "Fix leaks in cstest."

This reverts commit bf8ee125b0c58f9c794eb081a69c80f8a71825cd.

* Fix memleaks in cstest

* Document adding of ASAN job to release guide

* Add CAPSTONE_BUILD_CSTEST to build docs

* Fix double free

* Add more detail tests to CI and fix them

* Initialize variables

* Fix typo

* Update cstest build docs

* Revert "Remove make build from CI"

This reverts commit 84f7360c6da6183cd41bec0fef3e1d0a2ee49ddf.

* Make cstest only run for cmake builds.

* Add cstest job for make build.

* Add CAPSTONE_DIET build test.

* Compile the compatibility header test with ASAN if enabled.

* Fix DIET build by excluding not used code.

* Missing "

* Build static library with ASAN and DIET if enabled.

* Revert "Add CAPSTONE_DIET build test."

This reverts commit 71e1469dee.
2024-06-10 10:01:00 +08:00
Rot127
3a6331b4c2
Fix Warning C4098: void returns value. (#2362) 2024-05-31 20:02:03 +08:00
Rot127
5f11d3c1fe
Typo and tree-sitter init fix (#2358) 2024-05-16 20:31:44 +08:00
Florian Märkl
2ef45f2a73
Replace non-standard 0b(...) literals (#2314)
Despite being widely implemented and part of C++, the 0b prefix is not
part of any C standard and will be rejected by some compilers such as
Apple GCC 4.0.1 (5493).
2024-05-12 21:19:11 +08:00
RainRat
972bd066bb
fix typos (#2346)
* fix typos

* fix typos

* fix typos
2024-05-12 21:17:20 +08:00
RainRat
b91c727481
fix typos (#2344) 2024-04-30 10:37:53 +08:00
Rot127
b2d5b43ed2
Fix #2079 via the post-printer. (#2330) 2024-04-30 10:35:40 +08:00
Rot127
514b8fca9c
Fix #2128 by adding missing mapping values. (#2335) 2024-04-26 15:12:42 +08:00
Rot127
6c7b54817f
Add a clang-tidy checks and warnings (#2312) 2024-04-26 15:11:46 +08:00
Shuyi Cheng
c4d0993071
Add eBPF bswap16/32/64 instruction (#2323) 2024-04-23 22:04:37 +08:00
Ced2911
e9284b6b36
check if decode[idx] is callable (#2322) 2024-04-23 21:58:40 +08:00
careworry
16017d5f92
chore: remove repetitive words (#2326)
Signed-off-by: careworry <worrycare@outlook.com>

chore: remove repetitive words
2024-04-22 11:57:11 +08:00
R3v0LT
a5cf15e556
HPPA dissassembler fix unitialized variables errors (#2309) 2024-04-10 13:49:43 +08:00
R3v0LT
cda40c6537
Fix invalid comparison with HPPA_OP_INVALID (#2300) 2024-03-29 16:46:00 +08:00
R3v0LT
9daa1ffbac
Add HPPA(PA-RISC) architecture (#2265)
* Refactor HPPA

* Add full HPPA 1.1 instructions support

* Add HPPA 1.1 cs tests

* Fix HPPA dissassembler

* Add HPPA 2.0 instructions

* Add HPPA tests

* Fix HPPA disasm & printer

* Update HPPA tests

* Remove unused code

* Add implicit register access info & Refactor HPPA main files

* Add python bindings/tests and cstests

* Fix HPPA disasm wrong decoding

* Rewrite invalid test cases

* Update HPPA python constants

* Make HPPA python test executable

* Change HPPA python tests sequence to match c tests

* Refactor HPPA main files

* Write target instead of offset in details

* Add HPPA detail function support in cstest

* Rewrite targets in branch tests

* Make correct string modifier addition

* Add hppa test calls

* Add zero operands check

* Remove MCOperand array

* Change immediate values printing

* Add HPPA 2.0 wide support

* Fix invalid break instruction decode

Remove unused code

* Add HPPA to fuzzing tests

* Add HPPA to options

* Add HPPA to docs

* Refactor HPPA

* Fix invalid branch insn decoding

* Add HPPA to labeler

* clang-format hppa files

* Document internal structures and minor refactoring

* Add missing default statements

* Fix invalid default statement
2024-03-26 13:58:56 +08:00
Yudi Zheng
5d9942d13f
Avoid random access values for operands in not-yet-specified instructions. (#2259) 2024-03-21 13:33:30 +08:00
Rot127
b4fde983de
[PPC] Expose instruction formats (#2276)
* Expose PPC formats in PPC details

* Add PPC format note in v6 release guide.

* Update python bindings
2024-02-23 13:20:46 +08:00