* Remove Windows msvc project files and move build instructions to single BUILDING.md file.
* Move HACK.txt to Contributing and update it.
* Add refactoring guide.
* Add known bugs
* Remove compatibility headers.
* Fix smaller issues.
* Remove 'possible revert' column. People always can do manual changes.
* Move instruction alias description to the top
* Add table to general breaking changes.
* Update general release guide with the newest information.
* Highlight NanoMips and be more precise in writing.
* Add note about archs without alias.
* Add sentence about what is planned.
* Small corrections for Windows build instructions and debug macros.
* Fix rebase issues.
* Bring back make.sh for the CI
Run Test / ${{ matrix.config.name }} (map[arch:x64 build-system:make diet-build:OFF enable-asan:OFF name:ubuntu-22.04 x64 make os:ubuntu-22.04]) (push) Failing after 0s
Run Test / ${{ matrix.config.name }} (map[arch:x64 build-system:cmake diet-build:OFF enable-asan:ON name:ubuntu-24.04 x64 ASAN os:ubuntu-24.04]) (push) Has been cancelled
Run Test / ${{ matrix.config.name }} (map[arch:x64 name:windows x64 MSVC 64bit os:windows-latest platform:windows python-arch:x64 python-version:3.9]) (push) Has been cancelled
* Constify registerinfo.py output
Remove two conditionals separating identical bits of code.
Add "const" markup to MCRegisterDesc and MCRegisterClass.
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify instrinfo-arch.py output
In this case, do not actively strip const.
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the AArch64 backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the EVM backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify M680X backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify M68K backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the Mips backend
The Mips backend has not been regenerated from LLVM recently,
and there are more fixups required than I'd like. Just apply
the fixes to the tables by hand for now.
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the Sparc backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the TMS320C64x backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the X86 backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the XCore backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify systemregister.py output
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the ARM backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the PowerPC backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the MOS65XX backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the SystemZ backend
The mapping of system register to indexes is easy to
generate read-only. Since we know the indexes are
between 0 and 31, use uint8_t instead of unsigned.
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the WASM backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify cs.c
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the BPF backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Fix user data alignment in MEMBLOCK
Kernel memory allocations on Windows should be aligned on MEMORY_ALLOCATION_ALIGNMENT (16 bytes on x64 and 8 bytes on x86).
* Fix user data alignment in CS_WINKERNEL_MEMBLOCK
* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h
* Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction
* Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h
* Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter
* Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h
* Backport it from: 0db412ce3b
* All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly.
* Add refactored cs.c for RISCV
* Testing all I instructions in test_riscv.c
* Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture
* Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c
* fixed bug related to incorrect initialization of memory after malloc
* fix compile bug
* Fix compile errors.
* move riscv.h to include/capstone
* fix indentation issues
* fix coding style issues
* Fix indentation issues
* fix coding style
* Move variable declaration to the top of the block
* Fix coding indentation
* Move some stuff into RISCVMappingInsn.inc
* Fix code sytle
* remove cs_mode support for RISCV
* update asmwriter-inc to LLVM upstream
* update the .inc files to riscv upstream
* update riscv disassembler function for suport 16bit instructions
* update printer & tablegen inc files which have fixed arguments mismatch
* update headers and mapping source
* add riscv architecture specific test code
* fix all RISCV tons of compiler errors
* pass final tests
* add riscv tablegen patchs
* merge with upstream/next
* fix cstool missing riscv file
* fix root Makefile
* add new TableGen patchs for riscv
* fix cmakefile.txt of missing one riscv file
* fix declaration conflict
* fix incompatible declaration type
* change riscvc from arch to mode
* fix test_riscv warnning
* fix code style and add riscv part of test_basic
* add RISCV64 mode
* add suite for riscv
* crack fuzz test
* fix getfeaturebits test add riscvc
* fix test missing const qualifier warnning
* fix testcase type mismatch
* fix return value missing
* change getfeaturebits test
* add test cs files
* using a winder type contain the decode string
* fix a copy typo
* remove useless mode for riscv
* change cs file blank type
* add repo for update_riscv & fix cstool missing riscv mode
* fix typo
* add riscv for cstool useage
* add TableGen patch for riscv asmwriter
* clean ctags file
* remove black comment line
* fix fuzz related something
* fix missing RISCV string of fuzz
* update readme, etc..
* add riscv *.s.cs file
* add riscv *.s.cs file & clear ctags
* clear useless array declarations at capstone_test
* update to 5e4069f
* update readme change name more formal
* change position of riscv after bpf and modify copyright more uniform
* clear useless ctags file
* change blank with tab in riscv.h
* add riscv python bindings
* add riscv in __init__.py
* fix riscv define value for python binding
* fix test_riscv.py typo
* add missing riscvc in __init__.py of python bindings
* fix alias-insn printer bug, remove useless newline
* change inst print delimter from tab to bankspace for travis
* add riscv tablegen patch
* fix inst output more consistency
* add TableGen patch which fix inst output formal
* crack the effective address output for detail and change register print function
* fix not detail crash bug
* change item declaration position at cs_riscv
* update riscv.py
* change function name more meaningfull
* update python binding makefile
* fix register enum sequence according to riscvgenreginfo.inc
* test function name
* add enum s0/fp in riscv.h & update riscv_const.py
* add register name enum
* provide a validity check to prevent against Integer overflow conditions
* fix some style issues.
* provide a validity check in malloc() function to prevent against integer overflow conditions
* missing Ntintsafe.h
* use tabs for indentation
