Commit Graph

3802 Commits

Author SHA1 Message Date
Riccardo Schirone
c316ef189d arch/M68k: do not return reg_name if beyond limits (#1219)
* arch/M68k: do not return reg_name if beyond limits

(patch coming from radare2)

* arch: checks index when returning reg names
2018-07-24 16:25:47 +08:00
Nguyen Anh Quynh
af286d4914 sparc: fix issue #1221 on double printing imm operand 2018-07-24 14:53:00 +08:00
Riccardo Schirone
60616a6175 cstool: fix memleak to prevent ASAN from complaining (#1222) 2018-07-24 10:19:07 +08:00
Nguyen Anh Quynh
cdf269e020 fix warnings on const char * discards qualifiers 2018-07-24 01:41:59 +08:00
Nguyen Anh Quynh
d601b8971c Merge branch 'v4' 2018-07-23 21:20:46 +08:00
Francesco Tamagni
f6e0fa42f2 Fix testAndBranch sign extend to 64 bit (#1213) 2018-07-20 14:50:41 +08:00
Nguyen Anh Quynh
76c1c3c4e9 merge next to master 2018-07-20 12:36:50 +08:00
Nguyen Anh Quynh
91918b2608 ChangeLog 2018-07-19 00:17:10 +08:00
Nguyen Anh Quynh
9783ea8585 mips: compilable for MSVC 2013 2018-07-18 23:47:07 +08:00
Nguyen Anh Quynh
d64cfab1d8 mips: compilable for MSVC 2013 2018-07-18 23:46:36 +08:00
Nguyen Anh Quynh
d739e3f5bd ChangeLog 2018-07-18 13:48:32 +08:00
Nguyen Anh Quynh
377ededee7 python: raise CsError(CS_ERR_SKIPDATA) when accessing irrelevant data in skipdata mode. this fixes issue #679 2018-07-18 13:43:32 +08:00
Nguyen Anh Quynh
a1ccc8ebda python: raise CsError(CS_ERR_SKIPDATA) when accessing irrelevant data in skipdata mode. this fixes issue #679 2018-07-18 13:37:45 +08:00
Nguyen Anh Quynh
90963c0cb1 ChangeLog for v3.0.5 2018-07-17 15:59:51 +08:00
Nguyen Anh Quynh
9c4427d5d8 change PKG_TAG for v3.0.5 2018-07-17 15:30:42 +08:00
keenk
7bdf7dfefa Update TestX86.java (#1208)
* Fix java bindings for encoding

Fix java bindings broken with addition of encoding struct in #1194

* Add files via upload


Update TestX86.java for printing encoding struct and register access

* Add files via upload

Added conditions to only print encoding class info when needed.
Formatting.

* Add files via upload

Another space
2018-07-13 15:52:19 +07:00
clslgrnc
91601ac1fd Init cs_detail (#1205)
* Update init of cs_detail for AArch64

as @aquynh requested in #1125

* Update init of cs_detail for ARM

as @aquynh requested in #1125

* Update init of cs_detail for EVM

as @aquynh requested in #1125

* Update init of cs_detail for M680X

as @aquynh requested in #1125

* Update init of cs_detail for M68K

as @aquynh requested in #1125

* Update init of cs_detail for Mips

as @aquynh requested in #1125

* Update init of cs_detail for PowerPC

as @aquynh requested in #1125

* Update init of cs_detail for Sparc

as @aquynh requested in #1125

* Update init of cs_detail for SystemZ

as @aquynh requested in #1125

* Update init of cs_detail for TMS320C64x

as @aquynh requested in #1125

* Update init of cs_detail for XCore

as @aquynh requested in #1125

* Comment on init of cs_detail

* wrap long lines
2018-07-12 11:01:34 +07:00
Nguyen Anh Quynh
8171df5568 x86: fix imm operand of RETF. see #1204 2018-07-11 23:20:00 +08:00
Martin
ec81ee223b readDisplacement fix (#1200) 2018-07-11 23:19:45 +08:00
Martin
bd89989f5d readDisplacement fix (#1200) 2018-07-11 22:18:38 +07:00
Nguyen Anh Quynh
7e93de0714 x86: fix imm operand of RETF. see #1204 2018-07-11 23:12:18 +08:00
keenk
8596aa5b99 Fix java bindings for encoding (#1202)
Fix java bindings broken with addition of encoding struct in #1194
2018-07-09 08:26:33 +07:00
Nguyen Anh Quynh
940cbdcfea Merge branch 'next' of github.com:aquynh/capstone into next 2018-07-05 11:34:32 +08:00
Nguyen Anh Quynh
68d4e771eb evm: default case for switch 2018-07-05 11:33:39 +08:00
Nguyen Anh Quynh
5c173ca0cd evm: cleanup group_name_maps[] 2018-07-05 11:32:42 +08:00
Nguyen Anh Quynh
ec57c1b4ec evm: fix bug introduced in some recent fixes 2018-07-05 11:32:19 +08:00
Nguyen Anh Quynh
76a86e5354 evm: cleanup 2018-07-05 11:32:05 +08:00
Nguyen Anh Quynh
6c4ece4472 evm: simplify EVM_get_insn_id() 2018-07-05 11:31:53 +08:00
Nguyen Anh Quynh
3a3cff2e91 evm: correct comments on evm_insn_find() 2018-07-05 11:31:39 +08:00
Nguyen Anh Quynh
dfb75a21a0 evm: fix header guard in EVMModule.c 2018-07-05 01:16:24 +08:00
Nguyen Anh Quynh
97f34c87c7 x86: X86_immediate_size() returns uint8 2018-07-04 23:02:22 +08:00
Nguyen Anh Quynh
795ffa39e7 coding style 2018-07-04 22:54:14 +08:00
Nguyen Anh Quynh
5e153a2130 CREDITS.TXT 2018-07-04 22:50:28 +08:00
Stephen Eckels
e9861a1192 Merges encoding to next (#1194)
* merge encoding branch into next branch

* added python bindings and updated test to support encoding

* fix python import

* fix py binding fields

* fix disp size printing

* fixed py binding, again

* Update CREDITS.TXT

* fixed formatting and a cast

* Changed param from int to uint8_t, fixed warnings
2018-07-04 22:47:55 +08:00
Nguyen Anh Quynh
1036de09bf Revert "Merges encoding branch (#1187)"
This reverts commit a1ed8fc6f6.
2018-07-03 11:55:29 +08:00
Catena cyber
e14b4c4b11 Initializes to 0 X86 immediateOffset (#1192) 2018-06-29 17:00:51 +08:00
Catena cyber
b1f2f1a394 Initializes to 0 X86 immediateOffset (#1192) 2018-06-29 16:59:30 +08:00
Stephen Eckels
699611072b Merges encoding branch (#1187)
* Added encoding field to instructions, as per encoding branch

The encoding branch appears to have added some useful fields
accessible from the public API, including the size and offsets
of displacements and immediates in instructions.  I needed access
to these fields, but the encoding branch is months behind the
active branches, so I took the minimum code from the old encoding
branch and put them into a more recent version of master.

It does seem that the most recent version does not have an offset
for the modRM byte in the InternalInstruction struct, so I did
not keep this field when bringing it to the more recent version.

I also added some of the changes made by user jellever, who added
support for accessing these new fields from the python bindings.

(cherry picked from commit d358c4b987cc77af90e24da15937e021c42f682f)

* Fixed bug with python bindings from adding encoding field

I had forgotten an import that resulted in failure when trying
to obtain instruction details.

(cherry picked from commit 44a15e378900efb624e7cdb952d32558ba0de684)

* promoted displacement to 64 bits

* Added modrm offset

* formatting from review fixed

* updated 32 bit C tests

* Added 64 and 16 bit C tests

* Updated python tests

* fixed formatting and size in py bindings

* Delete Solution.VC.db-shm

* Delete Solution.VC.db-wal

* Update test_x86.c

* fixed formatting and conditional prints

* fixed formatting
2018-06-28 21:37:34 +08:00
Nguyen Anh Quynh
162c984437 CREDITS.TXT 2018-06-25 19:57:50 +08:00
Catena cyber
8ccaab5f79 Better error reporting for python binding (#1189) 2018-06-25 19:48:02 +08:00
Catena cyber
950476606b Initialize X86 necessaryPrefixLocation (#1179)
* Initialize X86 necessaryPrefixLocation

* necessaryPrefixLocation initialization to -1

* Revert "necessaryPrefixLocation initialization to -1"

This reverts commit 04fc4b6702.
2018-06-25 19:46:58 +08:00
Catena cyber
27a169e305 Initialize X86 necessaryPrefixLocation (#1179)
* Initialize X86 necessaryPrefixLocation

* necessaryPrefixLocation initialization to -1

* Revert "necessaryPrefixLocation initialization to -1"

This reverts commit 04fc4b6702.
2018-06-25 19:46:04 +08:00
Catena cyber
154c9ffdd8 Better error reporting for python binding (#1188)
To diagnose issue with oss-fuzz building corpus
2018-06-25 01:35:59 +08:00
Travis Finkenauer
292116bd0d Declare global arch arrays with contents (next branch) (#1186)
* Declare global arch arrays with contents (#1171)

This eliminates the need for archs_enable() and eliminates the racey
initialization.

This makes the architecture-specific init and option functions
non-static so that they may be called from a different file.

Cherry-picked 853a2870

* Add cs_arch_disallowed_mode_mask global

Cherry-pick 94bce437:
mips: CS_MODE_MIPS32R6 implies CS_MODE_32

Cherry-pick 8998a3a1:
ppc: fix endian check (#1029)
Fixes bug where endianness could not be set for ppc.

Remove `big_endian` field of `cs_struct`.
Added a helper macro `MODE_IS_BIG_ENDIAN()` to check if
`CS_MODE_BIG_ENDIAN` is set.

Refactored `cs_open()` check for valid mode out of arch-specific code
into arch-independent code. Also added a valid mode check to
`cs_option()`.  The checks use a new global array
`cs_arch_disallowed_mode_mask[]`.

* Make global arrays static

Make all_arch uint32_t to guarantee a certain number of bits (with
adequate room for growth).
2018-06-24 21:05:04 +08:00
Nguyen Anh Quynh
7566f79879 cleanup 2018-06-22 01:03:26 +08:00
Travis Finkenauer
ce597d5296 Declare global arch arrays with contents (#1171)
This eliminates the need for archs_enable() and eliminates the racey
initialization.

This makes the architecture-specific init, option, and destroy functions
non-static so that they may be called from a different file.
2018-06-21 14:52:35 +08:00
Nguyen Anh Quynh
618676a229 Java: pump number of Mips operands to 10. see #1183 2018-06-19 09:36:38 +08:00
Nguyen Anh Quynh
b6e566b726 Python: pump number of Mips operands to 10. see #1183 2018-06-19 09:35:37 +08:00
Catena cyber
d3c7fd57e7 Extends Mips number of operands (#1183)
for CS_MODE_MIPS32R6
2018-06-19 09:33:47 +08:00
Catena cyber
b22f425799 Builds a test corpus for fuzzing (#1184)
* Limit size of inputs for fuzz targets

* Build a test corpus for fuzzing
2018-06-19 09:31:50 +08:00