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152 Commits

Author SHA1 Message Date
Nguyen Anh Quynh
788f3e5dc5 arm: fix printPKHASRShiftImm() - issue #1456 2019-04-17 00:48:12 +08:00
Nguyen Anh Quynh
55b149f60a arm: alias LDR [sp], 4 to POP 2019-04-16 00:01:54 +08:00
Nguyen Anh Quynh
88d5c390eb arm: fix the missing third operand of LSR - issue #1456 2019-04-15 07:47:04 +08:00
Nguyen Anh Quynh
af867a3fe1 arm: fix wrong order of operand with shift - issue #1456 2019-04-15 00:04:40 +08:00
Nguyen Anh Quynh
3d50d2cffd arm: fix opcode of ASR/LSL/LSR/ROR/RRX - issue #1456 2019-04-12 00:08:04 +08:00
Nguyen Anh Quynh
58750a1b71 arm: fix more MSVC warnings 2019-03-16 15:40:38 +08:00
Nguyen Anh Quynh
41f24e31af arm: fix more MSVC warnings 2019-03-16 15:32:14 +08:00
Nguyen Anh Quynh
eb4dcfb214 arm: sync with llvm 7.0.1 2019-03-16 15:22:15 +08:00
Nguyen Anh Quynh
be24095038 arm: update writeback for STR_POST_REG (issue #1296) 2019-01-28 16:35:18 +08:00
Disconnect3d
6e29dfa2c0 Fix arm thb instruction shift value (#1330) 
* Fixes #1317 - arm thb operand.shift.value

For a more detailed description, see issue #1317.

Release 4.0.0 introduced a new field for ARM operands:
`operand.mem.lshift`. This field was supposed to be a bug fix for #246.
The #246 issue has been fixed in the meantime and the proper shift value
was stored in `operand.shift.value`.

The 4.0.0 changes created a regression in which `operand.shift.value`
was not set for a `tbh [r0, r1, lsl #1]` instruction on ARM and the
value was set in a `operand.mem.lshift` field instead.

As the regression broke some of users codebase (e.g. in
[manticore](https://github.com/trailofbits/manticore/pull/1312) project), we fix it by setting
`operand.shift.value` back again.

As a result, the shift value is set in two fields: `operand.shift.value`
and `operand.mem.lshift`. As the `operand.shift` also stores a `.type`
field, we might want to deprecate `operand.mem.lshift` in the future.

* Add changelog stub
 2019-01-02 09:51:22 +08:00
Nguyen Anh Quynh
76c1c3c4e9 merge next to master 2018-07-20 12:36:50 +08:00
Catena cyber
aad3aca3e7 Use printint functions from SStream (#1165) 
in perticular, not to overflow -INT_MIN
 2018-06-06 06:31:53 +08:00
Catena cyber
a33567db49 Fix ARM operand subtracted field (#1163) 2018-06-06 06:17:25 +08:00
Catena cyber
9217582b9f Fixes shift for ARM memory operand (#1162) 
Shift is for same operand as index register
 2018-06-06 06:09:53 +08:00
Catena cyber
62f1d9fe14 Fix ARM operand subtracted field (#1163) 2018-06-05 22:20:02 +08:00
l0stb1t
04b461a76d Fixed #1060 #1061 #1062 (#1079) 2018-03-12 22:23:48 +07:00
Nguyen Anh Quynh
d75eedd8bc arm: fix #1060 2017-12-15 10:10:04 +08:00
Richard Henderson
5423b215bf Constify backend data (#1040) 
* Constify string literals

Use -Wwrite-strings to force string literals to be of
type "const char[]", then fix up all warning fallout.

* Constify common infrastructure

Step one in allowing backend data to be readonly.
Minimal changes to backends for now; just set all pointers
in common structs that aren't modified to const.

* Constify AArch64 backend

Section size changes within libcapstone.so are

-.rodata               602587
-.data.rel.ro          228416
-.data                1003746
+.rodata               769051
+.data.rel.ro          241120
+.data                 824578

* Constify ARM backend

Section size changes within libcapstone.so are

-.rodata               769051
-.data.rel.ro          241120
-.data                 824578
+.rodata               959835
+.data.rel.ro          245120
+.data                 629506

* Constify Mips backend

Section size changes within libcapstone.so are

-.rodata               959835
-.data.rel.ro          245120
-.data                 629506
+.rodata              1069851
+.data.rel.ro          256416
+.data                 508194

* Constify PowerPC backend

Section size changes within libcapstone.so are

-.rodata              1069851
-.data.rel.ro          256416
-.data                 508194
+.rodata              1142715
+.data.rel.ro          272224
+.data                 419490

* Constify Sparc backend

Section size changes within libcapstone.so are

-.rodata              1142715
-.data.rel.ro          272224
-.data                 419490
+.rodata              1175227
+.data.rel.ro          277536
+.data                 381666

* Constify SystemZ backend

Section size changes within libcapstone.so are

-.rodata              1175227
-.data.rel.ro          277536
-.data                 381666
+.rodata              1221883
+.data.rel.ro          278016
+.data                 334498

* Constify X86 backend

Section size changes within libcapstone.so are

-.rodata              1221883
-.data.rel.ro          278016
-.data                 334498
+.rodata              1533531
+.data.rel.ro          281184
+.data                  19714

* Constify XCore backend

Section size changes within libcapstone.so are

-.rodata              1533531
-.data.rel.ro          281184
-.data                  19714
+.rodata              1553026
+.data.rel.ro          281280
+.data                     40
 2017-10-22 08:45:40 +08:00
Matt Suiche
0441af5ce7 Resolve some casting issues with Visual Studio. 2017-09-05 22:20:57 +07:00
Matt Suiche
4e7f49228b - Resolve some casting issues with Visual Studio. (#1007) 2017-09-05 22:15:13 +07:00
Nguyen Anh Quynh
f72bb9cfe2 arm: UADD8 updates flags. fix #980 2017-07-31 01:06:17 +07:00
Nguyen Anh Quynh
6cd9313c70 arm: UADD8 updates flags. fix #980 2017-07-31 01:05:28 +07:00
Nguyen Anh Quynh
663b210cb7 arm: another fix for #913 2017-05-05 09:53:29 +08:00
Nguyen Anh Quynh
5b92f8c1da arm: POP {reg} read/write SP register. this fixes #913 2017-05-04 17:21:41 +08:00
Nguyen Anh Quynh
a71f763b09 arm: POP {reg} read/write SP register. this fixes #913 2017-05-04 17:20:01 +08:00
noword
22d762085c fix compiling error in MS VS2015 (#869) 
for issue #868
 2017-04-26 09:10:44 +08:00
noword
8d5436b4e3 fix compiling error in MS VS2015 (#869) 
for issue #868
 2017-04-26 05:52:28 +08:00
Nguyen Anh Quynh
f91b2c2470 arm64: fix immediate number in detail mode. see #860 2017-02-26 18:17:39 +08:00
Nguyen Anh Quynh
695e60be9d arm: add IMM operand for printPostIdxImm8s4Operand(). issue #861 2017-02-22 09:27:16 +08:00
Nguyen Anh Quynh
fd1599e279 arm: add IMM operand for printPostIdxImm8s4Operand(). issue #861 2017-02-22 09:26:54 +08:00
Nguyen Anh Quynh
e22c6c6100 arm: fix access info for RET. see issue #825 2016-12-13 18:02:51 +07:00
Nguyen Anh Quynh
a5418178b2 arm: update imm in printOperand() to fix error reported by @trufae in PR #764 2016-09-22 22:25:09 +08:00
Nguyen Anh Quynh
53a4473c92 arm: update imm in printOperand() to fix error reported by @trufae in PR #764 2016-09-22 22:22:36 +08:00
Akihiko Odaki
e7e4e1dfda arm: treat ARM address as unsigned 
It should be unsigned because:
* It does arithmetic operations
* Format strings have "%u" instead of "%d"

# Conflicts:
#	arch/ARM/ARMInstPrinter.c
#	bindings/python/test_arm.py
#	tests/test_arm.c
 2016-09-04 00:13:50 +09:00
Akihiko Odaki
2876044815 arm: treat ARM address as unsigned 
It should be unsigned because:
* It does arithmetic operations
* Format strings have "%u" instead of "%d"
 2016-09-03 14:28:46 +09:00
Nguyen Anh Quynh
c6ddb2b553 arm: fix issue #760 2016-09-02 01:05:57 +08:00
Nguyen Anh Quynh
383adcf41f cleanup 2016-08-17 16:20:52 +08:00
Nguyen Anh Quynh
452c4e934f arm: fix issue #747 2016-08-17 16:19:21 +08:00
Nguyen Anh Quynh
34ecce8b72 arm: fix issue #746 2016-08-15 20:00:40 +08:00
Nguyen Anh Quynh
dc7568a926 arm: fix issue #740 2016-08-11 17:01:48 +08:00
Nguyen Anh Quynh
c7df4c0920 arm: fix issue #740 2016-08-09 23:19:04 +08:00
tandasat
0368aa7c42 fix #681 2016-05-16 08:32:58 -07:00
tandasat
d4ef430b33 port Windows driver support 2016-05-11 21:48:32 -07:00
Nguyen Anh Quynh
3f461adae3 remove myinttypes.h 2016-04-26 09:47:30 +08:00
Nguyen Anh Quynh
a23f9d37ed add CS_OPT_UNSIGNED option to print immediate in unsigned form. only ARM is supported for now (issue #585) 2016-03-14 13:52:23 +08:00
Nguyen Anh Quynh
15768eafb0 fix some compilation warnings reported by MSVC 2016-03-08 00:49:15 +08:00
reyalpchdk
8b12b71cf5 Align thumb BLX immediate by discarding low bits 2016-01-16 21:32:09 -08:00
Nguyen Anh Quynh
ebf0041e6a arm: another fix for #446. bug reported by @uxmal 2015-08-19 22:36:37 +08:00
Nguyen Anh Quynh
ddf5488d36 arm: another fix for #446. bug reported by @uxmal 2015-08-19 22:36:09 +08:00
Nguyen Anh Quynh
ed43e241c5 arm: fix issue #459 reported by Ahmed Garhy 2015-08-15 14:20:23 +08:00