The FNOP instruction has the same encoding as FBF with zero displacement,
but according to the manual, it has some additional synchronization
functions, so it would be good if Capstone disassembles this with the
FNOP mnemonic instead of the FBF mnemonic.
Before this change:
$ cstool m68k40 0xf2800000
0 f2 80 00 00 fbf.w $2
After this change:
$ cstool m68k40 0xf2800000
0 f2 80 00 00 fnop
Implemented new functions present in LLVM 14.0.5 for any new instruction
type in Armv9.2; mainly SME / Matrix printing functions.
New set_sme_index function added (called from AArch64GenAsmWriter.inc)
to correctly add operands to new sme_index operand type. Doing_SME_Index
bool added to cs_struct to indicate when operands should be added to
sme_index type.
Functionality added to support SMSTART/SMSTOP aliases.
Added new decode functions, mainly for SME matrix operands and SVCR sys
register, as well as updating existing decode functions which have seen
changes in LLVM 14.0.5.
The _getInstruction function has also been updated to its LLVM 14.0.5
counterpart; with a new switch case for adding implicit operands to the
relevant SME instructions.
* mos65xx: use imm field for immediate operand value
using the wrong field works on little-endian hosts, but on big-endian the wrong value would be read
* mos65xx: set operand mem field to address also in relative modes
previously the last operand would have an offset, which doesn't match the printed operand
* mos65xx: add bpl instruction to test
this demonstrates an address operand with relative addressing
* Fix a few registry access mode mappings
* Fix rollback of operand access changes
Re-fix operand access of three mov instructions
* Remove binding breaking #if 0
The python script for generating constants in the bindings does not know how to handle the #if 0 statements included in these files.
* Add files via upload
Update registry access mode for several versions of pop such as POPDS, POPSS, etc
* Fix a few registry access mode mappings
* Fix rollback of operand access changes
Re-fix operand access of three mov instructions
* Remove binding breaking #if 0
The python script for generating constants in the bindings does not know how to handle the #if 0 statements included in these files.
* Updated registry access on cmov instructions
Registry access for the destination operand of the conditional move (cmov) opcodes were incorrectly listed as READ | WRITE. Although you would expect the two operands to be compared in this opcode, it instead relies on the associated flag in EFLAGS regardless of the value in the destination operand.
* riscv: Fix printAliasInstr
We do not want to append the entire string, only the
single non-argument character.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* riscv: Implement printCSRSystemRegister
While upstream LLVM probably has a tablegen thing for these
somewhere, the current import doesn't include them. Take the
list from riscv-privileged-v1.10.pdf.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
