* Fix CID 508418 - Uninitialized struct
* Fix CID 509089 - Fix OOB read and write
* Fix CID 509088 - OOB.
Also adds tests and to ensure no OOB access.
* Fix CID 509085 - Resource leak.
* Fix CID 508414 and companions - Using undefined values.
* Fix CID 508405 - Use of uninitialized value
* Remove unnecessary and badly implemented dev fuzz code.
* Fix CID 508396 - Uninitialzied variable.
* Fix CID 508393, 508365 -- OOB read.
* Fix CID 432207 - OVerlapping memory access.
* Remove unused functions
* Fix CID 432170 - Overlapping memory access.
* Fix CID 166022 - Check for negative index
* Let strncat not depend n src operand.
* Fix 509083 and 509084 - NULL dereference
* Remove duplicated code.
* Initialize sysop
* Fix resource leak
* Remove unreachable code.
* Remove duplicate code.
* Add assert to check return value of cmoack
* Fixed: d should be a signed value, since it is checked against < 0
* Add missing break.
* Add NULL check
* Fix signs of binary search comparisons.
* Add explicit cast of or result
* Fix correct scope of case.
* Handle invalid integer type.
* Return UINT_MAX instead of implicitly casted -1
* Remove dead code
* Fix type of im
* Fix type of d
* Remove duplicated code.
* Add returns after CS_ASSERTS
* Check for len == 0 case.
* Ensure shift operates on uint64
* Replace strcpy with strncpy.
* Handle edge cases for 32bit rotate
* Fix some out of enum warnings
* Replace a strcpy with strncpy.
* Fix increment of address
* Skip some linting
* Fix: set instruction id
* Remove unused enum
* Replace the last usages of strcpy with SStream functions.
* Increase number of allowed AArch64 operands.
* Check safety of incrementing t the next operand.
* Fix naming of operand
* Update python constants
* Fix option setup of CS_OPT_DETAIL_REAL
* Document DETAIL_REAL has to be used with CS_OPT_ON.
* Run Coverity scan every Monday.
* Remove dead code
* Fix OOB read
* Rename macro to reflect it is only used with sstreams
* Fix rebase issues
* Add auto-sync updater.
* Update Capstone core with auto-sync changes.
* Update ARM via auto-sync.
* Make changes to arch modules which are introduced by auto-sync.
* Update tests for ARM.
* Fix build warnings for make
* Remove meson.build
* Print shift amount in decimal
* Patch non LLVM register alias.
* Change type of immediate operand to unsiged (due to: #771)
* Replace all occurances of a register with its alias.
* Fix printing of signed imms
* Print rotate amount in decimal
* CHange imm type to int64_t to match LLVM imm type.
* Fix search for register names, by completing string first.
* Print ModImm operands always in decimal
* Use number format of previous capstone version.
* Correct implicit writes and update_flags according to SBit.
* Add missing test for RegImmShift
* Reverse incorrect comparision.
* Set shift information for move instructions.
* Set mem access for all memory operands
* Set subtracted flag if offset is negative.
* Add flag for post-index memory operands.
* Add detail op for BX_RET and MOVPCLR
* Use instruction post_index operand.
* Add VPOP and VPUSH as unique CS IDs.
* Add shifting info for MOVsr.
* Add TODOs.
* Add in LLVM hardcoded operands to detail.
* Move detail editing from InstPrinter to Mapping
* Formatting
* Add removed check.
* Add writeback register and constraints to RFEI instructions.
* Translate shift immediate
* Print negative immediates
* Remove duplicate invalid entry
* Add CS groups to instructions
* Fix write attriutes of stores.
* Add missing names of added instructions
* Fix LLVM bug
* Add more post_index flags
* http -> https
* Make generated functions static
* Remove tab prefix for alias instructions.
* Set ValidateMCOperand to NULL.
* Fix AddrMode3Operand operands
* Allow getting system and banked register name via API
* Add writeback to STC/LDC instructions.
* Fix (hopefully) last case where disp is negative and subtracted = true
* Remove accidentially introduced regressions
* Constify registerinfo.py output
Remove two conditionals separating identical bits of code.
Add "const" markup to MCRegisterDesc and MCRegisterClass.
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify instrinfo-arch.py output
In this case, do not actively strip const.
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the AArch64 backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the EVM backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify M680X backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify M68K backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the Mips backend
The Mips backend has not been regenerated from LLVM recently,
and there are more fixups required than I'd like. Just apply
the fixes to the tables by hand for now.
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the Sparc backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the TMS320C64x backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the X86 backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the XCore backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify systemregister.py output
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the ARM backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the PowerPC backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the MOS65XX backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the SystemZ backend
The mapping of system register to indexes is easy to
generate read-only. Since we know the indexes are
between 0 and 31, use uint8_t instead of unsigned.
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the WASM backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify cs.c
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the BPF backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Avoids leak in wasm details
Extending cs_detail in capstone.h
* Safety checks before allocating memory for brtable in WASM
* Revert "Avoids leak in wasm details"
This reverts commit 03f822b34a03f23554aaffb2951b62c62645e5e5.
* Refactoring brtable for WASM
* Fix undefined shift in WASM get_varuint64
