* RISCV: Check CS_MODE_RISCVC in getFeatureBits
Enable compressed instruction extension with RISCVC.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* RISCV: Fix skipdata_size for CS_MODE_RISCVC
RISC-V compressed instructions are 2 bytes, not 1.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit adds some registers to the list of implicit used registers and
implicit modified registers for several AArch64 instructions.
This commit also maps the `ARM64_GRP_CALL` group to the BL* instruction family.
It should fix issue #1606.
* Constify registerinfo.py output
Remove two conditionals separating identical bits of code.
Add "const" markup to MCRegisterDesc and MCRegisterClass.
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify instrinfo-arch.py output
In this case, do not actively strip const.
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the AArch64 backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the EVM backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify M680X backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify M68K backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the Mips backend
The Mips backend has not been regenerated from LLVM recently,
and there are more fixups required than I'd like. Just apply
the fixes to the tables by hand for now.
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the Sparc backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the TMS320C64x backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the X86 backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the XCore backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify systemregister.py output
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the ARM backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the PowerPC backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the MOS65XX backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the SystemZ backend
The mapping of system register to indexes is easy to
generate read-only. Since we know the indexes are
between 0 and 31, use uint8_t instead of unsigned.
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the WASM backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify cs.c
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the BPF backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* updated 6502 support. some improvements to the base 6502 support but also adds support for 65c02, w65c02, and 65816.
* add CS_OPT_SYNTAX_MOTOROLA.
This will use "$" as a hex prefix instead of "0x"
* remove excess blank lines
- This is not suitable for an application framework
especially for kernel code.
- All these error conditions do not occur under normal conditions.
They only can occur if a maintainer (in the future) would make
inappropriate changes to the M680X code base.
- Added CS_ASSERT macro which allows to use assertions when debugging
by defining CAPSTONE_DEBUG.
- Updated compiler documenation
