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498 Commits

Author SHA1 Message Date
Wu ChenXu
5cca00533d
Update to v5.0.3 (#2451) 
* Prepare for release v5.0.2

* Update ChangeLog for v5.0.2

* Update Python package build action

* [CI] Downgrade upload-artifact tp v3

* update changelog

* [CI] downguard actions/download-artifact to v3

* Update version to v5.0.3

* update python bindings version
 2024-08-20 22:41:54 +08:00
Wu ChenXu
c34fc89a45
Prepare for release v5.0.2 (#2425) 2024-08-08 11:55:54 +08:00
Rot127
2971910d6e
Revert constant of CS_OP_MEM to v5 value. (#2275) 2024-02-18 13:03:49 +08:00
Rot127
6ac231ff04
Add CS_aarch64 macro without parameter. (#2219) 2023-12-18 08:36:54 +08:00
Rot127
ee75e4b9a4
[v5] Add meta-programming macros for ARM64/AArch64 name change to capstone.h (#2199) 
* Add meta-programming macros for ARM64/AArch64 name change to capstone.h

* Add tests for rename macros. (#2202)
 2023-11-24 11:57:23 +08:00
Wu ChenXu
16e2b9f942
Prepare for release v5.0.1 (#2143) 
* Add Python bindings for WASM

* Update Python bindings for m68k

* Update Python bindings for mos65xx

* Update Python bindings for x86

* Add Python bindings for SH

* Update CS_* constants in Python bindings

* Update constants from ARM auto-sync patch

* Fixing TriCore disasm instructions (#2088)

* allow absolute CMAKE_INSTALL_*DIR (#2134)

This patch fixes Capstone 5 build on NixOS.

NixOS's build infrastructure sets CMAKE_INSTALL_{LIB,INCLUDE}DIR to
absolute paths. If you append it to ${prefix}, you get the wrong path.
NixOS automatically detects it and links this issue:
https://github.com/NixOS/nixpkgs/issues/144170

* Disable swift binding const generate

* update bindings const

* update capstone version

* update ChangeLog

---------

Co-authored-by: Peace-Maker <peace-maker@wcfan.de>
Co-authored-by: Bastian Koppelmann <bkoppelmann@users.noreply.github.com>
Co-authored-by: chayleaf <chayleaf@protonmail.com>
 2023-08-21 18:05:18 +08:00
billow
b39fac744f Fix tricore.h 2023-06-23 23:46:19 +08:00
Peace-Maker
654512f029 Merge branch 'next' into riscv_insn_groups 2023-05-30 16:23:34 +02:00
billow
6c3a899646
Add operands access support for TriCore 2023-05-30 12:27:38 +08:00
billow
9d6c489c57
Add .clang-format and format 2023-05-30 11:09:37 +08:00
Rot127
b0e7417207
Pull auto-sync's changes from 2ab11ad9bd 2023-05-30 11:08:18 +08:00
Peace-Maker
0b1e82ac88 RISCV: add more instruction groups 
Add call, ret, int and branch_relative instruction groups to riscv
mappings.
 2023-05-01 22:55:26 +02:00
billow
985b6fcb07
Upper all inc and fix 2023-05-01 22:52:47 +08:00
billow
4d693da18b
Fix tricore.h 2023-04-26 16:06:31 +08:00
billow
1ed507bbf6
Fix tricore.h and remove inc folder 2023-04-25 09:24:07 +08:00
billow
58bce36a55
Format all .(c|h) code 2023-04-20 21:55:37 +08:00
billow
5af447542e
fix TRICORE_GENERIC inst 2023-04-14 00:36:07 +08:00
billow
5417985969
fix tests 2023-04-14 00:36:04 +08:00
billow
9c982d310c
fix tc1.6.2 tests 2023-04-14 00:36:02 +08:00
billow
f0cfb4d8b2
fix 2023-04-14 00:35:59 +08:00
billow
ff0c69f14b
fix 2023-04-14 00:35:58 +08:00
billow
c1c413765b
fix TriCoreDisassembler.c from tests 2023-04-14 00:35:51 +08:00
billow
7c56b54ebc
feat: Add support for TriCore feature bits and new architectures 
- Add support for new Tricore architectures
- Clean up redundant instructions definitions
- Modify architecture options for the TRICORE mode
- Update disallowed modes for Tricore architecture
 2023-04-14 00:35:47 +08:00
billow
b9151fb030
fix 2023-04-14 00:35:46 +08:00
billow
4409b29faf
Add support for TriCore V162 and new instructions/operands. 
- Add new instruction `MOVZ_A`, remove instruction `NOT`, and add several new multiply and multiply-subtract instructions
- Move `multiclass mISR_1` and `multiclass mISYS_0` to separate file and fix typo in `rfe` instruction in `mISYS_0`
- Add support for new CPU feature `TriCore_FEATURE_HasV162` and update relevant inc files.
 2023-04-14 00:35:42 +08:00
billow
072b70fab4
feat: Add and remove TriCore instructions. 
- Add 3 new TriCore instructions
- Remove TriCore instruction "TriCore_INS_INIT"
- Alphabetized and rearranged various TriCore instructions
- Commented out code remains in the diff but is not part of the program.
 2023-04-14 00:35:34 +08:00
billow
0aeed244df
add tricore_feature support 2023-04-14 00:35:33 +08:00
billow
29ced4e735
refactor: Refactor TriCore instruction decoding and register definition. 
- Update TriCore processor register definitions with auto-generated file `TriCoreGenCSRegEnum.inc`
- Add several new TriCore processor instructions with auto-generated file `TriCoreGenCSInsnEnum.inc`
- Update TriCore_OP_GROUP enumeration with auto-generated file `TriCoreGenCSOpGroup.inc`
- Rename and restructure TriCore processor register classes
- Remove unused register class definitions and related code
 2023-04-14 00:35:32 +08:00
billow
b1f77e406f
add some tricore v1.1 inst 2023-04-14 00:35:27 +08:00
billow
18954aa9ea
fix 2023-04-14 00:35:09 +08:00
billow
8fc6eccd82
- add tricore to python binding 
- try fix `test_corpus.py`
 2023-04-14 00:34:59 +08:00
billow
c776b8c84f
fix build 2023-04-14 00:34:52 +08:00
billow
abf826a2a4
update TriCore*.inc 2023-04-14 00:34:51 +08:00
billow
c6138aca25
Fix build and test 2023-04-14 00:34:28 +08:00
billow
6b4d73191d
Fix rebase error 2023-04-14 00:34:27 +08:00
Sidney Pontes Filho
dfd368f691
Transfer modifications of TriDis/llvm-tricore on Feb, 04 2017 2023-04-14 00:34:25 +08:00
Sidney Pontes Filho
1a5d594a4e
Adjustments in TriCore and add more instructions into tests/test_tricore.c 2023-04-14 00:34:22 +08:00
Sidney Pontes Filho
87f935dae7
Transfer modifications of TriDis/llvm-tricore on Oct 05, 2016 2023-04-14 00:34:20 +08:00
Sidney Pontes Filho
82fcf25a5c
Remove all compiler warnings 2023-04-14 00:34:17 +08:00
Sidney Pontes Filho
a351c48ddc
Add group name maps 2023-04-14 00:34:12 +08:00
Sidney Pontes Filho
6374a774d4
Modify Makefiles for TriCore architecture 2023-04-14 00:34:08 +08:00
Sidney Pontes Filho
7449ebc836
Add TriCore Architecture 2023-04-14 00:34:07 +08:00
Wu ChenXu
6eb1db9c04
Merge pull request #1927 from ysat0/superh 2023-01-27 14:58:24 +08:00
ζeh Matt
7939e88ada
Update comment 2022-11-22 22:25:22 +02:00
ζeh Matt
6d6debeae2
Add post_index to arm 2022-11-22 22:25:08 +02:00
ζeh Matt
1e416c8e71
Add post_index field for cs_arm64 2022-11-22 19:23:32 +02:00
Yoshinori Sato
a819f6b8be SH: Add missing sh.h 
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
 2022-10-20 13:04:56 +09:00
Yoshinori Sato
39f10cc243 Merge remote-tracking branch 'origin/next' into superh 2022-10-13 12:30:15 +09:00
Yoshinori Sato
c68acf3540 SH: Add superh support for common part. 
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
 2022-10-12 20:11:05 +09:00
Wu ChenXu
662bb3f6cc
Merge pull request #1907 from FinnWilkinson/AArch64-Armv9.2-update 2022-10-06 17:27:20 +08:00