- Add 3 new TriCore instructions
- Remove TriCore instruction "TriCore_INS_INIT"
- Alphabetized and rearranged various TriCore instructions
- Commented out code remains in the diff but is not part of the program.
- Add support for V110 and V120 in various LD instructions
- Define new multiclass for code reuse
- Restructure LD_A_v120 in favor of LD_A with Requires constraint
- Add new defs for LT_U with suffixes for V110 support
- Fix bug in `printDisp8Imm` function in `TriCoreInstPrinter.c`
- Add new `CALL_sb` instruction to `TriCoreInstrInfo.td`
- Reorder instruction definitions and operands in `TriCoreInstrInfo.td`
- Add new immediate operands and refactor code for better readability in TriCoreInstrInfo
- Update InstPrinter functions to handle new immediate operands and remove unused function
- Rename `ISLR_post_increment` to `ISLR_pos` for clarity
- Fix register decoding for TriCore architecture in `TriCoreDisassembler.c`
- Add new file `LoadStore.s.cs` to `suite/MC/TriCore`
The FNOP instruction has the same encoding as FBF with zero displacement,
but according to the manual, it has some additional synchronization
functions, so it would be good if Capstone disassembles this with the
FNOP mnemonic instead of the FBF mnemonic.
Before this change:
$ cstool m68k40 0xf2800000
0 f2 80 00 00 fbf.w $2
After this change:
$ cstool m68k40 0xf2800000
0 f2 80 00 00 fnop
Implemented new functions present in LLVM 14.0.5 for any new instruction
type in Armv9.2; mainly SME / Matrix printing functions.
New set_sme_index function added (called from AArch64GenAsmWriter.inc)
to correctly add operands to new sme_index operand type. Doing_SME_Index
bool added to cs_struct to indicate when operands should be added to
sme_index type.
Functionality added to support SMSTART/SMSTOP aliases.
Added new decode functions, mainly for SME matrix operands and SVCR sys
register, as well as updating existing decode functions which have seen
changes in LLVM 14.0.5.
The _getInstruction function has also been updated to its LLVM 14.0.5
counterpart; with a new switch case for adding implicit operands to the
relevant SME instructions.
* mos65xx: use imm field for immediate operand value
using the wrong field works on little-endian hosts, but on big-endian the wrong value would be read
* mos65xx: set operand mem field to address also in relative modes
previously the last operand would have an offset, which doesn't match the printed operand
* mos65xx: add bpl instruction to test
this demonstrates an address operand with relative addressing
* Fix a few registry access mode mappings
* Fix rollback of operand access changes
Re-fix operand access of three mov instructions
* Remove binding breaking #if 0
The python script for generating constants in the bindings does not know how to handle the #if 0 statements included in these files.
* Add files via upload
Update registry access mode for several versions of pop such as POPDS, POPSS, etc
* Fix a few registry access mode mappings
* Fix rollback of operand access changes
Re-fix operand access of three mov instructions
* Remove binding breaking #if 0
The python script for generating constants in the bindings does not know how to handle the #if 0 statements included in these files.
* Updated registry access on cmov instructions
Registry access for the destination operand of the conditional move (cmov) opcodes were incorrectly listed as READ | WRITE. Although you would expect the two operands to be compared in this opcode, it instead relies on the associated flag in EFLAGS regardless of the value in the destination operand.
* riscv: Fix printAliasInstr
We do not want to append the entire string, only the
single non-argument character.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* riscv: Implement printCSRSystemRegister
While upstream LLVM probably has a tablegen thing for these
somewhere, the current import doesn't include them. Take the
list from riscv-privileged-v1.10.pdf.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* RISCV: Check CS_MODE_RISCVC in getFeatureBits
Enable compressed instruction extension with RISCVC.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* RISCV: Fix skipdata_size for CS_MODE_RISCVC
RISC-V compressed instructions are 2 bytes, not 1.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit adds some registers to the list of implicit used registers and
implicit modified registers for several AArch64 instructions.
This commit also maps the `ARM64_GRP_CALL` group to the BL* instruction family.
It should fix issue #1606.
* Constify registerinfo.py output
Remove two conditionals separating identical bits of code.
Add "const" markup to MCRegisterDesc and MCRegisterClass.
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify instrinfo-arch.py output
In this case, do not actively strip const.
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the AArch64 backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the EVM backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify M680X backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify M68K backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the Mips backend
The Mips backend has not been regenerated from LLVM recently,
and there are more fixups required than I'd like. Just apply
the fixes to the tables by hand for now.
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the Sparc backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the TMS320C64x backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the X86 backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the XCore backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify systemregister.py output
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the ARM backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the PowerPC backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the MOS65XX backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the SystemZ backend
The mapping of system register to indexes is easy to
generate read-only. Since we know the indexes are
between 0 and 31, use uint8_t instead of unsigned.
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the WASM backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify cs.c
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the BPF backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* updated 6502 support. some improvements to the base 6502 support but also adds support for 65c02, w65c02, and 65816.
* add CS_OPT_SYNTAX_MOTOROLA.
This will use "$" as a hex prefix instead of "0x"
* remove excess blank lines
- This is not suitable for an application framework
especially for kernel code.
- All these error conditions do not occur under normal conditions.
They only can occur if a maintainer (in the future) would make
inappropriate changes to the M680X code base.
- Added CS_ASSERT macro which allows to use assertions when debugging
by defining CAPSTONE_DEBUG.
- Updated compiler documenation
