* Update init of cs_detail for AArch64
as @aquynh requested in #1125
* Update init of cs_detail for ARM
as @aquynh requested in #1125
* Update init of cs_detail for EVM
as @aquynh requested in #1125
* Update init of cs_detail for M680X
as @aquynh requested in #1125
* Update init of cs_detail for M68K
as @aquynh requested in #1125
* Update init of cs_detail for Mips
as @aquynh requested in #1125
* Update init of cs_detail for PowerPC
as @aquynh requested in #1125
* Update init of cs_detail for Sparc
as @aquynh requested in #1125
* Update init of cs_detail for SystemZ
as @aquynh requested in #1125
* Update init of cs_detail for TMS320C64x
as @aquynh requested in #1125
* Update init of cs_detail for XCore
as @aquynh requested in #1125
* Comment on init of cs_detail
* wrap long lines
* Declare global arch arrays with contents (#1171)
This eliminates the need for archs_enable() and eliminates the racey
initialization.
This makes the architecture-specific init and option functions
non-static so that they may be called from a different file.
Cherry-picked 853a2870
* Add cs_arch_disallowed_mode_mask global
Cherry-pick 94bce437:
mips: CS_MODE_MIPS32R6 implies CS_MODE_32
Cherry-pick 8998a3a1:
ppc: fix endian check (#1029)
Fixes bug where endianness could not be set for ppc.
Remove `big_endian` field of `cs_struct`.
Added a helper macro `MODE_IS_BIG_ENDIAN()` to check if
`CS_MODE_BIG_ENDIAN` is set.
Refactored `cs_open()` check for valid mode out of arch-specific code
into arch-independent code. Also added a valid mode check to
`cs_option()`. The checks use a new global array
`cs_arch_disallowed_mode_mask[]`.
* Make global arrays static
Make all_arch uint32_t to guarantee a certain number of bits (with
adequate room for growth).
This eliminates the need for archs_enable() and eliminates the racey
initialization.
This makes the architecture-specific init, option, and destroy functions
non-static so that they may be called from a different file.
* Fix undefined shifts
Found by oss-fuzz
uint8_t gets promoted to integer
and integers shift cannot overflow on sign bit
* Fix undefined shifts
shifting 31 bits the sign bit
* Fix undefined shifts
uint8 gets promoted to signed integer
in ARM, MIPS, Sparc
in AArch64, PPC and Xcore
* fix undefined shift in powerpc
* Fix undefined shift in Mips
use mulitply instead
* Remove `big_endian` field of `cs_struct`
Added a helper macro `MODE_IS_BIG_ENDIAN()` to check if
`CS_MODE_BIG_ENDIAN` is set.
Refactored `cs_open()` check for valid mode out of arch-specific code
into arch-independent code. Also added a valid mode check to
`cs_option()`. The checks use a new global array
`arch_disallowed_mode_mask[]`, which is initialized in the arch-specific
`*_enable()` functions.
Fixes bug where endianness could not be set for ppc.
* Fix Mac OS brew for Travis CI
* Add a new group for relative branching instructions
* x86: Add relative branch group to appropiate instructions
* Rename RELATIVE_BRANCH to BRANCH_RELATIVE
* aarch64: Add relative branch group to appropiate instructions
* arm: Add relative branch group to appropiate instructions
* m68k: Add relative branch group to appropiate instructions
* mips: Add relative branch group to appropiate instructions
* arm64: handling of system registers added in ARMv8.2
This commit adds handling of system registers added in ARMv8.2.
Those registers are accessed by mrs and msr instructions.
Changes based on https://static.docs.arm.com/ddi0487/b/DDI0487B_a_armv8_arm.pdf, chapters D7.2-5.
List of added registers:
id_mmfr4_el1
id_aa64mmfr2_el1
sctlr_el12
cpacr_el12
ttbr0_el12
ttbr1_el12
ttbr1_el2
tcr_el12
spsr_el12
elr_el12
afsr0_el12
afsr1_el12
esr_el12
far_el12
mair_el12
amair_el12
vbar_el12
cntkctl_el12
cnthv_ctl_el2
cnthv_cval_el2
cnthv_tval_el2
cntp_tval_el02
cntp_cval_el02
cntv_ctl_el02
ntv_cval_el02
cntv_tval_el02
lorid_el1
lorc_el1
lorea_el1
lorn_el1
lorsa_el1
contextidr_el12
sign-of: Michalina Oleksy (https://github.com/layika)
* arm64: handling of system registers added in ARMv8.1/2
v8.1:
PAN (https://static.docs.arm.com/ddi0487/b/DDI0487B_a_armv8_arm.pdf, page 358)
PAN (as pstate field)
contextdir_el2
v8.2:
UAO (https://static.docs.arm.com/ddi0487/b/DDI0487B_a_armv8_arm.pdf, page 403)
UAO (as pstate field)
* arm64: handling of system registers for statistical profiling
Added handling of system registers for statistical profiling extension based on https://static.docs.arm.com/ddi0586/a/DDI0586A_Statistical_Profiling_Extension.pdf
* Update AArch64BaseInfo.h
* arm64: An attempt to fix indentation
* replace if-s in AArch64_AM_decodeAdvSIMDModImmType10 with lookup table
Lookup table is much faster than bunch of if-s. If you don't like lookup tables, I have another proposal. See http://goo.gl/RjW1lr and compare generated machine code
* Smaller lookup table and shifting and bit mask used
* Update AArch64AddressingModes.h
* replace if-s in AArch64_AM_decodeAdvSIMDModImmType10 with lookup table
Lookup table is much faster than bunch of if-s. If you don't like lookup tables, I have another proposal. See http://goo.gl/RjW1lr and compare generated machine code
* Smaller lookup table and shifting and bit mask used
* Update AArch64AddressingModes.h
The instruction encoded « 00 00 19 B2 » was correctly disassembled « orr x0, x0, #0x8000000080 », but the reported immediate value, in the detail structure, was truncated to 0x80 due to the cast.
Added support for building binaries for Windows CE 7 on ARMv7 (a.k.a., Windows Embedded Compact 7) and for Windows CE 8 on ARMv7 (a.k.a., Windows Embedded Compact 2013).
Added support for building binaries for Windows CE 7 on ARMv7 (a.k.a., Windows Embedded Compact 7) and for Windows CE 8 on ARMv7 (a.k.a., Windows Embedded Compact 2013).
Replaced header inclusions of "stdint.h" and "intrin.h" by selective inclusions to support platforms that do not provide those headers. The header "platform.h" handles the platform test.
Updated the build script for Windows CE 7 on ARMv7.
