* m68k: store correct m68k_reg value in op.reg_pair
Originally, value - M68K_REG_D0 was stored and the print logic added
M68K_REG_D0.
* m68k: fix license typo
* Bump the "cs_insn.bytes[]" size to 24 (from 16) to support M680x0 instructions with full EA (maximum 11 words)
Added a test for this in test_m68k.s
* Bump the "cs_detail.regs_read[]" size to 16 (from 12) to support M680x0 instructions with full REG_BITS (Dn+An = 16)
* m68k: use immediate mode syntax (#$0) for movem/fmovem instructions with empty register list
* update bindings to match changes to cs_insn and cs_detail
* Update init of cs_detail for AArch64
as @aquynh requested in #1125
* Update init of cs_detail for ARM
as @aquynh requested in #1125
* Update init of cs_detail for EVM
as @aquynh requested in #1125
* Update init of cs_detail for M680X
as @aquynh requested in #1125
* Update init of cs_detail for M68K
as @aquynh requested in #1125
* Update init of cs_detail for Mips
as @aquynh requested in #1125
* Update init of cs_detail for PowerPC
as @aquynh requested in #1125
* Update init of cs_detail for Sparc
as @aquynh requested in #1125
* Update init of cs_detail for SystemZ
as @aquynh requested in #1125
* Update init of cs_detail for TMS320C64x
as @aquynh requested in #1125
* Update init of cs_detail for XCore
as @aquynh requested in #1125
* Comment on init of cs_detail
* wrap long lines
* Declare global arch arrays with contents (#1171)
This eliminates the need for archs_enable() and eliminates the racey
initialization.
This makes the architecture-specific init and option functions
non-static so that they may be called from a different file.
Cherry-picked 853a2870
* Add cs_arch_disallowed_mode_mask global
Cherry-pick 94bce437:
mips: CS_MODE_MIPS32R6 implies CS_MODE_32
Cherry-pick 8998a3a1:
ppc: fix endian check (#1029)
Fixes bug where endianness could not be set for ppc.
Remove `big_endian` field of `cs_struct`.
Added a helper macro `MODE_IS_BIG_ENDIAN()` to check if
`CS_MODE_BIG_ENDIAN` is set.
Refactored `cs_open()` check for valid mode out of arch-specific code
into arch-independent code. Also added a valid mode check to
`cs_option()`. The checks use a new global array
`cs_arch_disallowed_mode_mask[]`.
* Make global arrays static
Make all_arch uint32_t to guarantee a certain number of bits (with
adequate room for growth).
* Branch targets are a separate addressing mode
Branch targets are relative displacements that identify code locations. These are neither .w nor .l nor immediates. This change removes the immediate #s before branch target addresses in disassembly, and represents the actual branch instructions more accurately in the cs_m68k_op datastructure.
M68K Python bindings have also been updated.
* m68k_inst.pc handles better; print target for PC relative offsets
Previous changes to branch operations relied on m68k_inst.pc pointing to (start of instruction + 2). This was not the case - it pointed to the end of the current instruction. This change makes it so that m68k_inst.pc points to (start of instruction), which is simple to work with.
It also changes printing of PC relative offsets to print the absolute target address, which is consistent with how most 68000 assemblers & disassemblers behave.
This is one of those “how did this ever work?” changes. Problem was that as m68k_op was aliased with the imm value so when changing that to something big it would trash the values in the mem struct which would make things go really bad.
Now m68k_op_mem has been moved out of the union so this will not happen again. Also fixed instruction printing bug related to this (just happend to “work” due to the old union layout)
* Add a new group for relative branching instructions
* x86: Add relative branch group to appropiate instructions
* Rename RELATIVE_BRANCH to BRANCH_RELATIVE
* aarch64: Add relative branch group to appropiate instructions
* arm: Add relative branch group to appropiate instructions
* m68k: Add relative branch group to appropiate instructions
* mips: Add relative branch group to appropiate instructions
* instead of using bit operations, we now leverage the size of the
enclosing union to avoid running code and provide a more convenient
interface to the library user.
* Fixed a break indentation
* Fixed incorrect enum value for M68K_GRP_IRET
* Fixed so groups_count is set to 0 at init
* Added group_count printing in python example
Added support for building binaries for Windows CE 7 on ARMv7 (a.k.a., Windows Embedded Compact 7) and for Windows CE 8 on ARMv7 (a.k.a., Windows Embedded Compact 2013).
Added support for building binaries for Windows CE 7 on ARMv7 (a.k.a., Windows Embedded Compact 7) and for Windows CE 8 on ARMv7 (a.k.a., Windows Embedded Compact 2013).
Replaced header inclusions of "stdint.h" and "intrin.h" by selective inclusions to support platforms that do not provide those headers. The header "platform.h" handles the platform test.
Updated the build script for Windows CE 7 on ARMv7.
* Cleaned up M68KDisassembler.h with legacy stuff from Musashi which isn't used at all.
* Removed M68KConf.h which isn't needed anymore.
* Made some functions static as they are now only local to the current file.
In case of out of bound access return a poison value to force to point to
d68000_invalid() opcode. This will force instruction_is_valid() to return
false and capstone will do skipdata.
Line A are more M68K standard invalid lines than 0x0808.
