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104f693c11
* Add auto-sync updater. * Update Capstone core with auto-sync changes. * Update ARM via auto-sync. * Make changes to arch modules which are introduced by auto-sync. * Update tests for ARM. * Fix build warnings for make * Remove meson.build * Print shift amount in decimal * Patch non LLVM register alias. * Change type of immediate operand to unsiged (due to: #771) * Replace all occurances of a register with its alias. * Fix printing of signed imms * Print rotate amount in decimal * CHange imm type to int64_t to match LLVM imm type. * Fix search for register names, by completing string first. * Print ModImm operands always in decimal * Use number format of previous capstone version. * Correct implicit writes and update_flags according to SBit. * Add missing test for RegImmShift * Reverse incorrect comparision. * Set shift information for move instructions. * Set mem access for all memory operands * Set subtracted flag if offset is negative. * Add flag for post-index memory operands. * Add detail op for BX_RET and MOVPCLR * Use instruction post_index operand. * Add VPOP and VPUSH as unique CS IDs. * Add shifting info for MOVsr. * Add TODOs. * Add in LLVM hardcoded operands to detail. * Move detail editing from InstPrinter to Mapping * Formatting * Add removed check. * Add writeback register and constraints to RFEI instructions. * Translate shift immediate * Print negative immediates * Remove duplicate invalid entry * Add CS groups to instructions * Fix write attriutes of stores. * Add missing names of added instructions * Fix LLVM bug * Add more post_index flags * http -> https * Make generated functions static * Remove tab prefix for alias instructions. * Set ValidateMCOperand to NULL. * Fix AddrMode3Operand operands * Allow getting system and banked register name via API * Add writeback to STC/LDC instructions. * Fix (hopefully) last case where disp is negative and subtracted = true * Remove accidentially introduced regressions
168 lines
5.3 KiB
C++
168 lines
5.3 KiB
C++
//===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the MCOperandInfo and MCInstrDesc classes, which
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// are used to describe target instructions and their operands.
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//
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//===----------------------------------------------------------------------===//
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/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
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#ifndef CS_LLVM_MC_MCINSTRDESC_H
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#define CS_LLVM_MC_MCINSTRDESC_H
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#include "MCRegisterInfo.h"
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#include "capstone/platform.h"
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//===----------------------------------------------------------------------===//
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// Machine Operand Flags and Description
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//===----------------------------------------------------------------------===//
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/// Operand constraints. These are encoded in 16 bits with one of the
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/// low-order 3 bits specifying that a constraint is present and the
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/// corresponding high-order hex digit specifying the constraint value.
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/// This allows for a maximum of 3 constraints.
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typedef enum {
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MCOI_TIED_TO = 0, // Operand tied to another operand.
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MCOI_EARLY_CLOBBER // Operand is an early clobber register operand
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} MCOI_OperandConstraint;
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// Define a macro to produce each constraint value.
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#define CONSTRAINT_MCOI_TIED_TO(op) \
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((1 << MCOI_TIED_TO) | ((op) << (4 + MCOI_TIED_TO * 4)))
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#define CONSTRAINT_MCOI_EARLY_CLOBBER \
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(1 << MCOI_EARLY_CLOBBER)
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/// OperandFlags - These are flags set on operands, but should be considered
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/// private, all access should go through the MCOperandInfo accessors.
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/// See the accessors for a description of what these are.
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enum MCOI_OperandFlags {
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MCOI_LookupPtrRegClass = 0,
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MCOI_Predicate,
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MCOI_OptionalDef
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};
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/// Operand Type - Operands are tagged with one of the values of this enum.
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enum MCOI_OperandType {
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MCOI_OPERAND_UNKNOWN = 0,
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MCOI_OPERAND_IMMEDIATE = 1,
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MCOI_OPERAND_REGISTER = 2,
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MCOI_OPERAND_MEMORY = 3,
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MCOI_OPERAND_PCREL = 4,
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MCOI_OPERAND_FIRST_GENERIC = 6,
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MCOI_OPERAND_GENERIC_0 = 6,
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MCOI_OPERAND_GENERIC_1 = 7,
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MCOI_OPERAND_GENERIC_2 = 8,
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MCOI_OPERAND_GENERIC_3 = 9,
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MCOI_OPERAND_GENERIC_4 = 10,
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MCOI_OPERAND_GENERIC_5 = 11,
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MCOI_OPERAND_LAST_GENERIC = 11,
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MCOI_OPERAND_FIRST_GENERIC_IMM = 12,
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MCOI_OPERAND_GENERIC_IMM_0 = 12,
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MCOI_OPERAND_LAST_GENERIC_IMM = 12,
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MCOI_OPERAND_FIRST_TARGET = 13,
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};
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/// MCOperandInfo - This holds information about one operand of a machine
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/// instruction, indicating the register class for register operands, etc.
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///
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typedef struct MCOperandInfo {
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/// This specifies the register class enumeration of the operand
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/// if the operand is a register. If isLookupPtrRegClass is set, then this is
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/// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
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/// get a dynamic register class.
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int16_t RegClass;
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/// These are flags from the MCOI::OperandFlags enum.
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uint8_t Flags;
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/// Information about the type of the operand.
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uint8_t OperandType;
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/// The lower 3 bits are used to specify which constraints are set.
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/// The higher 13 bits are used to specify the value of constraints (4 bits each).
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uint16_t Constraints;
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/// Currently no other information.
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} MCOperandInfo;
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//===----------------------------------------------------------------------===//
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// Machine Instruction Flags and Description
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//===----------------------------------------------------------------------===//
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/// MCInstrDesc flags - These should be considered private to the
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/// implementation of the MCInstrDesc class. Clients should use the predicate
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/// methods on MCInstrDesc, not use these directly. These all correspond to
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/// bitfields in the MCInstrDesc::Flags field.
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enum {
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MCID_Variadic = 0,
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MCID_HasOptionalDef,
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MCID_Pseudo,
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MCID_Return,
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MCID_Call,
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MCID_Barrier,
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MCID_Terminator,
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MCID_Branch,
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MCID_IndirectBranch,
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MCID_Compare,
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MCID_MoveImm,
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MCID_MoveReg,
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MCID_Bitcast,
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MCID_Select,
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MCID_DelaySlot,
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MCID_FoldableAsLoad,
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MCID_MayLoad,
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MCID_MayStore,
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MCID_Predicable,
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MCID_NotDuplicable,
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MCID_UnmodeledSideEffects,
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MCID_Commutable,
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MCID_ConvertibleTo3Addr,
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MCID_UsesCustomInserter,
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MCID_HasPostISelHook,
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MCID_Rematerializable,
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MCID_CheapAsAMove,
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MCID_ExtraSrcRegAllocReq,
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MCID_ExtraDefRegAllocReq,
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MCID_RegSequence,
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MCID_ExtractSubreg,
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MCID_InsertSubreg,
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MCID_Convergent,
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MCID_Add,
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MCID_Trap,
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};
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/// MCInstrDesc - Describe properties that are true of each instruction in the
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/// target description file. This captures information about side effects,
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/// register use and many other things. There is one instance of this struct
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/// for each target instruction class, and the MachineInstr class points to
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/// this struct directly to describe itself.
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typedef struct MCInstrDesc {
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unsigned char NumOperands; // Num of args (may be more if variable_ops)
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const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
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} MCInstrDesc;
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bool MCOperandInfo_isPredicate(const MCOperandInfo *m);
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bool MCOperandInfo_isOptionalDef(const MCOperandInfo *m);
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bool MCOperandInfo_isTiedToOp(const MCOperandInfo *m);
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int MCOperandInfo_getOperandConstraint(const MCInstrDesc *OpInfo,
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unsigned OpNum,
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MCOI_OperandConstraint Constraint);
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#endif
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