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capstone/arch/ARM/ARMGenInstrInfo.inc
Richard Henderson 936dca0e2d Constify backends (#1549) 
* Constify registerinfo.py output

Remove two conditionals separating identical bits of code.
Add "const" markup to MCRegisterDesc and MCRegisterClass.

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify instrinfo-arch.py output

In this case, do not actively strip const.

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the AArch64 backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the EVM backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify M680X backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify M68K backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the Mips backend

The Mips backend has not been regenerated from LLVM recently,
and there are more fixups required than I'd like.  Just apply
the fixes to the tables by hand for now.

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the Sparc backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the TMS320C64x backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the X86 backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the XCore backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify systemregister.py output

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the ARM backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the PowerPC backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the MOS65XX backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the SystemZ backend

The mapping of system register to indexes is easy to
generate read-only.  Since we know the indexes are
between 0 and 31, use uint8_t instead of unsigned.

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the WASM backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify cs.c

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the BPF backend

Signed-off-by: Richard Henderson <rth@twiddle.net>
2019-12-23 20:30:57 +08:00

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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *|
|* Target Instruction Enum Values and Descriptors *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM
enum {
ARM_PHI = 0,
ARM_INLINEASM = 1,
ARM_CFI_INSTRUCTION = 2,
ARM_EH_LABEL = 3,
ARM_GC_LABEL = 4,
ARM_ANNOTATION_LABEL = 5,
ARM_KILL = 6,
ARM_EXTRACT_SUBREG = 7,
ARM_INSERT_SUBREG = 8,
ARM_IMPLICIT_DEF = 9,
ARM_SUBREG_TO_REG = 10,
ARM_COPY_TO_REGCLASS = 11,
ARM_DBG_VALUE = 12,
ARM_DBG_LABEL = 13,
ARM_REG_SEQUENCE = 14,
ARM_COPY = 15,
ARM_BUNDLE = 16,
ARM_LIFETIME_START = 17,
ARM_LIFETIME_END = 18,
ARM_STACKMAP = 19,
ARM_FENTRY_CALL = 20,
ARM_PATCHPOINT = 21,
ARM_LOAD_STACK_GUARD = 22,
ARM_STATEPOINT = 23,
ARM_LOCAL_ESCAPE = 24,
ARM_FAULTING_OP = 25,
ARM_PATCHABLE_OP = 26,
ARM_PATCHABLE_FUNCTION_ENTER = 27,
ARM_PATCHABLE_RET = 28,
ARM_PATCHABLE_FUNCTION_EXIT = 29,
ARM_PATCHABLE_TAIL_CALL = 30,
ARM_PATCHABLE_EVENT_CALL = 31,
ARM_PATCHABLE_TYPED_EVENT_CALL = 32,
ARM_ICALL_BRANCH_FUNNEL = 33,
ARM_G_ADD = 34,
ARM_G_SUB = 35,
ARM_G_MUL = 36,
ARM_G_SDIV = 37,
ARM_G_UDIV = 38,
ARM_G_SREM = 39,
ARM_G_UREM = 40,
ARM_G_AND = 41,
ARM_G_OR = 42,
ARM_G_XOR = 43,
ARM_G_IMPLICIT_DEF = 44,
ARM_G_PHI = 45,
ARM_G_FRAME_INDEX = 46,
ARM_G_GLOBAL_VALUE = 47,
ARM_G_EXTRACT = 48,
ARM_G_UNMERGE_VALUES = 49,
ARM_G_INSERT = 50,
ARM_G_MERGE_VALUES = 51,
ARM_G_PTRTOINT = 52,
ARM_G_INTTOPTR = 53,
ARM_G_BITCAST = 54,
ARM_G_LOAD = 55,
ARM_G_SEXTLOAD = 56,
ARM_G_ZEXTLOAD = 57,
ARM_G_STORE = 58,
ARM_G_ATOMIC_CMPXCHG_WITH_SUCCESS = 59,
ARM_G_ATOMIC_CMPXCHG = 60,
ARM_G_ATOMICRMW_XCHG = 61,
ARM_G_ATOMICRMW_ADD = 62,
ARM_G_ATOMICRMW_SUB = 63,
ARM_G_ATOMICRMW_AND = 64,
ARM_G_ATOMICRMW_NAND = 65,
ARM_G_ATOMICRMW_OR = 66,
ARM_G_ATOMICRMW_XOR = 67,
ARM_G_ATOMICRMW_MAX = 68,
ARM_G_ATOMICRMW_MIN = 69,
ARM_G_ATOMICRMW_UMAX = 70,
ARM_G_ATOMICRMW_UMIN = 71,
ARM_G_BRCOND = 72,
ARM_G_BRINDIRECT = 73,
ARM_G_INTRINSIC = 74,
ARM_G_INTRINSIC_W_SIDE_EFFECTS = 75,
ARM_G_ANYEXT = 76,
ARM_G_TRUNC = 77,
ARM_G_CONSTANT = 78,
ARM_G_FCONSTANT = 79,
ARM_G_VASTART = 80,
ARM_G_VAARG = 81,
ARM_G_SEXT = 82,
ARM_G_ZEXT = 83,
ARM_G_SHL = 84,
ARM_G_LSHR = 85,
ARM_G_ASHR = 86,
ARM_G_ICMP = 87,
ARM_G_FCMP = 88,
ARM_G_SELECT = 89,
ARM_G_UADDE = 90,
ARM_G_USUBE = 91,
ARM_G_SADDO = 92,
ARM_G_SSUBO = 93,
ARM_G_UMULO = 94,
ARM_G_SMULO = 95,
ARM_G_UMULH = 96,
ARM_G_SMULH = 97,
ARM_G_FADD = 98,
ARM_G_FSUB = 99,
ARM_G_FMUL = 100,
ARM_G_FMA = 101,
ARM_G_FDIV = 102,
ARM_G_FREM = 103,
ARM_G_FPOW = 104,
ARM_G_FEXP = 105,
ARM_G_FEXP2 = 106,
ARM_G_FLOG = 107,
ARM_G_FLOG2 = 108,
ARM_G_FNEG = 109,
ARM_G_FPEXT = 110,
ARM_G_FPTRUNC = 111,
ARM_G_FPTOSI = 112,
ARM_G_FPTOUI = 113,
ARM_G_SITOFP = 114,
ARM_G_UITOFP = 115,
ARM_G_FABS = 116,
ARM_G_GEP = 117,
ARM_G_PTR_MASK = 118,
ARM_G_BR = 119,
ARM_G_INSERT_VECTOR_ELT = 120,
ARM_G_EXTRACT_VECTOR_ELT = 121,
ARM_G_SHUFFLE_VECTOR = 122,
ARM_G_BSWAP = 123,
ARM_G_ADDRSPACE_CAST = 124,
ARM_G_BLOCK_ADDR = 125,
ARM_ABS = 126,
ARM_ADDSri = 127,
ARM_ADDSrr = 128,
ARM_ADDSrsi = 129,
ARM_ADDSrsr = 130,
ARM_ADJCALLSTACKDOWN = 131,
ARM_ADJCALLSTACKUP = 132,
ARM_ASRi = 133,
ARM_ASRr = 134,
ARM_B = 135,
ARM_BCCZi64 = 136,
ARM_BCCi64 = 137,
ARM_BMOVPCB_CALL = 138,
ARM_BMOVPCRX_CALL = 139,
ARM_BR_JTadd = 140,
ARM_BR_JTm_i12 = 141,
ARM_BR_JTm_rs = 142,
ARM_BR_JTr = 143,
ARM_BX_CALL = 144,
ARM_CMP_SWAP_16 = 145,
ARM_CMP_SWAP_32 = 146,
ARM_CMP_SWAP_64 = 147,
ARM_CMP_SWAP_8 = 148,
ARM_CONSTPOOL_ENTRY = 149,
ARM_COPY_STRUCT_BYVAL_I32 = 150,
ARM_CompilerBarrier = 151,
ARM_ITasm = 152,
ARM_Int_eh_sjlj_dispatchsetup = 153,
ARM_Int_eh_sjlj_setup_dispatch = 157,
ARM_JUMPTABLE_ADDRS = 158,
ARM_JUMPTABLE_INSTS = 159,
ARM_JUMPTABLE_TBB = 160,
ARM_JUMPTABLE_TBH = 161,
ARM_LDMIA_RET = 162,
ARM_LDRBT_POST = 163,
ARM_LDRConstPool = 164,
ARM_LDRLIT_ga_abs = 165,
ARM_LDRLIT_ga_pcrel = 166,
ARM_LDRLIT_ga_pcrel_ldr = 167,
ARM_LDRT_POST = 168,
ARM_LEApcrel = 169,
ARM_LEApcrelJT = 170,
ARM_LSLi = 171,
ARM_LSLr = 172,
ARM_LSRi = 173,
ARM_LSRr = 174,
ARM_MEMCPY = 175,
ARM_MLAv5 = 176,
ARM_MOVCCi = 177,
ARM_MOVCCi16 = 178,
ARM_MOVCCi32imm = 179,
ARM_MOVCCr = 180,
ARM_MOVCCsi = 181,
ARM_MOVCCsr = 182,
ARM_MOVPCRX = 183,
ARM_MOVTi16_ga_pcrel = 184,
ARM_MOV_ga_pcrel = 185,
ARM_MOV_ga_pcrel_ldr = 186,
ARM_MOVi16_ga_pcrel = 187,
ARM_MOVi32imm = 188,
ARM_MOVsra_flag = 189,
ARM_MOVsrl_flag = 190,
ARM_MULv5 = 191,
ARM_MVNCCi = 192,
ARM_PICADD = 193,
ARM_PICLDR = 194,
ARM_PICLDRB = 195,
ARM_PICLDRH = 196,
ARM_PICLDRSB = 197,
ARM_PICLDRSH = 198,
ARM_PICSTR = 199,
ARM_PICSTRB = 200,
ARM_PICSTRH = 201,
ARM_RORi = 202,
ARM_RORr = 203,
ARM_RRX = 204,
ARM_RRXi = 205,
ARM_RSBSri = 206,
ARM_RSBSrsi = 207,
ARM_RSBSrsr = 208,
ARM_SMLALv5 = 209,
ARM_SMULLv5 = 210,
ARM_SPACE = 211,
ARM_STRBT_POST = 212,
ARM_STRBi_preidx = 213,
ARM_STRBr_preidx = 214,
ARM_STRH_preidx = 215,
ARM_STRT_POST = 216,
ARM_STRi_preidx = 217,
ARM_STRr_preidx = 218,
ARM_SUBS_PC_LR = 219,
ARM_SUBSri = 220,
ARM_SUBSrr = 221,
ARM_SUBSrsi = 222,
ARM_SUBSrsr = 223,
ARM_TAILJMPd = 224,
ARM_TAILJMPr = 225,
ARM_TAILJMPr4 = 226,
ARM_TCRETURNdi = 227,
ARM_TCRETURNri = 228,
ARM_TPsoft = 229,
ARM_UMLALv5 = 230,
ARM_UMULLv5 = 231,
ARM_VLD1LNdAsm_16 = 232,
ARM_VLD1LNdAsm_32 = 233,
ARM_VLD1LNdAsm_8 = 234,
ARM_VLD1LNdWB_fixed_Asm_16 = 235,
ARM_VLD1LNdWB_fixed_Asm_32 = 236,
ARM_VLD1LNdWB_fixed_Asm_8 = 237,
ARM_VLD1LNdWB_register_Asm_16 = 238,
ARM_VLD1LNdWB_register_Asm_32 = 239,
ARM_VLD1LNdWB_register_Asm_8 = 240,
ARM_VLD2LNdAsm_16 = 241,
ARM_VLD2LNdAsm_32 = 242,
ARM_VLD2LNdAsm_8 = 243,
ARM_VLD2LNdWB_fixed_Asm_16 = 244,
ARM_VLD2LNdWB_fixed_Asm_32 = 245,
ARM_VLD2LNdWB_fixed_Asm_8 = 246,
ARM_VLD2LNdWB_register_Asm_16 = 247,
ARM_VLD2LNdWB_register_Asm_32 = 248,
ARM_VLD2LNdWB_register_Asm_8 = 249,
ARM_VLD2LNqAsm_16 = 250,
ARM_VLD2LNqAsm_32 = 251,
ARM_VLD2LNqWB_fixed_Asm_16 = 252,
ARM_VLD2LNqWB_fixed_Asm_32 = 253,
ARM_VLD2LNqWB_register_Asm_16 = 254,
ARM_VLD2LNqWB_register_Asm_32 = 255,
ARM_VLD3DUPdAsm_16 = 256,
ARM_VLD3DUPdAsm_32 = 257,
ARM_VLD3DUPdAsm_8 = 258,
ARM_VLD3DUPdWB_fixed_Asm_16 = 259,
ARM_VLD3DUPdWB_fixed_Asm_32 = 260,
ARM_VLD3DUPdWB_fixed_Asm_8 = 261,
ARM_VLD3DUPdWB_register_Asm_16 = 262,
ARM_VLD3DUPdWB_register_Asm_32 = 263,
ARM_VLD3DUPdWB_register_Asm_8 = 264,
ARM_VLD3DUPqAsm_16 = 265,
ARM_VLD3DUPqAsm_32 = 266,
ARM_VLD3DUPqAsm_8 = 267,
ARM_VLD3DUPqWB_fixed_Asm_16 = 268,
ARM_VLD3DUPqWB_fixed_Asm_32 = 269,
ARM_VLD3DUPqWB_fixed_Asm_8 = 270,
ARM_VLD3DUPqWB_register_Asm_16 = 271,
ARM_VLD3DUPqWB_register_Asm_32 = 272,
ARM_VLD3DUPqWB_register_Asm_8 = 273,
ARM_VLD3LNdAsm_16 = 274,
ARM_VLD3LNdAsm_32 = 275,
ARM_VLD3LNdAsm_8 = 276,
ARM_VLD3LNdWB_fixed_Asm_16 = 277,
ARM_VLD3LNdWB_fixed_Asm_32 = 278,
ARM_VLD3LNdWB_fixed_Asm_8 = 279,
ARM_VLD3LNdWB_register_Asm_16 = 280,
ARM_VLD3LNdWB_register_Asm_32 = 281,
ARM_VLD3LNdWB_register_Asm_8 = 282,
ARM_VLD3LNqAsm_16 = 283,
ARM_VLD3LNqAsm_32 = 284,
ARM_VLD3LNqWB_fixed_Asm_16 = 285,
ARM_VLD3LNqWB_fixed_Asm_32 = 286,
ARM_VLD3LNqWB_register_Asm_16 = 287,
ARM_VLD3LNqWB_register_Asm_32 = 288,
ARM_VLD3dAsm_16 = 289,
ARM_VLD3dAsm_32 = 290,
ARM_VLD3dAsm_8 = 291,
ARM_VLD3dWB_fixed_Asm_16 = 292,
ARM_VLD3dWB_fixed_Asm_32 = 293,
ARM_VLD3dWB_fixed_Asm_8 = 294,
ARM_VLD3dWB_register_Asm_16 = 295,
ARM_VLD3dWB_register_Asm_32 = 296,
ARM_VLD3dWB_register_Asm_8 = 297,
ARM_VLD3qAsm_16 = 298,
ARM_VLD3qAsm_32 = 299,
ARM_VLD3qAsm_8 = 300,
ARM_VLD3qWB_fixed_Asm_16 = 301,
ARM_VLD3qWB_fixed_Asm_32 = 302,
ARM_VLD3qWB_fixed_Asm_8 = 303,
ARM_VLD3qWB_register_Asm_16 = 304,
ARM_VLD3qWB_register_Asm_32 = 305,
ARM_VLD3qWB_register_Asm_8 = 306,
ARM_VLD4DUPdAsm_16 = 307,
ARM_VLD4DUPdAsm_32 = 308,
ARM_VLD4DUPdAsm_8 = 309,
ARM_VLD4DUPdWB_fixed_Asm_16 = 310,
ARM_VLD4DUPdWB_fixed_Asm_32 = 311,
ARM_VLD4DUPdWB_fixed_Asm_8 = 312,
ARM_VLD4DUPdWB_register_Asm_16 = 313,
ARM_VLD4DUPdWB_register_Asm_32 = 314,
ARM_VLD4DUPdWB_register_Asm_8 = 315,
ARM_VLD4DUPqAsm_16 = 316,
ARM_VLD4DUPqAsm_32 = 317,
ARM_VLD4DUPqAsm_8 = 318,
ARM_VLD4DUPqWB_fixed_Asm_16 = 319,
ARM_VLD4DUPqWB_fixed_Asm_32 = 320,
ARM_VLD4DUPqWB_fixed_Asm_8 = 321,
ARM_VLD4DUPqWB_register_Asm_16 = 322,
ARM_VLD4DUPqWB_register_Asm_32 = 323,
ARM_VLD4DUPqWB_register_Asm_8 = 324,
ARM_VLD4LNdAsm_16 = 325,
ARM_VLD4LNdAsm_32 = 326,
ARM_VLD4LNdAsm_8 = 327,
ARM_VLD4LNdWB_fixed_Asm_16 = 328,
ARM_VLD4LNdWB_fixed_Asm_32 = 329,
ARM_VLD4LNdWB_fixed_Asm_8 = 330,
ARM_VLD4LNdWB_register_Asm_16 = 331,
ARM_VLD4LNdWB_register_Asm_32 = 332,
ARM_VLD4LNdWB_register_Asm_8 = 333,
ARM_VLD4LNqAsm_16 = 334,
ARM_VLD4LNqAsm_32 = 335,
ARM_VLD4LNqWB_fixed_Asm_16 = 336,
ARM_VLD4LNqWB_fixed_Asm_32 = 337,
ARM_VLD4LNqWB_register_Asm_16 = 338,
ARM_VLD4LNqWB_register_Asm_32 = 339,
ARM_VLD4dAsm_16 = 340,
ARM_VLD4dAsm_32 = 341,
ARM_VLD4dAsm_8 = 342,
ARM_VLD4dWB_fixed_Asm_16 = 343,
ARM_VLD4dWB_fixed_Asm_32 = 344,
ARM_VLD4dWB_fixed_Asm_8 = 345,
ARM_VLD4dWB_register_Asm_16 = 346,
ARM_VLD4dWB_register_Asm_32 = 347,
ARM_VLD4dWB_register_Asm_8 = 348,
ARM_VLD4qAsm_16 = 349,
ARM_VLD4qAsm_32 = 350,
ARM_VLD4qAsm_8 = 351,
ARM_VLD4qWB_fixed_Asm_16 = 352,
ARM_VLD4qWB_fixed_Asm_32 = 353,
ARM_VLD4qWB_fixed_Asm_8 = 354,
ARM_VLD4qWB_register_Asm_16 = 355,
ARM_VLD4qWB_register_Asm_32 = 356,
ARM_VLD4qWB_register_Asm_8 = 357,
ARM_VMOVD0 = 358,
ARM_VMOVDcc = 359,
ARM_VMOVQ0 = 360,
ARM_VMOVScc = 361,
ARM_VST1LNdAsm_16 = 362,
ARM_VST1LNdAsm_32 = 363,
ARM_VST1LNdAsm_8 = 364,
ARM_VST1LNdWB_fixed_Asm_16 = 365,
ARM_VST1LNdWB_fixed_Asm_32 = 366,
ARM_VST1LNdWB_fixed_Asm_8 = 367,
ARM_VST1LNdWB_register_Asm_16 = 368,
ARM_VST1LNdWB_register_Asm_32 = 369,
ARM_VST1LNdWB_register_Asm_8 = 370,
ARM_VST2LNdAsm_16 = 371,
ARM_VST2LNdAsm_32 = 372,
ARM_VST2LNdAsm_8 = 373,
ARM_VST2LNdWB_fixed_Asm_16 = 374,
ARM_VST2LNdWB_fixed_Asm_32 = 375,
ARM_VST2LNdWB_fixed_Asm_8 = 376,
ARM_VST2LNdWB_register_Asm_16 = 377,
ARM_VST2LNdWB_register_Asm_32 = 378,
ARM_VST2LNdWB_register_Asm_8 = 379,
ARM_VST2LNqAsm_16 = 380,
ARM_VST2LNqAsm_32 = 381,
ARM_VST2LNqWB_fixed_Asm_16 = 382,
ARM_VST2LNqWB_fixed_Asm_32 = 383,
ARM_VST2LNqWB_register_Asm_16 = 384,
ARM_VST2LNqWB_register_Asm_32 = 385,
ARM_VST3LNdAsm_16 = 386,
ARM_VST3LNdAsm_32 = 387,
ARM_VST3LNdAsm_8 = 388,
ARM_VST3LNdWB_fixed_Asm_16 = 389,
ARM_VST3LNdWB_fixed_Asm_32 = 390,
ARM_VST3LNdWB_fixed_Asm_8 = 391,
ARM_VST3LNdWB_register_Asm_16 = 392,
ARM_VST3LNdWB_register_Asm_32 = 393,
ARM_VST3LNdWB_register_Asm_8 = 394,
ARM_VST3LNqAsm_16 = 395,
ARM_VST3LNqAsm_32 = 396,
ARM_VST3LNqWB_fixed_Asm_16 = 397,
ARM_VST3LNqWB_fixed_Asm_32 = 398,
ARM_VST3LNqWB_register_Asm_16 = 399,
ARM_VST3LNqWB_register_Asm_32 = 400,
ARM_VST3dAsm_16 = 401,
ARM_VST3dAsm_32 = 402,
ARM_VST3dAsm_8 = 403,
ARM_VST3dWB_fixed_Asm_16 = 404,
ARM_VST3dWB_fixed_Asm_32 = 405,
ARM_VST3dWB_fixed_Asm_8 = 406,
ARM_VST3dWB_register_Asm_16 = 407,
ARM_VST3dWB_register_Asm_32 = 408,
ARM_VST3dWB_register_Asm_8 = 409,
ARM_VST3qAsm_16 = 410,
ARM_VST3qAsm_32 = 411,
ARM_VST3qAsm_8 = 412,
ARM_VST3qWB_fixed_Asm_16 = 413,
ARM_VST3qWB_fixed_Asm_32 = 414,
ARM_VST3qWB_fixed_Asm_8 = 415,
ARM_VST3qWB_register_Asm_16 = 416,
ARM_VST3qWB_register_Asm_32 = 417,
ARM_VST3qWB_register_Asm_8 = 418,
ARM_VST4LNdAsm_16 = 419,
ARM_VST4LNdAsm_32 = 420,
ARM_VST4LNdAsm_8 = 421,
ARM_VST4LNdWB_fixed_Asm_16 = 422,
ARM_VST4LNdWB_fixed_Asm_32 = 423,
ARM_VST4LNdWB_fixed_Asm_8 = 424,
ARM_VST4LNdWB_register_Asm_16 = 425,
ARM_VST4LNdWB_register_Asm_32 = 426,
ARM_VST4LNdWB_register_Asm_8 = 427,
ARM_VST4LNqAsm_16 = 428,
ARM_VST4LNqAsm_32 = 429,
ARM_VST4LNqWB_fixed_Asm_16 = 430,
ARM_VST4LNqWB_fixed_Asm_32 = 431,
ARM_VST4LNqWB_register_Asm_16 = 432,
ARM_VST4LNqWB_register_Asm_32 = 433,
ARM_VST4dAsm_16 = 434,
ARM_VST4dAsm_32 = 435,
ARM_VST4dAsm_8 = 436,
ARM_VST4dWB_fixed_Asm_16 = 437,
ARM_VST4dWB_fixed_Asm_32 = 438,
ARM_VST4dWB_fixed_Asm_8 = 439,
ARM_VST4dWB_register_Asm_16 = 440,
ARM_VST4dWB_register_Asm_32 = 441,
ARM_VST4dWB_register_Asm_8 = 442,
ARM_VST4qAsm_16 = 443,
ARM_VST4qAsm_32 = 444,
ARM_VST4qAsm_8 = 445,
ARM_VST4qWB_fixed_Asm_16 = 446,
ARM_VST4qWB_fixed_Asm_32 = 447,
ARM_VST4qWB_fixed_Asm_8 = 448,
ARM_VST4qWB_register_Asm_16 = 449,
ARM_VST4qWB_register_Asm_32 = 450,
ARM_VST4qWB_register_Asm_8 = 451,
ARM_t2ABS = 454,
ARM_t2ADDSri = 455,
ARM_t2ADDSrr = 456,
ARM_t2ADDSrs = 457,
ARM_t2BR_JT = 458,
ARM_t2LDMIA_RET = 459,
ARM_t2LDRBpcrel = 460,
ARM_t2LDRConstPool = 461,
ARM_t2LDRHpcrel = 462,
ARM_t2LDRSBpcrel = 463,
ARM_t2LDRSHpcrel = 464,
ARM_t2LDRpci_pic = 465,
ARM_t2LDRpcrel = 466,
ARM_t2LEApcrel = 467,
ARM_t2LEApcrelJT = 468,
ARM_t2MOVCCasr = 469,
ARM_t2MOVCCi = 470,
ARM_t2MOVCCi16 = 471,
ARM_t2MOVCCi32imm = 472,
ARM_t2MOVCClsl = 473,
ARM_t2MOVCClsr = 474,
ARM_t2MOVCCr = 475,
ARM_t2MOVCCror = 476,
ARM_t2MOVSsi = 477,
ARM_t2MOVSsr = 478,
ARM_t2MOVTi16_ga_pcrel = 479,
ARM_t2MOV_ga_pcrel = 480,
ARM_t2MOVi16_ga_pcrel = 481,
ARM_t2MOVi32imm = 482,
ARM_t2MOVsi = 483,
ARM_t2MOVsr = 484,
ARM_t2MVNCCi = 485,
ARM_t2RSBSri = 486,
ARM_t2RSBSrs = 487,
ARM_t2STRB_preidx = 488,
ARM_t2STRH_preidx = 489,
ARM_t2STR_preidx = 490,
ARM_t2SUBSri = 491,
ARM_t2SUBSrr = 492,
ARM_t2SUBSrs = 493,
ARM_t2TBB_JT = 494,
ARM_t2TBH_JT = 495,
ARM_tADCS = 496,
ARM_tADDSi3 = 497,
ARM_tADDSi8 = 498,
ARM_tADDSrr = 499,
ARM_tADDframe = 500,
ARM_tADJCALLSTACKDOWN = 501,
ARM_tADJCALLSTACKUP = 502,
ARM_tBRIND = 503,
ARM_tBR_JTr = 504,
ARM_tBX_CALL = 505,
ARM_tBX_RET = 506,
ARM_tBX_RET_vararg = 507,
ARM_tBfar = 508,
ARM_tLDMIA_UPD = 509,
ARM_tLDRConstPool = 510,
ARM_tLDRLIT_ga_abs = 511,
ARM_tLDRLIT_ga_pcrel = 512,
ARM_tLDR_postidx = 513,
ARM_tLDRpci_pic = 514,
ARM_tLEApcrel = 515,
ARM_tLEApcrelJT = 516,
ARM_tMOVCCr_pseudo = 517,
ARM_tPOP_RET = 518,
ARM_tSBCS = 519,
ARM_tSUBSi3 = 520,
ARM_tSUBSi8 = 521,
ARM_tSUBSrr = 522,
ARM_tTAILJMPd = 523,
ARM_tTAILJMPdND = 524,
ARM_tTAILJMPr = 525,
ARM_tTBB_JT = 526,
ARM_tTBH_JT = 527,
ARM_tTPsoft = 528,
ARM_ADCri = 529,
ARM_ADCrr = 530,
ARM_ADCrsi = 531,
ARM_ADCrsr = 532,
ARM_ADDri = 533,
ARM_ADDrr = 534,
ARM_ADDrsi = 535,
ARM_ADDrsr = 536,
ARM_ADR = 537,
ARM_AESD = 538,
ARM_AESE = 539,
ARM_AESIMC = 540,
ARM_AESMC = 541,
ARM_ANDri = 542,
ARM_ANDrr = 543,
ARM_ANDrsi = 544,
ARM_ANDrsr = 545,
ARM_BFC = 546,
ARM_BFI = 547,
ARM_BICri = 548,
ARM_BICrr = 549,
ARM_BICrsi = 550,
ARM_BICrsr = 551,
ARM_BKPT = 552,
ARM_BL = 553,
ARM_BLX = 554,
ARM_BLX_pred = 555,
ARM_BLXi = 556,
ARM_BL_pred = 557,
ARM_BX = 558,
ARM_BXJ = 559,
ARM_BX_RET = 560,
ARM_BX_pred = 561,
ARM_Bcc = 562,
ARM_CDP = 563,
ARM_CDP2 = 564,
ARM_CLREX = 565,
ARM_CLZ = 566,
ARM_CMNri = 567,
ARM_CMNzrr = 568,
ARM_CMNzrsi = 569,
ARM_CMNzrsr = 570,
ARM_CMPri = 571,
ARM_CMPrr = 572,
ARM_CMPrsi = 573,
ARM_CMPrsr = 574,
ARM_CPS1p = 575,
ARM_CPS2p = 576,
ARM_CPS3p = 577,
ARM_CRC32B = 578,
ARM_CRC32CB = 579,
ARM_CRC32CH = 580,
ARM_CRC32CW = 581,
ARM_CRC32H = 582,
ARM_CRC32W = 583,
ARM_DBG = 584,
ARM_DMB = 585,
ARM_DSB = 586,
ARM_EORri = 587,
ARM_EORrr = 588,
ARM_EORrsi = 589,
ARM_EORrsr = 590,
ARM_ERET = 591,
ARM_FCONSTD = 592,
ARM_FCONSTH = 593,
ARM_FCONSTS = 594,
ARM_FLDMXDB_UPD = 595,
ARM_FLDMXIA = 596,
ARM_FLDMXIA_UPD = 597,
ARM_FMSTAT = 598,
ARM_FSTMXDB_UPD = 599,
ARM_FSTMXIA = 600,
ARM_FSTMXIA_UPD = 601,
ARM_HINT = 602,
ARM_HLT = 603,
ARM_HVC = 604,
ARM_ISB = 605,
ARM_LDA = 606,
ARM_LDAB = 607,
ARM_LDAEX = 608,
ARM_LDAEXB = 609,
ARM_LDAEXD = 610,
ARM_LDAEXH = 611,
ARM_LDAH = 612,
ARM_LDC2L_OFFSET = 613,
ARM_LDC2L_OPTION = 614,
ARM_LDC2L_POST = 615,
ARM_LDC2L_PRE = 616,
ARM_LDC2_OFFSET = 617,
ARM_LDC2_OPTION = 618,
ARM_LDC2_POST = 619,
ARM_LDC2_PRE = 620,
ARM_LDCL_OFFSET = 621,
ARM_LDCL_OPTION = 622,
ARM_LDCL_POST = 623,
ARM_LDCL_PRE = 624,
ARM_LDC_OFFSET = 625,
ARM_LDC_OPTION = 626,
ARM_LDC_POST = 627,
ARM_LDC_PRE = 628,
ARM_LDMDA = 629,
ARM_LDMDA_UPD = 630,
ARM_LDMDB = 631,
ARM_LDMDB_UPD = 632,
ARM_LDMIA = 633,
ARM_LDMIA_UPD = 634,
ARM_LDMIB = 635,
ARM_LDMIB_UPD = 636,
ARM_LDRBT_POST_IMM = 637,
ARM_LDRBT_POST_REG = 638,
ARM_LDRB_POST_IMM = 639,
ARM_LDRB_POST_REG = 640,
ARM_LDRB_PRE_IMM = 641,
ARM_LDRB_PRE_REG = 642,
ARM_LDRBi12 = 643,
ARM_LDRBrs = 644,
ARM_LDRD = 645,
ARM_LDRD_POST = 646,
ARM_LDRD_PRE = 647,
ARM_LDREX = 648,
ARM_LDREXB = 649,
ARM_LDREXD = 650,
ARM_LDREXH = 651,
ARM_LDRH = 652,
ARM_LDRHTi = 653,
ARM_LDRHTr = 654,
ARM_LDRH_POST = 655,
ARM_LDRH_PRE = 656,
ARM_LDRSB = 657,
ARM_LDRSBTi = 658,
ARM_LDRSBTr = 659,
ARM_LDRSB_POST = 660,
ARM_LDRSB_PRE = 661,
ARM_LDRSH = 662,
ARM_LDRSHTi = 663,
ARM_LDRSHTr = 664,
ARM_LDRSH_POST = 665,
ARM_LDRSH_PRE = 666,
ARM_LDRT_POST_IMM = 667,
ARM_LDRT_POST_REG = 668,
ARM_LDR_POST_IMM = 669,
ARM_LDR_POST_REG = 670,
ARM_LDR_PRE_IMM = 671,
ARM_LDR_PRE_REG = 672,
ARM_LDRcp = 673,
ARM_LDRi12 = 674,
ARM_LDRrs = 675,
ARM_MCR = 676,
ARM_MCR2 = 677,
ARM_MCRR = 678,
ARM_MCRR2 = 679,
ARM_MLA = 680,
ARM_MLS = 681,
ARM_MOVPCLR = 682,
ARM_MOVTi16 = 683,
ARM_MOVi = 684,
ARM_MOVi16 = 685,
ARM_MOVr = 686,
ARM_MOVr_TC = 687,
ARM_MOVsi = 688,
ARM_MOVsr = 689,
ARM_MRC = 690,
ARM_MRC2 = 691,
ARM_MRRC = 692,
ARM_MRRC2 = 693,
ARM_MRS = 694,
ARM_MRSbanked = 695,
ARM_MRSsys = 696,
ARM_MSR = 697,
ARM_MSRbanked = 698,
ARM_MSRi = 699,
ARM_MUL = 700,
ARM_MVNi = 701,
ARM_MVNr = 702,
ARM_MVNsi = 703,
ARM_MVNsr = 704,
ARM_ORRri = 705,
ARM_ORRrr = 706,
ARM_ORRrsi = 707,
ARM_ORRrsr = 708,
ARM_PKHBT = 709,
ARM_PKHTB = 710,
ARM_PLDWi12 = 711,
ARM_PLDWrs = 712,
ARM_PLDi12 = 713,
ARM_PLDrs = 714,
ARM_PLIi12 = 715,
ARM_PLIrs = 716,
ARM_QADD = 717,
ARM_QADD16 = 718,
ARM_QADD8 = 719,
ARM_QASX = 720,
ARM_QDADD = 721,
ARM_QDSUB = 722,
ARM_QSAX = 723,
ARM_QSUB = 724,
ARM_QSUB16 = 725,
ARM_QSUB8 = 726,
ARM_RBIT = 727,
ARM_REV = 728,
ARM_REV16 = 729,
ARM_REVSH = 730,
ARM_RFEDA = 731,
ARM_RFEDA_UPD = 732,
ARM_RFEDB = 733,
ARM_RFEDB_UPD = 734,
ARM_RFEIA = 735,
ARM_RFEIA_UPD = 736,
ARM_RFEIB = 737,
ARM_RFEIB_UPD = 738,
ARM_RSBri = 739,
ARM_RSBrr = 740,
ARM_RSBrsi = 741,
ARM_RSBrsr = 742,
ARM_RSCri = 743,
ARM_RSCrr = 744,
ARM_RSCrsi = 745,
ARM_RSCrsr = 746,
ARM_SADD16 = 747,
ARM_SADD8 = 748,
ARM_SASX = 749,
ARM_SBCri = 750,
ARM_SBCrr = 751,
ARM_SBCrsi = 752,
ARM_SBCrsr = 753,
ARM_SBFX = 754,
ARM_SDIV = 755,
ARM_SEL = 756,
ARM_SETEND = 757,
ARM_SETPAN = 758,
ARM_SHA1C = 759,
ARM_SHA1H = 760,
ARM_SHA1M = 761,
ARM_SHA1P = 762,
ARM_SHA1SU0 = 763,
ARM_SHA1SU1 = 764,
ARM_SHA256H = 765,
ARM_SHA256H2 = 766,
ARM_SHA256SU0 = 767,
ARM_SHA256SU1 = 768,
ARM_SHADD16 = 769,
ARM_SHADD8 = 770,
ARM_SHASX = 771,
ARM_SHSAX = 772,
ARM_SHSUB16 = 773,
ARM_SHSUB8 = 774,
ARM_SMC = 775,
ARM_SMLABB = 776,
ARM_SMLABT = 777,
ARM_SMLAD = 778,
ARM_SMLADX = 779,
ARM_SMLAL = 780,
ARM_SMLALBB = 781,
ARM_SMLALBT = 782,
ARM_SMLALD = 783,
ARM_SMLALDX = 784,
ARM_SMLALTB = 785,
ARM_SMLALTT = 786,
ARM_SMLATB = 787,
ARM_SMLATT = 788,
ARM_SMLAWB = 789,
ARM_SMLAWT = 790,
ARM_SMLSD = 791,
ARM_SMLSDX = 792,
ARM_SMLSLD = 793,
ARM_SMLSLDX = 794,
ARM_SMMLA = 795,
ARM_SMMLAR = 796,
ARM_SMMLS = 797,
ARM_SMMLSR = 798,
ARM_SMMUL = 799,
ARM_SMMULR = 800,
ARM_SMUAD = 801,
ARM_SMUADX = 802,
ARM_SMULBB = 803,
ARM_SMULBT = 804,
ARM_SMULL = 805,
ARM_SMULTB = 806,
ARM_SMULTT = 807,
ARM_SMULWB = 808,
ARM_SMULWT = 809,
ARM_SMUSD = 810,
ARM_SMUSDX = 811,
ARM_SRSDA = 812,
ARM_SRSDA_UPD = 813,
ARM_SRSDB = 814,
ARM_SRSDB_UPD = 815,
ARM_SRSIA = 816,
ARM_SRSIA_UPD = 817,
ARM_SRSIB = 818,
ARM_SRSIB_UPD = 819,
ARM_SSAT = 820,
ARM_SSAT16 = 821,
ARM_SSAX = 822,
ARM_SSUB16 = 823,
ARM_SSUB8 = 824,
ARM_STC2L_OFFSET = 825,
ARM_STC2L_OPTION = 826,
ARM_STC2L_POST = 827,
ARM_STC2L_PRE = 828,
ARM_STC2_OFFSET = 829,
ARM_STC2_OPTION = 830,
ARM_STC2_POST = 831,
ARM_STC2_PRE = 832,
ARM_STCL_OFFSET = 833,
ARM_STCL_OPTION = 834,
ARM_STCL_POST = 835,
ARM_STCL_PRE = 836,
ARM_STC_OFFSET = 837,
ARM_STC_OPTION = 838,
ARM_STC_POST = 839,
ARM_STC_PRE = 840,
ARM_STL = 841,
ARM_STLB = 842,
ARM_STLEX = 843,
ARM_STLEXB = 844,
ARM_STLEXD = 845,
ARM_STLEXH = 846,
ARM_STLH = 847,
ARM_STMDA = 848,
ARM_STMDA_UPD = 849,
ARM_STMDB = 850,
ARM_STMDB_UPD = 851,
ARM_STMIA = 852,
ARM_STMIA_UPD = 853,
ARM_STMIB = 854,
ARM_STMIB_UPD = 855,
ARM_STRBT_POST_IMM = 856,
ARM_STRBT_POST_REG = 857,
ARM_STRB_POST_IMM = 858,
ARM_STRB_POST_REG = 859,
ARM_STRB_PRE_IMM = 860,
ARM_STRB_PRE_REG = 861,
ARM_STRBi12 = 862,
ARM_STRBrs = 863,
ARM_STRD = 864,
ARM_STRD_POST = 865,
ARM_STRD_PRE = 866,
ARM_STREX = 867,
ARM_STREXB = 868,
ARM_STREXD = 869,
ARM_STREXH = 870,
ARM_STRH = 871,
ARM_STRHTi = 872,
ARM_STRHTr = 873,
ARM_STRH_POST = 874,
ARM_STRH_PRE = 875,
ARM_STRT_POST_IMM = 876,
ARM_STRT_POST_REG = 877,
ARM_STR_POST_IMM = 878,
ARM_STR_POST_REG = 879,
ARM_STR_PRE_IMM = 880,
ARM_STR_PRE_REG = 881,
ARM_STRi12 = 882,
ARM_STRrs = 883,
ARM_SUBri = 884,
ARM_SUBrr = 885,
ARM_SUBrsi = 886,
ARM_SUBrsr = 887,
ARM_SVC = 888,
ARM_SWP = 889,
ARM_SWPB = 890,
ARM_SXTAB = 891,
ARM_SXTAB16 = 892,
ARM_SXTAH = 893,
ARM_SXTB = 894,
ARM_SXTB16 = 895,
ARM_SXTH = 896,
ARM_TEQri = 897,
ARM_TEQrr = 898,
ARM_TEQrsi = 899,
ARM_TEQrsr = 900,
ARM_TRAP = 901,
ARM_TRAPNaCl = 902,
ARM_TSB = 903,
ARM_TSTri = 904,
ARM_TSTrr = 905,
ARM_TSTrsi = 906,
ARM_TSTrsr = 907,
ARM_UADD16 = 908,
ARM_UADD8 = 909,
ARM_UASX = 910,
ARM_UBFX = 911,
ARM_UDF = 912,
ARM_UDIV = 913,
ARM_UHADD16 = 914,
ARM_UHADD8 = 915,
ARM_UHASX = 916,
ARM_UHSAX = 917,
ARM_UHSUB16 = 918,
ARM_UHSUB8 = 919,
ARM_UMAAL = 920,
ARM_UMLAL = 921,
ARM_UMULL = 922,
ARM_UQADD16 = 923,
ARM_UQADD8 = 924,
ARM_UQASX = 925,
ARM_UQSAX = 926,
ARM_UQSUB16 = 927,
ARM_UQSUB8 = 928,
ARM_USAD8 = 929,
ARM_USADA8 = 930,
ARM_USAT = 931,
ARM_USAT16 = 932,
ARM_USAX = 933,
ARM_USUB16 = 934,
ARM_USUB8 = 935,
ARM_UXTAB = 936,
ARM_UXTAB16 = 937,
ARM_UXTAH = 938,
ARM_UXTB = 939,
ARM_UXTB16 = 940,
ARM_UXTH = 941,
ARM_VABALsv2i64 = 942,
ARM_VABALsv4i32 = 943,
ARM_VABALsv8i16 = 944,
ARM_VABALuv2i64 = 945,
ARM_VABALuv4i32 = 946,
ARM_VABALuv8i16 = 947,
ARM_VABAsv16i8 = 948,
ARM_VABAsv2i32 = 949,
ARM_VABAsv4i16 = 950,
ARM_VABAsv4i32 = 951,
ARM_VABAsv8i16 = 952,
ARM_VABAsv8i8 = 953,
ARM_VABAuv16i8 = 954,
ARM_VABAuv2i32 = 955,
ARM_VABAuv4i16 = 956,
ARM_VABAuv4i32 = 957,
ARM_VABAuv8i16 = 958,
ARM_VABAuv8i8 = 959,
ARM_VABDLsv2i64 = 960,
ARM_VABDLsv4i32 = 961,
ARM_VABDLsv8i16 = 962,
ARM_VABDLuv2i64 = 963,
ARM_VABDLuv4i32 = 964,
ARM_VABDLuv8i16 = 965,
ARM_VABDfd = 966,
ARM_VABDfq = 967,
ARM_VABDhd = 968,
ARM_VABDhq = 969,
ARM_VABDsv16i8 = 970,
ARM_VABDsv2i32 = 971,
ARM_VABDsv4i16 = 972,
ARM_VABDsv4i32 = 973,
ARM_VABDsv8i16 = 974,
ARM_VABDsv8i8 = 975,
ARM_VABDuv16i8 = 976,
ARM_VABDuv2i32 = 977,
ARM_VABDuv4i16 = 978,
ARM_VABDuv4i32 = 979,
ARM_VABDuv8i16 = 980,
ARM_VABDuv8i8 = 981,
ARM_VABSD = 982,
ARM_VABSH = 983,
ARM_VABSS = 984,
ARM_VABSfd = 985,
ARM_VABSfq = 986,
ARM_VABShd = 987,
ARM_VABShq = 988,
ARM_VABSv16i8 = 989,
ARM_VABSv2i32 = 990,
ARM_VABSv4i16 = 991,
ARM_VABSv4i32 = 992,
ARM_VABSv8i16 = 993,
ARM_VABSv8i8 = 994,
ARM_VACGEfd = 995,
ARM_VACGEfq = 996,
ARM_VACGEhd = 997,
ARM_VACGEhq = 998,
ARM_VACGTfd = 999,
ARM_VACGTfq = 1000,
ARM_VACGThd = 1001,
ARM_VACGThq = 1002,
ARM_VADDD = 1003,
ARM_VADDH = 1004,
ARM_VADDHNv2i32 = 1005,
ARM_VADDHNv4i16 = 1006,
ARM_VADDHNv8i8 = 1007,
ARM_VADDLsv2i64 = 1008,
ARM_VADDLsv4i32 = 1009,
ARM_VADDLsv8i16 = 1010,
ARM_VADDLuv2i64 = 1011,
ARM_VADDLuv4i32 = 1012,
ARM_VADDLuv8i16 = 1013,
ARM_VADDS = 1014,
ARM_VADDWsv2i64 = 1015,
ARM_VADDWsv4i32 = 1016,
ARM_VADDWsv8i16 = 1017,
ARM_VADDWuv2i64 = 1018,
ARM_VADDWuv4i32 = 1019,
ARM_VADDWuv8i16 = 1020,
ARM_VADDfd = 1021,
ARM_VADDfq = 1022,
ARM_VADDhd = 1023,
ARM_VADDhq = 1024,
ARM_VADDv16i8 = 1025,
ARM_VADDv1i64 = 1026,
ARM_VADDv2i32 = 1027,
ARM_VADDv2i64 = 1028,
ARM_VADDv4i16 = 1029,
ARM_VADDv4i32 = 1030,
ARM_VADDv8i16 = 1031,
ARM_VADDv8i8 = 1032,
ARM_VANDd = 1033,
ARM_VANDq = 1034,
ARM_VBICd = 1035,
ARM_VBICiv2i32 = 1036,
ARM_VBICiv4i16 = 1037,
ARM_VBICiv4i32 = 1038,
ARM_VBICiv8i16 = 1039,
ARM_VBICq = 1040,
ARM_VBIFd = 1041,
ARM_VBIFq = 1042,
ARM_VBITd = 1043,
ARM_VBITq = 1044,
ARM_VBSLd = 1045,
ARM_VBSLq = 1046,
ARM_VCADDv2f32 = 1047,
ARM_VCADDv4f16 = 1048,
ARM_VCADDv4f32 = 1049,
ARM_VCADDv8f16 = 1050,
ARM_VCEQfd = 1051,
ARM_VCEQfq = 1052,
ARM_VCEQhd = 1053,
ARM_VCEQhq = 1054,
ARM_VCEQv16i8 = 1055,
ARM_VCEQv2i32 = 1056,
ARM_VCEQv4i16 = 1057,
ARM_VCEQv4i32 = 1058,
ARM_VCEQv8i16 = 1059,
ARM_VCEQv8i8 = 1060,
ARM_VCEQzv16i8 = 1061,
ARM_VCEQzv2f32 = 1062,
ARM_VCEQzv2i32 = 1063,
ARM_VCEQzv4f16 = 1064,
ARM_VCEQzv4f32 = 1065,
ARM_VCEQzv4i16 = 1066,
ARM_VCEQzv4i32 = 1067,
ARM_VCEQzv8f16 = 1068,
ARM_VCEQzv8i16 = 1069,
ARM_VCEQzv8i8 = 1070,
ARM_VCGEfd = 1071,
ARM_VCGEfq = 1072,
ARM_VCGEhd = 1073,
ARM_VCGEhq = 1074,
ARM_VCGEsv16i8 = 1075,
ARM_VCGEsv2i32 = 1076,
ARM_VCGEsv4i16 = 1077,
ARM_VCGEsv4i32 = 1078,
ARM_VCGEsv8i16 = 1079,
ARM_VCGEsv8i8 = 1080,
ARM_VCGEuv16i8 = 1081,
ARM_VCGEuv2i32 = 1082,
ARM_VCGEuv4i16 = 1083,
ARM_VCGEuv4i32 = 1084,
ARM_VCGEuv8i16 = 1085,
ARM_VCGEuv8i8 = 1086,
ARM_VCGEzv16i8 = 1087,
ARM_VCGEzv2f32 = 1088,
ARM_VCGEzv2i32 = 1089,
ARM_VCGEzv4f16 = 1090,
ARM_VCGEzv4f32 = 1091,
ARM_VCGEzv4i16 = 1092,
ARM_VCGEzv4i32 = 1093,
ARM_VCGEzv8f16 = 1094,
ARM_VCGEzv8i16 = 1095,
ARM_VCGEzv8i8 = 1096,
ARM_VCGTfd = 1097,
ARM_VCGTfq = 1098,
ARM_VCGThd = 1099,
ARM_VCGThq = 1100,
ARM_VCGTsv16i8 = 1101,
ARM_VCGTsv2i32 = 1102,
ARM_VCGTsv4i16 = 1103,
ARM_VCGTsv4i32 = 1104,
ARM_VCGTsv8i16 = 1105,
ARM_VCGTsv8i8 = 1106,
ARM_VCGTuv16i8 = 1107,
ARM_VCGTuv2i32 = 1108,
ARM_VCGTuv4i16 = 1109,
ARM_VCGTuv4i32 = 1110,
ARM_VCGTuv8i16 = 1111,
ARM_VCGTuv8i8 = 1112,
ARM_VCGTzv16i8 = 1113,
ARM_VCGTzv2f32 = 1114,
ARM_VCGTzv2i32 = 1115,
ARM_VCGTzv4f16 = 1116,
ARM_VCGTzv4f32 = 1117,
ARM_VCGTzv4i16 = 1118,
ARM_VCGTzv4i32 = 1119,
ARM_VCGTzv8f16 = 1120,
ARM_VCGTzv8i16 = 1121,
ARM_VCGTzv8i8 = 1122,
ARM_VCLEzv16i8 = 1123,
ARM_VCLEzv2f32 = 1124,
ARM_VCLEzv2i32 = 1125,
ARM_VCLEzv4f16 = 1126,
ARM_VCLEzv4f32 = 1127,
ARM_VCLEzv4i16 = 1128,
ARM_VCLEzv4i32 = 1129,
ARM_VCLEzv8f16 = 1130,
ARM_VCLEzv8i16 = 1131,
ARM_VCLEzv8i8 = 1132,
ARM_VCLSv16i8 = 1133,
ARM_VCLSv2i32 = 1134,
ARM_VCLSv4i16 = 1135,
ARM_VCLSv4i32 = 1136,
ARM_VCLSv8i16 = 1137,
ARM_VCLSv8i8 = 1138,
ARM_VCLTzv16i8 = 1139,
ARM_VCLTzv2f32 = 1140,
ARM_VCLTzv2i32 = 1141,
ARM_VCLTzv4f16 = 1142,
ARM_VCLTzv4f32 = 1143,
ARM_VCLTzv4i16 = 1144,
ARM_VCLTzv4i32 = 1145,
ARM_VCLTzv8f16 = 1146,
ARM_VCLTzv8i16 = 1147,
ARM_VCLTzv8i8 = 1148,
ARM_VCLZv16i8 = 1149,
ARM_VCLZv2i32 = 1150,
ARM_VCLZv4i16 = 1151,
ARM_VCLZv4i32 = 1152,
ARM_VCLZv8i16 = 1153,
ARM_VCLZv8i8 = 1154,
ARM_VCMLAv2f32 = 1155,
ARM_VCMLAv2f32_indexed = 1156,
ARM_VCMLAv4f16 = 1157,
ARM_VCMLAv4f16_indexed = 1158,
ARM_VCMLAv4f32 = 1159,
ARM_VCMLAv4f32_indexed = 1160,
ARM_VCMLAv8f16 = 1161,
ARM_VCMLAv8f16_indexed = 1162,
ARM_VCMPD = 1163,
ARM_VCMPED = 1164,
ARM_VCMPEH = 1165,
ARM_VCMPES = 1166,
ARM_VCMPEZD = 1167,
ARM_VCMPEZH = 1168,
ARM_VCMPEZS = 1169,
ARM_VCMPH = 1170,
ARM_VCMPS = 1171,
ARM_VCMPZD = 1172,
ARM_VCMPZH = 1173,
ARM_VCMPZS = 1174,
ARM_VCNTd = 1175,
ARM_VCNTq = 1176,
ARM_VCVTANSDf = 1177,
ARM_VCVTANSDh = 1178,
ARM_VCVTANSQf = 1179,
ARM_VCVTANSQh = 1180,
ARM_VCVTANUDf = 1181,
ARM_VCVTANUDh = 1182,
ARM_VCVTANUQf = 1183,
ARM_VCVTANUQh = 1184,
ARM_VCVTASD = 1185,
ARM_VCVTASH = 1186,
ARM_VCVTASS = 1187,
ARM_VCVTAUD = 1188,
ARM_VCVTAUH = 1189,
ARM_VCVTAUS = 1190,
ARM_VCVTBDH = 1191,
ARM_VCVTBHD = 1192,
ARM_VCVTBHS = 1193,
ARM_VCVTBSH = 1194,
ARM_VCVTDS = 1195,
ARM_VCVTMNSDf = 1196,
ARM_VCVTMNSDh = 1197,
ARM_VCVTMNSQf = 1198,
ARM_VCVTMNSQh = 1199,
ARM_VCVTMNUDf = 1200,
ARM_VCVTMNUDh = 1201,
ARM_VCVTMNUQf = 1202,
ARM_VCVTMNUQh = 1203,
ARM_VCVTMSD = 1204,
ARM_VCVTMSH = 1205,
ARM_VCVTMSS = 1206,
ARM_VCVTMUD = 1207,
ARM_VCVTMUH = 1208,
ARM_VCVTMUS = 1209,
ARM_VCVTNNSDf = 1210,
ARM_VCVTNNSDh = 1211,
ARM_VCVTNNSQf = 1212,
ARM_VCVTNNSQh = 1213,
ARM_VCVTNNUDf = 1214,
ARM_VCVTNNUDh = 1215,
ARM_VCVTNNUQf = 1216,
ARM_VCVTNNUQh = 1217,
ARM_VCVTNSD = 1218,
ARM_VCVTNSH = 1219,
ARM_VCVTNSS = 1220,
ARM_VCVTNUD = 1221,
ARM_VCVTNUH = 1222,
ARM_VCVTNUS = 1223,
ARM_VCVTPNSDf = 1224,
ARM_VCVTPNSDh = 1225,
ARM_VCVTPNSQf = 1226,
ARM_VCVTPNSQh = 1227,
ARM_VCVTPNUDf = 1228,
ARM_VCVTPNUDh = 1229,
ARM_VCVTPNUQf = 1230,
ARM_VCVTPNUQh = 1231,
ARM_VCVTPSD = 1232,
ARM_VCVTPSH = 1233,
ARM_VCVTPSS = 1234,
ARM_VCVTPUD = 1235,
ARM_VCVTPUH = 1236,
ARM_VCVTPUS = 1237,
ARM_VCVTSD = 1238,
ARM_VCVTTDH = 1239,
ARM_VCVTTHD = 1240,
ARM_VCVTTHS = 1241,
ARM_VCVTTSH = 1242,
ARM_VCVTf2h = 1243,
ARM_VCVTf2sd = 1244,
ARM_VCVTf2sq = 1245,
ARM_VCVTf2ud = 1246,
ARM_VCVTf2uq = 1247,
ARM_VCVTf2xsd = 1248,
ARM_VCVTf2xsq = 1249,
ARM_VCVTf2xud = 1250,
ARM_VCVTf2xuq = 1251,
ARM_VCVTh2f = 1252,
ARM_VCVTh2sd = 1253,
ARM_VCVTh2sq = 1254,
ARM_VCVTh2ud = 1255,
ARM_VCVTh2uq = 1256,
ARM_VCVTh2xsd = 1257,
ARM_VCVTh2xsq = 1258,
ARM_VCVTh2xud = 1259,
ARM_VCVTh2xuq = 1260,
ARM_VCVTs2fd = 1261,
ARM_VCVTs2fq = 1262,
ARM_VCVTs2hd = 1263,
ARM_VCVTs2hq = 1264,
ARM_VCVTu2fd = 1265,
ARM_VCVTu2fq = 1266,
ARM_VCVTu2hd = 1267,
ARM_VCVTu2hq = 1268,
ARM_VCVTxs2fd = 1269,
ARM_VCVTxs2fq = 1270,
ARM_VCVTxs2hd = 1271,
ARM_VCVTxs2hq = 1272,
ARM_VCVTxu2fd = 1273,
ARM_VCVTxu2fq = 1274,
ARM_VCVTxu2hd = 1275,
ARM_VCVTxu2hq = 1276,
ARM_VDIVD = 1277,
ARM_VDIVH = 1278,
ARM_VDIVS = 1279,
ARM_VDUP16d = 1280,
ARM_VDUP16q = 1281,
ARM_VDUP32d = 1282,
ARM_VDUP32q = 1283,
ARM_VDUP8d = 1284,
ARM_VDUP8q = 1285,
ARM_VDUPLN16d = 1286,
ARM_VDUPLN16q = 1287,
ARM_VDUPLN32d = 1288,
ARM_VDUPLN32q = 1289,
ARM_VDUPLN8d = 1290,
ARM_VDUPLN8q = 1291,
ARM_VEORd = 1292,
ARM_VEORq = 1293,
ARM_VEXTd16 = 1294,
ARM_VEXTd32 = 1295,
ARM_VEXTd8 = 1296,
ARM_VEXTq16 = 1297,
ARM_VEXTq32 = 1298,
ARM_VEXTq64 = 1299,
ARM_VEXTq8 = 1300,
ARM_VFMAD = 1301,
ARM_VFMAH = 1302,
ARM_VFMAS = 1303,
ARM_VFMAfd = 1304,
ARM_VFMAfq = 1305,
ARM_VFMAhd = 1306,
ARM_VFMAhq = 1307,
ARM_VFMSD = 1308,
ARM_VFMSH = 1309,
ARM_VFMSS = 1310,
ARM_VFMSfd = 1311,
ARM_VFMSfq = 1312,
ARM_VFMShd = 1313,
ARM_VFMShq = 1314,
ARM_VFNMAD = 1315,
ARM_VFNMAH = 1316,
ARM_VFNMAS = 1317,
ARM_VFNMSD = 1318,
ARM_VFNMSH = 1319,
ARM_VFNMSS = 1320,
ARM_VGETLNi32 = 1321,
ARM_VGETLNs16 = 1322,
ARM_VGETLNs8 = 1323,
ARM_VGETLNu16 = 1324,
ARM_VGETLNu8 = 1325,
ARM_VHADDsv16i8 = 1326,
ARM_VHADDsv2i32 = 1327,
ARM_VHADDsv4i16 = 1328,
ARM_VHADDsv4i32 = 1329,
ARM_VHADDsv8i16 = 1330,
ARM_VHADDsv8i8 = 1331,
ARM_VHADDuv16i8 = 1332,
ARM_VHADDuv2i32 = 1333,
ARM_VHADDuv4i16 = 1334,
ARM_VHADDuv4i32 = 1335,
ARM_VHADDuv8i16 = 1336,
ARM_VHADDuv8i8 = 1337,
ARM_VHSUBsv16i8 = 1338,
ARM_VHSUBsv2i32 = 1339,
ARM_VHSUBsv4i16 = 1340,
ARM_VHSUBsv4i32 = 1341,
ARM_VHSUBsv8i16 = 1342,
ARM_VHSUBsv8i8 = 1343,
ARM_VHSUBuv16i8 = 1344,
ARM_VHSUBuv2i32 = 1345,
ARM_VHSUBuv4i16 = 1346,
ARM_VHSUBuv4i32 = 1347,
ARM_VHSUBuv8i16 = 1348,
ARM_VHSUBuv8i8 = 1349,
ARM_VINSH = 1350,
ARM_VJCVT = 1351,
ARM_VLD1DUPd16 = 1352,
ARM_VLD1DUPd16wb_fixed = 1353,
ARM_VLD1DUPd16wb_register = 1354,
ARM_VLD1DUPd32 = 1355,
ARM_VLD1DUPd32wb_fixed = 1356,
ARM_VLD1DUPd32wb_register = 1357,
ARM_VLD1DUPd8 = 1358,
ARM_VLD1DUPd8wb_fixed = 1359,
ARM_VLD1DUPd8wb_register = 1360,
ARM_VLD1DUPq16 = 1361,
ARM_VLD1DUPq16wb_fixed = 1362,
ARM_VLD1DUPq16wb_register = 1363,
ARM_VLD1DUPq32 = 1364,
ARM_VLD1DUPq32wb_fixed = 1365,
ARM_VLD1DUPq32wb_register = 1366,
ARM_VLD1DUPq8 = 1367,
ARM_VLD1DUPq8wb_fixed = 1368,
ARM_VLD1DUPq8wb_register = 1369,
ARM_VLD1LNd16 = 1370,
ARM_VLD1LNd16_UPD = 1371,
ARM_VLD1LNd32 = 1372,
ARM_VLD1LNd32_UPD = 1373,
ARM_VLD1LNd8 = 1374,
ARM_VLD1LNd8_UPD = 1375,
ARM_VLD1d16 = 1382,
ARM_VLD1d16Q = 1383,
ARM_VLD1d16Qwb_fixed = 1385,
ARM_VLD1d16Qwb_register = 1386,
ARM_VLD1d16T = 1387,
ARM_VLD1d16Twb_fixed = 1389,
ARM_VLD1d16Twb_register = 1390,
ARM_VLD1d16wb_fixed = 1391,
ARM_VLD1d16wb_register = 1392,
ARM_VLD1d32 = 1393,
ARM_VLD1d32Q = 1394,
ARM_VLD1d32Qwb_fixed = 1396,
ARM_VLD1d32Qwb_register = 1397,
ARM_VLD1d32T = 1398,
ARM_VLD1d32Twb_fixed = 1400,
ARM_VLD1d32Twb_register = 1401,
ARM_VLD1d32wb_fixed = 1402,
ARM_VLD1d32wb_register = 1403,
ARM_VLD1d64 = 1404,
ARM_VLD1d64Q = 1405,
ARM_VLD1d64Qwb_fixed = 1409,
ARM_VLD1d64Qwb_register = 1410,
ARM_VLD1d64T = 1411,
ARM_VLD1d64Twb_fixed = 1415,
ARM_VLD1d64Twb_register = 1416,
ARM_VLD1d64wb_fixed = 1417,
ARM_VLD1d64wb_register = 1418,
ARM_VLD1d8 = 1419,
ARM_VLD1d8Q = 1420,
ARM_VLD1d8Qwb_fixed = 1422,
ARM_VLD1d8Qwb_register = 1423,
ARM_VLD1d8T = 1424,
ARM_VLD1d8Twb_fixed = 1426,
ARM_VLD1d8Twb_register = 1427,
ARM_VLD1d8wb_fixed = 1428,
ARM_VLD1d8wb_register = 1429,
ARM_VLD1q16 = 1430,
ARM_VLD1q16wb_fixed = 1435,
ARM_VLD1q16wb_register = 1436,
ARM_VLD1q32 = 1437,
ARM_VLD1q32wb_fixed = 1442,
ARM_VLD1q32wb_register = 1443,
ARM_VLD1q64 = 1444,
ARM_VLD1q64wb_fixed = 1449,
ARM_VLD1q64wb_register = 1450,
ARM_VLD1q8 = 1451,
ARM_VLD1q8wb_fixed = 1456,
ARM_VLD1q8wb_register = 1457,
ARM_VLD2DUPd16 = 1458,
ARM_VLD2DUPd16wb_fixed = 1459,
ARM_VLD2DUPd16wb_register = 1460,
ARM_VLD2DUPd16x2 = 1461,
ARM_VLD2DUPd16x2wb_fixed = 1462,
ARM_VLD2DUPd16x2wb_register = 1463,
ARM_VLD2DUPd32 = 1464,
ARM_VLD2DUPd32wb_fixed = 1465,
ARM_VLD2DUPd32wb_register = 1466,
ARM_VLD2DUPd32x2 = 1467,
ARM_VLD2DUPd32x2wb_fixed = 1468,
ARM_VLD2DUPd32x2wb_register = 1469,
ARM_VLD2DUPd8 = 1470,
ARM_VLD2DUPd8wb_fixed = 1471,
ARM_VLD2DUPd8wb_register = 1472,
ARM_VLD2DUPd8x2 = 1473,
ARM_VLD2DUPd8x2wb_fixed = 1474,
ARM_VLD2DUPd8x2wb_register = 1475,
ARM_VLD2LNd16 = 1482,
ARM_VLD2LNd16_UPD = 1485,
ARM_VLD2LNd32 = 1486,
ARM_VLD2LNd32_UPD = 1489,
ARM_VLD2LNd8 = 1490,
ARM_VLD2LNd8_UPD = 1493,
ARM_VLD2LNq16 = 1494,
ARM_VLD2LNq16_UPD = 1497,
ARM_VLD2LNq32 = 1498,
ARM_VLD2LNq32_UPD = 1501,
ARM_VLD2b16 = 1502,
ARM_VLD2b16wb_fixed = 1503,
ARM_VLD2b16wb_register = 1504,
ARM_VLD2b32 = 1505,
ARM_VLD2b32wb_fixed = 1506,
ARM_VLD2b32wb_register = 1507,
ARM_VLD2b8 = 1508,
ARM_VLD2b8wb_fixed = 1509,
ARM_VLD2b8wb_register = 1510,
ARM_VLD2d16 = 1511,
ARM_VLD2d16wb_fixed = 1512,
ARM_VLD2d16wb_register = 1513,
ARM_VLD2d32 = 1514,
ARM_VLD2d32wb_fixed = 1515,
ARM_VLD2d32wb_register = 1516,
ARM_VLD2d8 = 1517,
ARM_VLD2d8wb_fixed = 1518,
ARM_VLD2d8wb_register = 1519,
ARM_VLD2q16 = 1520,
ARM_VLD2q16wb_fixed = 1524,
ARM_VLD2q16wb_register = 1525,
ARM_VLD2q32 = 1526,
ARM_VLD2q32wb_fixed = 1530,
ARM_VLD2q32wb_register = 1531,
ARM_VLD2q8 = 1532,
ARM_VLD2q8wb_fixed = 1536,
ARM_VLD2q8wb_register = 1537,
ARM_VLD3DUPd16 = 1538,
ARM_VLD3DUPd16_UPD = 1541,
ARM_VLD3DUPd32 = 1542,
ARM_VLD3DUPd32_UPD = 1545,
ARM_VLD3DUPd8 = 1546,
ARM_VLD3DUPd8_UPD = 1549,
ARM_VLD3DUPq16 = 1550,
ARM_VLD3DUPq16_UPD = 1553,
ARM_VLD3DUPq32 = 1554,
ARM_VLD3DUPq32_UPD = 1557,
ARM_VLD3DUPq8 = 1558,
ARM_VLD3DUPq8_UPD = 1561,
ARM_VLD3LNd16 = 1562,
ARM_VLD3LNd16_UPD = 1565,
ARM_VLD3LNd32 = 1566,
ARM_VLD3LNd32_UPD = 1569,
ARM_VLD3LNd8 = 1570,
ARM_VLD3LNd8_UPD = 1573,
ARM_VLD3LNq16 = 1574,
ARM_VLD3LNq16_UPD = 1577,
ARM_VLD3LNq32 = 1578,
ARM_VLD3LNq32_UPD = 1581,
ARM_VLD3d16 = 1582,
ARM_VLD3d16_UPD = 1585,
ARM_VLD3d32 = 1586,
ARM_VLD3d32_UPD = 1589,
ARM_VLD3d8 = 1590,
ARM_VLD3d8_UPD = 1593,
ARM_VLD3q16 = 1594,
ARM_VLD3q16_UPD = 1596,
ARM_VLD3q32 = 1599,
ARM_VLD3q32_UPD = 1601,
ARM_VLD3q8 = 1604,
ARM_VLD3q8_UPD = 1606,
ARM_VLD4DUPd16 = 1609,
ARM_VLD4DUPd16_UPD = 1612,
ARM_VLD4DUPd32 = 1613,
ARM_VLD4DUPd32_UPD = 1616,
ARM_VLD4DUPd8 = 1617,
ARM_VLD4DUPd8_UPD = 1620,
ARM_VLD4DUPq16 = 1621,
ARM_VLD4DUPq16_UPD = 1624,
ARM_VLD4DUPq32 = 1625,
ARM_VLD4DUPq32_UPD = 1628,
ARM_VLD4DUPq8 = 1629,
ARM_VLD4DUPq8_UPD = 1632,
ARM_VLD4LNd16 = 1633,
ARM_VLD4LNd16_UPD = 1636,
ARM_VLD4LNd32 = 1637,
ARM_VLD4LNd32_UPD = 1640,
ARM_VLD4LNd8 = 1641,
ARM_VLD4LNd8_UPD = 1644,
ARM_VLD4LNq16 = 1645,
ARM_VLD4LNq16_UPD = 1648,
ARM_VLD4LNq32 = 1649,
ARM_VLD4LNq32_UPD = 1652,
ARM_VLD4d16 = 1653,
ARM_VLD4d16_UPD = 1656,
ARM_VLD4d32 = 1657,
ARM_VLD4d32_UPD = 1660,
ARM_VLD4d8 = 1661,
ARM_VLD4d8_UPD = 1664,
ARM_VLD4q16 = 1665,
ARM_VLD4q16_UPD = 1667,
ARM_VLD4q32 = 1670,
ARM_VLD4q32_UPD = 1672,
ARM_VLD4q8 = 1675,
ARM_VLD4q8_UPD = 1677,
ARM_VLDMDDB_UPD = 1680,
ARM_VLDMDIA = 1681,
ARM_VLDMDIA_UPD = 1682,
ARM_VLDMQIA = 1683,
ARM_VLDMSDB_UPD = 1684,
ARM_VLDMSIA = 1685,
ARM_VLDMSIA_UPD = 1686,
ARM_VLDRD = 1687,
ARM_VLDRH = 1688,
ARM_VLDRS = 1689,
ARM_VLLDM = 1690,
ARM_VLSTM = 1691,
ARM_VMAXNMD = 1692,
ARM_VMAXNMH = 1693,
ARM_VMAXNMNDf = 1694,
ARM_VMAXNMNDh = 1695,
ARM_VMAXNMNQf = 1696,
ARM_VMAXNMNQh = 1697,
ARM_VMAXNMS = 1698,
ARM_VMAXfd = 1699,
ARM_VMAXfq = 1700,
ARM_VMAXhd = 1701,
ARM_VMAXhq = 1702,
ARM_VMAXsv16i8 = 1703,
ARM_VMAXsv2i32 = 1704,
ARM_VMAXsv4i16 = 1705,
ARM_VMAXsv4i32 = 1706,
ARM_VMAXsv8i16 = 1707,
ARM_VMAXsv8i8 = 1708,
ARM_VMAXuv16i8 = 1709,
ARM_VMAXuv2i32 = 1710,
ARM_VMAXuv4i16 = 1711,
ARM_VMAXuv4i32 = 1712,
ARM_VMAXuv8i16 = 1713,
ARM_VMAXuv8i8 = 1714,
ARM_VMINNMD = 1715,
ARM_VMINNMH = 1716,
ARM_VMINNMNDf = 1717,
ARM_VMINNMNDh = 1718,
ARM_VMINNMNQf = 1719,
ARM_VMINNMNQh = 1720,
ARM_VMINNMS = 1721,
ARM_VMINfd = 1722,
ARM_VMINfq = 1723,
ARM_VMINhd = 1724,
ARM_VMINhq = 1725,
ARM_VMINsv16i8 = 1726,
ARM_VMINsv2i32 = 1727,
ARM_VMINsv4i16 = 1728,
ARM_VMINsv4i32 = 1729,
ARM_VMINsv8i16 = 1730,
ARM_VMINsv8i8 = 1731,
ARM_VMINuv16i8 = 1732,
ARM_VMINuv2i32 = 1733,
ARM_VMINuv4i16 = 1734,
ARM_VMINuv4i32 = 1735,
ARM_VMINuv8i16 = 1736,
ARM_VMINuv8i8 = 1737,
ARM_VMLAD = 1738,
ARM_VMLAH = 1739,
ARM_VMLALslsv2i32 = 1740,
ARM_VMLALslsv4i16 = 1741,
ARM_VMLALsluv2i32 = 1742,
ARM_VMLALsluv4i16 = 1743,
ARM_VMLALsv2i64 = 1744,
ARM_VMLALsv4i32 = 1745,
ARM_VMLALsv8i16 = 1746,
ARM_VMLALuv2i64 = 1747,
ARM_VMLALuv4i32 = 1748,
ARM_VMLALuv8i16 = 1749,
ARM_VMLAS = 1750,
ARM_VMLAfd = 1751,
ARM_VMLAfq = 1752,
ARM_VMLAhd = 1753,
ARM_VMLAhq = 1754,
ARM_VMLAslfd = 1755,
ARM_VMLAslfq = 1756,
ARM_VMLAslhd = 1757,
ARM_VMLAslhq = 1758,
ARM_VMLAslv2i32 = 1759,
ARM_VMLAslv4i16 = 1760,
ARM_VMLAslv4i32 = 1761,
ARM_VMLAslv8i16 = 1762,
ARM_VMLAv16i8 = 1763,
ARM_VMLAv2i32 = 1764,
ARM_VMLAv4i16 = 1765,
ARM_VMLAv4i32 = 1766,
ARM_VMLAv8i16 = 1767,
ARM_VMLAv8i8 = 1768,
ARM_VMLSD = 1769,
ARM_VMLSH = 1770,
ARM_VMLSLslsv2i32 = 1771,
ARM_VMLSLslsv4i16 = 1772,
ARM_VMLSLsluv2i32 = 1773,
ARM_VMLSLsluv4i16 = 1774,
ARM_VMLSLsv2i64 = 1775,
ARM_VMLSLsv4i32 = 1776,
ARM_VMLSLsv8i16 = 1777,
ARM_VMLSLuv2i64 = 1778,
ARM_VMLSLuv4i32 = 1779,
ARM_VMLSLuv8i16 = 1780,
ARM_VMLSS = 1781,
ARM_VMLSfd = 1782,
ARM_VMLSfq = 1783,
ARM_VMLShd = 1784,
ARM_VMLShq = 1785,
ARM_VMLSslfd = 1786,
ARM_VMLSslfq = 1787,
ARM_VMLSslhd = 1788,
ARM_VMLSslhq = 1789,
ARM_VMLSslv2i32 = 1790,
ARM_VMLSslv4i16 = 1791,
ARM_VMLSslv4i32 = 1792,
ARM_VMLSslv8i16 = 1793,
ARM_VMLSv16i8 = 1794,
ARM_VMLSv2i32 = 1795,
ARM_VMLSv4i16 = 1796,
ARM_VMLSv4i32 = 1797,
ARM_VMLSv8i16 = 1798,
ARM_VMLSv8i8 = 1799,
ARM_VMOVD = 1800,
ARM_VMOVDRR = 1801,
ARM_VMOVH = 1802,
ARM_VMOVHR = 1803,
ARM_VMOVLsv2i64 = 1804,
ARM_VMOVLsv4i32 = 1805,
ARM_VMOVLsv8i16 = 1806,
ARM_VMOVLuv2i64 = 1807,
ARM_VMOVLuv4i32 = 1808,
ARM_VMOVLuv8i16 = 1809,
ARM_VMOVNv2i32 = 1810,
ARM_VMOVNv4i16 = 1811,
ARM_VMOVNv8i8 = 1812,
ARM_VMOVRH = 1813,
ARM_VMOVRRD = 1814,
ARM_VMOVRRS = 1815,
ARM_VMOVRS = 1816,
ARM_VMOVS = 1817,
ARM_VMOVSR = 1818,
ARM_VMOVSRR = 1819,
ARM_VMOVv16i8 = 1820,
ARM_VMOVv1i64 = 1821,
ARM_VMOVv2f32 = 1822,
ARM_VMOVv2i32 = 1823,
ARM_VMOVv2i64 = 1824,
ARM_VMOVv4f32 = 1825,
ARM_VMOVv4i16 = 1826,
ARM_VMOVv4i32 = 1827,
ARM_VMOVv8i16 = 1828,
ARM_VMOVv8i8 = 1829,
ARM_VMRS = 1830,
ARM_VMRS_FPEXC = 1831,
ARM_VMRS_FPINST = 1832,
ARM_VMRS_FPINST2 = 1833,
ARM_VMRS_FPSID = 1834,
ARM_VMRS_MVFR0 = 1835,
ARM_VMRS_MVFR1 = 1836,
ARM_VMRS_MVFR2 = 1837,
ARM_VMSR = 1838,
ARM_VMSR_FPEXC = 1839,
ARM_VMSR_FPINST = 1840,
ARM_VMSR_FPINST2 = 1841,
ARM_VMSR_FPSID = 1842,
ARM_VMULD = 1843,
ARM_VMULH = 1844,
ARM_VMULLp64 = 1845,
ARM_VMULLp8 = 1846,
ARM_VMULLslsv2i32 = 1847,
ARM_VMULLslsv4i16 = 1848,
ARM_VMULLsluv2i32 = 1849,
ARM_VMULLsluv4i16 = 1850,
ARM_VMULLsv2i64 = 1851,
ARM_VMULLsv4i32 = 1852,
ARM_VMULLsv8i16 = 1853,
ARM_VMULLuv2i64 = 1854,
ARM_VMULLuv4i32 = 1855,
ARM_VMULLuv8i16 = 1856,
ARM_VMULS = 1857,
ARM_VMULfd = 1858,
ARM_VMULfq = 1859,
ARM_VMULhd = 1860,
ARM_VMULhq = 1861,
ARM_VMULpd = 1862,
ARM_VMULpq = 1863,
ARM_VMULslfd = 1864,
ARM_VMULslfq = 1865,
ARM_VMULslhd = 1866,
ARM_VMULslhq = 1867,
ARM_VMULslv2i32 = 1868,
ARM_VMULslv4i16 = 1869,
ARM_VMULslv4i32 = 1870,
ARM_VMULslv8i16 = 1871,
ARM_VMULv16i8 = 1872,
ARM_VMULv2i32 = 1873,
ARM_VMULv4i16 = 1874,
ARM_VMULv4i32 = 1875,
ARM_VMULv8i16 = 1876,
ARM_VMULv8i8 = 1877,
ARM_VMVNd = 1878,
ARM_VMVNq = 1879,
ARM_VMVNv2i32 = 1880,
ARM_VMVNv4i16 = 1881,
ARM_VMVNv4i32 = 1882,
ARM_VMVNv8i16 = 1883,
ARM_VNEGD = 1884,
ARM_VNEGH = 1885,
ARM_VNEGS = 1886,
ARM_VNEGf32q = 1887,
ARM_VNEGfd = 1888,
ARM_VNEGhd = 1889,
ARM_VNEGhq = 1890,
ARM_VNEGs16d = 1891,
ARM_VNEGs16q = 1892,
ARM_VNEGs32d = 1893,
ARM_VNEGs32q = 1894,
ARM_VNEGs8d = 1895,
ARM_VNEGs8q = 1896,
ARM_VNMLAD = 1897,
ARM_VNMLAH = 1898,
ARM_VNMLAS = 1899,
ARM_VNMLSD = 1900,
ARM_VNMLSH = 1901,
ARM_VNMLSS = 1902,
ARM_VNMULD = 1903,
ARM_VNMULH = 1904,
ARM_VNMULS = 1905,
ARM_VORNd = 1906,
ARM_VORNq = 1907,
ARM_VORRd = 1908,
ARM_VORRiv2i32 = 1909,
ARM_VORRiv4i16 = 1910,
ARM_VORRiv4i32 = 1911,
ARM_VORRiv8i16 = 1912,
ARM_VORRq = 1913,
ARM_VPADALsv16i8 = 1914,
ARM_VPADALsv2i32 = 1915,
ARM_VPADALsv4i16 = 1916,
ARM_VPADALsv4i32 = 1917,
ARM_VPADALsv8i16 = 1918,
ARM_VPADALsv8i8 = 1919,
ARM_VPADALuv16i8 = 1920,
ARM_VPADALuv2i32 = 1921,
ARM_VPADALuv4i16 = 1922,
ARM_VPADALuv4i32 = 1923,
ARM_VPADALuv8i16 = 1924,
ARM_VPADALuv8i8 = 1925,
ARM_VPADDLsv16i8 = 1926,
ARM_VPADDLsv2i32 = 1927,
ARM_VPADDLsv4i16 = 1928,
ARM_VPADDLsv4i32 = 1929,
ARM_VPADDLsv8i16 = 1930,
ARM_VPADDLsv8i8 = 1931,
ARM_VPADDLuv16i8 = 1932,
ARM_VPADDLuv2i32 = 1933,
ARM_VPADDLuv4i16 = 1934,
ARM_VPADDLuv4i32 = 1935,
ARM_VPADDLuv8i16 = 1936,
ARM_VPADDLuv8i8 = 1937,
ARM_VPADDf = 1938,
ARM_VPADDh = 1939,
ARM_VPADDi16 = 1940,
ARM_VPADDi32 = 1941,
ARM_VPADDi8 = 1942,
ARM_VPMAXf = 1943,
ARM_VPMAXh = 1944,
ARM_VPMAXs16 = 1945,
ARM_VPMAXs32 = 1946,
ARM_VPMAXs8 = 1947,
ARM_VPMAXu16 = 1948,
ARM_VPMAXu32 = 1949,
ARM_VPMAXu8 = 1950,
ARM_VPMINf = 1951,
ARM_VPMINh = 1952,
ARM_VPMINs16 = 1953,
ARM_VPMINs32 = 1954,
ARM_VPMINs8 = 1955,
ARM_VPMINu16 = 1956,
ARM_VPMINu32 = 1957,
ARM_VPMINu8 = 1958,
ARM_VQABSv16i8 = 1959,
ARM_VQABSv2i32 = 1960,
ARM_VQABSv4i16 = 1961,
ARM_VQABSv4i32 = 1962,
ARM_VQABSv8i16 = 1963,
ARM_VQABSv8i8 = 1964,
ARM_VQADDsv16i8 = 1965,
ARM_VQADDsv1i64 = 1966,
ARM_VQADDsv2i32 = 1967,
ARM_VQADDsv2i64 = 1968,
ARM_VQADDsv4i16 = 1969,
ARM_VQADDsv4i32 = 1970,
ARM_VQADDsv8i16 = 1971,
ARM_VQADDsv8i8 = 1972,
ARM_VQADDuv16i8 = 1973,
ARM_VQADDuv1i64 = 1974,
ARM_VQADDuv2i32 = 1975,
ARM_VQADDuv2i64 = 1976,
ARM_VQADDuv4i16 = 1977,
ARM_VQADDuv4i32 = 1978,
ARM_VQADDuv8i16 = 1979,
ARM_VQADDuv8i8 = 1980,
ARM_VQDMLALslv2i32 = 1981,
ARM_VQDMLALslv4i16 = 1982,
ARM_VQDMLALv2i64 = 1983,
ARM_VQDMLALv4i32 = 1984,
ARM_VQDMLSLslv2i32 = 1985,
ARM_VQDMLSLslv4i16 = 1986,
ARM_VQDMLSLv2i64 = 1987,
ARM_VQDMLSLv4i32 = 1988,
ARM_VQDMULHslv2i32 = 1989,
ARM_VQDMULHslv4i16 = 1990,
ARM_VQDMULHslv4i32 = 1991,
ARM_VQDMULHslv8i16 = 1992,
ARM_VQDMULHv2i32 = 1993,
ARM_VQDMULHv4i16 = 1994,
ARM_VQDMULHv4i32 = 1995,
ARM_VQDMULHv8i16 = 1996,
ARM_VQDMULLslv2i32 = 1997,
ARM_VQDMULLslv4i16 = 1998,
ARM_VQDMULLv2i64 = 1999,
ARM_VQDMULLv4i32 = 2000,
ARM_VQMOVNsuv2i32 = 2001,
ARM_VQMOVNsuv4i16 = 2002,
ARM_VQMOVNsuv8i8 = 2003,
ARM_VQMOVNsv2i32 = 2004,
ARM_VQMOVNsv4i16 = 2005,
ARM_VQMOVNsv8i8 = 2006,
ARM_VQMOVNuv2i32 = 2007,
ARM_VQMOVNuv4i16 = 2008,
ARM_VQMOVNuv8i8 = 2009,
ARM_VQNEGv16i8 = 2010,
ARM_VQNEGv2i32 = 2011,
ARM_VQNEGv4i16 = 2012,
ARM_VQNEGv4i32 = 2013,
ARM_VQNEGv8i16 = 2014,
ARM_VQNEGv8i8 = 2015,
ARM_VQRDMLAHslv2i32 = 2016,
ARM_VQRDMLAHslv4i16 = 2017,
ARM_VQRDMLAHslv4i32 = 2018,
ARM_VQRDMLAHslv8i16 = 2019,
ARM_VQRDMLAHv2i32 = 2020,
ARM_VQRDMLAHv4i16 = 2021,
ARM_VQRDMLAHv4i32 = 2022,
ARM_VQRDMLAHv8i16 = 2023,
ARM_VQRDMLSHslv2i32 = 2024,
ARM_VQRDMLSHslv4i16 = 2025,
ARM_VQRDMLSHslv4i32 = 2026,
ARM_VQRDMLSHslv8i16 = 2027,
ARM_VQRDMLSHv2i32 = 2028,
ARM_VQRDMLSHv4i16 = 2029,
ARM_VQRDMLSHv4i32 = 2030,
ARM_VQRDMLSHv8i16 = 2031,
ARM_VQRDMULHslv2i32 = 2032,
ARM_VQRDMULHslv4i16 = 2033,
ARM_VQRDMULHslv4i32 = 2034,
ARM_VQRDMULHslv8i16 = 2035,
ARM_VQRDMULHv2i32 = 2036,
ARM_VQRDMULHv4i16 = 2037,
ARM_VQRDMULHv4i32 = 2038,
ARM_VQRDMULHv8i16 = 2039,
ARM_VQRSHLsv16i8 = 2040,
ARM_VQRSHLsv1i64 = 2041,
ARM_VQRSHLsv2i32 = 2042,
ARM_VQRSHLsv2i64 = 2043,
ARM_VQRSHLsv4i16 = 2044,
ARM_VQRSHLsv4i32 = 2045,
ARM_VQRSHLsv8i16 = 2046,
ARM_VQRSHLsv8i8 = 2047,
ARM_VQRSHLuv16i8 = 2048,
ARM_VQRSHLuv1i64 = 2049,
ARM_VQRSHLuv2i32 = 2050,
ARM_VQRSHLuv2i64 = 2051,
ARM_VQRSHLuv4i16 = 2052,
ARM_VQRSHLuv4i32 = 2053,
ARM_VQRSHLuv8i16 = 2054,
ARM_VQRSHLuv8i8 = 2055,
ARM_VQRSHRNsv2i32 = 2056,
ARM_VQRSHRNsv4i16 = 2057,
ARM_VQRSHRNsv8i8 = 2058,
ARM_VQRSHRNuv2i32 = 2059,
ARM_VQRSHRNuv4i16 = 2060,
ARM_VQRSHRNuv8i8 = 2061,
ARM_VQRSHRUNv2i32 = 2062,
ARM_VQRSHRUNv4i16 = 2063,
ARM_VQRSHRUNv8i8 = 2064,
ARM_VQSHLsiv16i8 = 2065,
ARM_VQSHLsiv1i64 = 2066,
ARM_VQSHLsiv2i32 = 2067,
ARM_VQSHLsiv2i64 = 2068,
ARM_VQSHLsiv4i16 = 2069,
ARM_VQSHLsiv4i32 = 2070,
ARM_VQSHLsiv8i16 = 2071,
ARM_VQSHLsiv8i8 = 2072,
ARM_VQSHLsuv16i8 = 2073,
ARM_VQSHLsuv1i64 = 2074,
ARM_VQSHLsuv2i32 = 2075,
ARM_VQSHLsuv2i64 = 2076,
ARM_VQSHLsuv4i16 = 2077,
ARM_VQSHLsuv4i32 = 2078,
ARM_VQSHLsuv8i16 = 2079,
ARM_VQSHLsuv8i8 = 2080,
ARM_VQSHLsv16i8 = 2081,
ARM_VQSHLsv1i64 = 2082,
ARM_VQSHLsv2i32 = 2083,
ARM_VQSHLsv2i64 = 2084,
ARM_VQSHLsv4i16 = 2085,
ARM_VQSHLsv4i32 = 2086,
ARM_VQSHLsv8i16 = 2087,
ARM_VQSHLsv8i8 = 2088,
ARM_VQSHLuiv16i8 = 2089,
ARM_VQSHLuiv1i64 = 2090,
ARM_VQSHLuiv2i32 = 2091,
ARM_VQSHLuiv2i64 = 2092,
ARM_VQSHLuiv4i16 = 2093,
ARM_VQSHLuiv4i32 = 2094,
ARM_VQSHLuiv8i16 = 2095,
ARM_VQSHLuiv8i8 = 2096,
ARM_VQSHLuv16i8 = 2097,
ARM_VQSHLuv1i64 = 2098,
ARM_VQSHLuv2i32 = 2099,
ARM_VQSHLuv2i64 = 2100,
ARM_VQSHLuv4i16 = 2101,
ARM_VQSHLuv4i32 = 2102,
ARM_VQSHLuv8i16 = 2103,
ARM_VQSHLuv8i8 = 2104,
ARM_VQSHRNsv2i32 = 2105,
ARM_VQSHRNsv4i16 = 2106,
ARM_VQSHRNsv8i8 = 2107,
ARM_VQSHRNuv2i32 = 2108,
ARM_VQSHRNuv4i16 = 2109,
ARM_VQSHRNuv8i8 = 2110,
ARM_VQSHRUNv2i32 = 2111,
ARM_VQSHRUNv4i16 = 2112,
ARM_VQSHRUNv8i8 = 2113,
ARM_VQSUBsv16i8 = 2114,
ARM_VQSUBsv1i64 = 2115,
ARM_VQSUBsv2i32 = 2116,
ARM_VQSUBsv2i64 = 2117,
ARM_VQSUBsv4i16 = 2118,
ARM_VQSUBsv4i32 = 2119,
ARM_VQSUBsv8i16 = 2120,
ARM_VQSUBsv8i8 = 2121,
ARM_VQSUBuv16i8 = 2122,
ARM_VQSUBuv1i64 = 2123,
ARM_VQSUBuv2i32 = 2124,
ARM_VQSUBuv2i64 = 2125,
ARM_VQSUBuv4i16 = 2126,
ARM_VQSUBuv4i32 = 2127,
ARM_VQSUBuv8i16 = 2128,
ARM_VQSUBuv8i8 = 2129,
ARM_VRADDHNv2i32 = 2130,
ARM_VRADDHNv4i16 = 2131,
ARM_VRADDHNv8i8 = 2132,
ARM_VRECPEd = 2133,
ARM_VRECPEfd = 2134,
ARM_VRECPEfq = 2135,
ARM_VRECPEhd = 2136,
ARM_VRECPEhq = 2137,
ARM_VRECPEq = 2138,
ARM_VRECPSfd = 2139,
ARM_VRECPSfq = 2140,
ARM_VRECPShd = 2141,
ARM_VRECPShq = 2142,
ARM_VREV16d8 = 2143,
ARM_VREV16q8 = 2144,
ARM_VREV32d16 = 2145,
ARM_VREV32d8 = 2146,
ARM_VREV32q16 = 2147,
ARM_VREV32q8 = 2148,
ARM_VREV64d16 = 2149,
ARM_VREV64d32 = 2150,
ARM_VREV64d8 = 2151,
ARM_VREV64q16 = 2152,
ARM_VREV64q32 = 2153,
ARM_VREV64q8 = 2154,
ARM_VRHADDsv16i8 = 2155,
ARM_VRHADDsv2i32 = 2156,
ARM_VRHADDsv4i16 = 2157,
ARM_VRHADDsv4i32 = 2158,
ARM_VRHADDsv8i16 = 2159,
ARM_VRHADDsv8i8 = 2160,
ARM_VRHADDuv16i8 = 2161,
ARM_VRHADDuv2i32 = 2162,
ARM_VRHADDuv4i16 = 2163,
ARM_VRHADDuv4i32 = 2164,
ARM_VRHADDuv8i16 = 2165,
ARM_VRHADDuv8i8 = 2166,
ARM_VRINTAD = 2167,
ARM_VRINTAH = 2168,
ARM_VRINTANDf = 2169,
ARM_VRINTANDh = 2170,
ARM_VRINTANQf = 2171,
ARM_VRINTANQh = 2172,
ARM_VRINTAS = 2173,
ARM_VRINTMD = 2174,
ARM_VRINTMH = 2175,
ARM_VRINTMNDf = 2176,
ARM_VRINTMNDh = 2177,
ARM_VRINTMNQf = 2178,
ARM_VRINTMNQh = 2179,
ARM_VRINTMS = 2180,
ARM_VRINTND = 2181,
ARM_VRINTNH = 2182,
ARM_VRINTNNDf = 2183,
ARM_VRINTNNDh = 2184,
ARM_VRINTNNQf = 2185,
ARM_VRINTNNQh = 2186,
ARM_VRINTNS = 2187,
ARM_VRINTPD = 2188,
ARM_VRINTPH = 2189,
ARM_VRINTPNDf = 2190,
ARM_VRINTPNDh = 2191,
ARM_VRINTPNQf = 2192,
ARM_VRINTPNQh = 2193,
ARM_VRINTPS = 2194,
ARM_VRINTRD = 2195,
ARM_VRINTRH = 2196,
ARM_VRINTRS = 2197,
ARM_VRINTXD = 2198,
ARM_VRINTXH = 2199,
ARM_VRINTXNDf = 2200,
ARM_VRINTXNDh = 2201,
ARM_VRINTXNQf = 2202,
ARM_VRINTXNQh = 2203,
ARM_VRINTXS = 2204,
ARM_VRINTZD = 2205,
ARM_VRINTZH = 2206,
ARM_VRINTZNDf = 2207,
ARM_VRINTZNDh = 2208,
ARM_VRINTZNQf = 2209,
ARM_VRINTZNQh = 2210,
ARM_VRINTZS = 2211,
ARM_VRSHLsv16i8 = 2212,
ARM_VRSHLsv1i64 = 2213,
ARM_VRSHLsv2i32 = 2214,
ARM_VRSHLsv2i64 = 2215,
ARM_VRSHLsv4i16 = 2216,
ARM_VRSHLsv4i32 = 2217,
ARM_VRSHLsv8i16 = 2218,
ARM_VRSHLsv8i8 = 2219,
ARM_VRSHLuv16i8 = 2220,
ARM_VRSHLuv1i64 = 2221,
ARM_VRSHLuv2i32 = 2222,
ARM_VRSHLuv2i64 = 2223,
ARM_VRSHLuv4i16 = 2224,
ARM_VRSHLuv4i32 = 2225,
ARM_VRSHLuv8i16 = 2226,
ARM_VRSHLuv8i8 = 2227,
ARM_VRSHRNv2i32 = 2228,
ARM_VRSHRNv4i16 = 2229,
ARM_VRSHRNv8i8 = 2230,
ARM_VRSHRsv16i8 = 2231,
ARM_VRSHRsv1i64 = 2232,
ARM_VRSHRsv2i32 = 2233,
ARM_VRSHRsv2i64 = 2234,
ARM_VRSHRsv4i16 = 2235,
ARM_VRSHRsv4i32 = 2236,
ARM_VRSHRsv8i16 = 2237,
ARM_VRSHRsv8i8 = 2238,
ARM_VRSHRuv16i8 = 2239,
ARM_VRSHRuv1i64 = 2240,
ARM_VRSHRuv2i32 = 2241,
ARM_VRSHRuv2i64 = 2242,
ARM_VRSHRuv4i16 = 2243,
ARM_VRSHRuv4i32 = 2244,
ARM_VRSHRuv8i16 = 2245,
ARM_VRSHRuv8i8 = 2246,
ARM_VRSQRTEd = 2247,
ARM_VRSQRTEfd = 2248,
ARM_VRSQRTEfq = 2249,
ARM_VRSQRTEhd = 2250,
ARM_VRSQRTEhq = 2251,
ARM_VRSQRTEq = 2252,
ARM_VRSQRTSfd = 2253,
ARM_VRSQRTSfq = 2254,
ARM_VRSQRTShd = 2255,
ARM_VRSQRTShq = 2256,
ARM_VRSRAsv16i8 = 2257,
ARM_VRSRAsv1i64 = 2258,
ARM_VRSRAsv2i32 = 2259,
ARM_VRSRAsv2i64 = 2260,
ARM_VRSRAsv4i16 = 2261,
ARM_VRSRAsv4i32 = 2262,
ARM_VRSRAsv8i16 = 2263,
ARM_VRSRAsv8i8 = 2264,
ARM_VRSRAuv16i8 = 2265,
ARM_VRSRAuv1i64 = 2266,
ARM_VRSRAuv2i32 = 2267,
ARM_VRSRAuv2i64 = 2268,
ARM_VRSRAuv4i16 = 2269,
ARM_VRSRAuv4i32 = 2270,
ARM_VRSRAuv8i16 = 2271,
ARM_VRSRAuv8i8 = 2272,
ARM_VRSUBHNv2i32 = 2273,
ARM_VRSUBHNv4i16 = 2274,
ARM_VRSUBHNv8i8 = 2275,
ARM_VSDOTD = 2276,
ARM_VSDOTDI = 2277,
ARM_VSDOTQ = 2278,
ARM_VSDOTQI = 2279,
ARM_VSELEQD = 2280,
ARM_VSELEQH = 2281,
ARM_VSELEQS = 2282,
ARM_VSELGED = 2283,
ARM_VSELGEH = 2284,
ARM_VSELGES = 2285,
ARM_VSELGTD = 2286,
ARM_VSELGTH = 2287,
ARM_VSELGTS = 2288,
ARM_VSELVSD = 2289,
ARM_VSELVSH = 2290,
ARM_VSELVSS = 2291,
ARM_VSETLNi16 = 2292,
ARM_VSETLNi32 = 2293,
ARM_VSETLNi8 = 2294,
ARM_VSHLLi16 = 2295,
ARM_VSHLLi32 = 2296,
ARM_VSHLLi8 = 2297,
ARM_VSHLLsv2i64 = 2298,
ARM_VSHLLsv4i32 = 2299,
ARM_VSHLLsv8i16 = 2300,
ARM_VSHLLuv2i64 = 2301,
ARM_VSHLLuv4i32 = 2302,
ARM_VSHLLuv8i16 = 2303,
ARM_VSHLiv16i8 = 2304,
ARM_VSHLiv1i64 = 2305,
ARM_VSHLiv2i32 = 2306,
ARM_VSHLiv2i64 = 2307,
ARM_VSHLiv4i16 = 2308,
ARM_VSHLiv4i32 = 2309,
ARM_VSHLiv8i16 = 2310,
ARM_VSHLiv8i8 = 2311,
ARM_VSHLsv16i8 = 2312,
ARM_VSHLsv1i64 = 2313,
ARM_VSHLsv2i32 = 2314,
ARM_VSHLsv2i64 = 2315,
ARM_VSHLsv4i16 = 2316,
ARM_VSHLsv4i32 = 2317,
ARM_VSHLsv8i16 = 2318,
ARM_VSHLsv8i8 = 2319,
ARM_VSHLuv16i8 = 2320,
ARM_VSHLuv1i64 = 2321,
ARM_VSHLuv2i32 = 2322,
ARM_VSHLuv2i64 = 2323,
ARM_VSHLuv4i16 = 2324,
ARM_VSHLuv4i32 = 2325,
ARM_VSHLuv8i16 = 2326,
ARM_VSHLuv8i8 = 2327,
ARM_VSHRNv2i32 = 2328,
ARM_VSHRNv4i16 = 2329,
ARM_VSHRNv8i8 = 2330,
ARM_VSHRsv16i8 = 2331,
ARM_VSHRsv1i64 = 2332,
ARM_VSHRsv2i32 = 2333,
ARM_VSHRsv2i64 = 2334,
ARM_VSHRsv4i16 = 2335,
ARM_VSHRsv4i32 = 2336,
ARM_VSHRsv8i16 = 2337,
ARM_VSHRsv8i8 = 2338,
ARM_VSHRuv16i8 = 2339,
ARM_VSHRuv1i64 = 2340,
ARM_VSHRuv2i32 = 2341,
ARM_VSHRuv2i64 = 2342,
ARM_VSHRuv4i16 = 2343,
ARM_VSHRuv4i32 = 2344,
ARM_VSHRuv8i16 = 2345,
ARM_VSHRuv8i8 = 2346,
ARM_VSHTOD = 2347,
ARM_VSHTOH = 2348,
ARM_VSHTOS = 2349,
ARM_VSITOD = 2350,
ARM_VSITOH = 2351,
ARM_VSITOS = 2352,
ARM_VSLIv16i8 = 2353,
ARM_VSLIv1i64 = 2354,
ARM_VSLIv2i32 = 2355,
ARM_VSLIv2i64 = 2356,
ARM_VSLIv4i16 = 2357,
ARM_VSLIv4i32 = 2358,
ARM_VSLIv8i16 = 2359,
ARM_VSLIv8i8 = 2360,
ARM_VSLTOD = 2361,
ARM_VSLTOH = 2362,
ARM_VSLTOS = 2363,
ARM_VSQRTD = 2364,
ARM_VSQRTH = 2365,
ARM_VSQRTS = 2366,
ARM_VSRAsv16i8 = 2367,
ARM_VSRAsv1i64 = 2368,
ARM_VSRAsv2i32 = 2369,
ARM_VSRAsv2i64 = 2370,
ARM_VSRAsv4i16 = 2371,
ARM_VSRAsv4i32 = 2372,
ARM_VSRAsv8i16 = 2373,
ARM_VSRAsv8i8 = 2374,
ARM_VSRAuv16i8 = 2375,
ARM_VSRAuv1i64 = 2376,
ARM_VSRAuv2i32 = 2377,
ARM_VSRAuv2i64 = 2378,
ARM_VSRAuv4i16 = 2379,
ARM_VSRAuv4i32 = 2380,
ARM_VSRAuv8i16 = 2381,
ARM_VSRAuv8i8 = 2382,
ARM_VSRIv16i8 = 2383,
ARM_VSRIv1i64 = 2384,
ARM_VSRIv2i32 = 2385,
ARM_VSRIv2i64 = 2386,
ARM_VSRIv4i16 = 2387,
ARM_VSRIv4i32 = 2388,
ARM_VSRIv8i16 = 2389,
ARM_VSRIv8i8 = 2390,
ARM_VST1LNd16 = 2391,
ARM_VST1LNd16_UPD = 2392,
ARM_VST1LNd32 = 2393,
ARM_VST1LNd32_UPD = 2394,
ARM_VST1LNd8 = 2395,
ARM_VST1LNd8_UPD = 2396,
ARM_VST1d16 = 2403,
ARM_VST1d16Q = 2404,
ARM_VST1d16Qwb_fixed = 2406,
ARM_VST1d16Qwb_register = 2407,
ARM_VST1d16T = 2408,
ARM_VST1d16Twb_fixed = 2410,
ARM_VST1d16Twb_register = 2411,
ARM_VST1d16wb_fixed = 2412,
ARM_VST1d16wb_register = 2413,
ARM_VST1d32 = 2414,
ARM_VST1d32Q = 2415,
ARM_VST1d32Qwb_fixed = 2417,
ARM_VST1d32Qwb_register = 2418,
ARM_VST1d32T = 2419,
ARM_VST1d32Twb_fixed = 2421,
ARM_VST1d32Twb_register = 2422,
ARM_VST1d32wb_fixed = 2423,
ARM_VST1d32wb_register = 2424,
ARM_VST1d64 = 2425,
ARM_VST1d64Q = 2426,
ARM_VST1d64Qwb_fixed = 2430,
ARM_VST1d64Qwb_register = 2431,
ARM_VST1d64T = 2432,
ARM_VST1d64Twb_fixed = 2436,
ARM_VST1d64Twb_register = 2437,
ARM_VST1d64wb_fixed = 2438,
ARM_VST1d64wb_register = 2439,
ARM_VST1d8 = 2440,
ARM_VST1d8Q = 2441,
ARM_VST1d8Qwb_fixed = 2443,
ARM_VST1d8Qwb_register = 2444,
ARM_VST1d8T = 2445,
ARM_VST1d8Twb_fixed = 2447,
ARM_VST1d8Twb_register = 2448,
ARM_VST1d8wb_fixed = 2449,
ARM_VST1d8wb_register = 2450,
ARM_VST1q16 = 2451,
ARM_VST1q16wb_fixed = 2456,
ARM_VST1q16wb_register = 2457,
ARM_VST1q32 = 2458,
ARM_VST1q32wb_fixed = 2463,
ARM_VST1q32wb_register = 2464,
ARM_VST1q64 = 2465,
ARM_VST1q64wb_fixed = 2470,
ARM_VST1q64wb_register = 2471,
ARM_VST1q8 = 2472,
ARM_VST1q8wb_fixed = 2477,
ARM_VST1q8wb_register = 2478,
ARM_VST2LNd16 = 2479,
ARM_VST2LNd16_UPD = 2482,
ARM_VST2LNd32 = 2483,
ARM_VST2LNd32_UPD = 2486,
ARM_VST2LNd8 = 2487,
ARM_VST2LNd8_UPD = 2490,
ARM_VST2LNq16 = 2491,
ARM_VST2LNq16_UPD = 2494,
ARM_VST2LNq32 = 2495,
ARM_VST2LNq32_UPD = 2498,
ARM_VST2b16 = 2499,
ARM_VST2b16wb_fixed = 2500,
ARM_VST2b16wb_register = 2501,
ARM_VST2b32 = 2502,
ARM_VST2b32wb_fixed = 2503,
ARM_VST2b32wb_register = 2504,
ARM_VST2b8 = 2505,
ARM_VST2b8wb_fixed = 2506,
ARM_VST2b8wb_register = 2507,
ARM_VST2d16 = 2508,
ARM_VST2d16wb_fixed = 2509,
ARM_VST2d16wb_register = 2510,
ARM_VST2d32 = 2511,
ARM_VST2d32wb_fixed = 2512,
ARM_VST2d32wb_register = 2513,
ARM_VST2d8 = 2514,
ARM_VST2d8wb_fixed = 2515,
ARM_VST2d8wb_register = 2516,
ARM_VST2q16 = 2517,
ARM_VST2q16wb_fixed = 2521,
ARM_VST2q16wb_register = 2522,
ARM_VST2q32 = 2523,
ARM_VST2q32wb_fixed = 2527,
ARM_VST2q32wb_register = 2528,
ARM_VST2q8 = 2529,
ARM_VST2q8wb_fixed = 2533,
ARM_VST2q8wb_register = 2534,
ARM_VST3LNd16 = 2535,
ARM_VST3LNd16_UPD = 2538,
ARM_VST3LNd32 = 2539,
ARM_VST3LNd32_UPD = 2542,
ARM_VST3LNd8 = 2543,
ARM_VST3LNd8_UPD = 2546,
ARM_VST3LNq16 = 2547,
ARM_VST3LNq16_UPD = 2550,
ARM_VST3LNq32 = 2551,
ARM_VST3LNq32_UPD = 2554,
ARM_VST3d16 = 2555,
ARM_VST3d16_UPD = 2558,
ARM_VST3d32 = 2559,
ARM_VST3d32_UPD = 2562,
ARM_VST3d8 = 2563,
ARM_VST3d8_UPD = 2566,
ARM_VST3q16 = 2567,
ARM_VST3q16_UPD = 2569,
ARM_VST3q32 = 2572,
ARM_VST3q32_UPD = 2574,
ARM_VST3q8 = 2577,
ARM_VST3q8_UPD = 2579,
ARM_VST4LNd16 = 2582,
ARM_VST4LNd16_UPD = 2585,
ARM_VST4LNd32 = 2586,
ARM_VST4LNd32_UPD = 2589,
ARM_VST4LNd8 = 2590,
ARM_VST4LNd8_UPD = 2593,
ARM_VST4LNq16 = 2594,
ARM_VST4LNq16_UPD = 2597,
ARM_VST4LNq32 = 2598,
ARM_VST4LNq32_UPD = 2601,
ARM_VST4d16 = 2602,
ARM_VST4d16_UPD = 2605,
ARM_VST4d32 = 2606,
ARM_VST4d32_UPD = 2609,
ARM_VST4d8 = 2610,
ARM_VST4d8_UPD = 2613,
ARM_VST4q16 = 2614,
ARM_VST4q16_UPD = 2616,
ARM_VST4q32 = 2619,
ARM_VST4q32_UPD = 2621,
ARM_VST4q8 = 2624,
ARM_VST4q8_UPD = 2626,
ARM_VSTMDDB_UPD = 2629,
ARM_VSTMDIA = 2630,
ARM_VSTMDIA_UPD = 2631,
ARM_VSTMQIA = 2632,
ARM_VSTMSDB_UPD = 2633,
ARM_VSTMSIA = 2634,
ARM_VSTMSIA_UPD = 2635,
ARM_VSTRD = 2636,
ARM_VSTRH = 2637,
ARM_VSTRS = 2638,
ARM_VSUBD = 2639,
ARM_VSUBH = 2640,
ARM_VSUBHNv2i32 = 2641,
ARM_VSUBHNv4i16 = 2642,
ARM_VSUBHNv8i8 = 2643,
ARM_VSUBLsv2i64 = 2644,
ARM_VSUBLsv4i32 = 2645,
ARM_VSUBLsv8i16 = 2646,
ARM_VSUBLuv2i64 = 2647,
ARM_VSUBLuv4i32 = 2648,
ARM_VSUBLuv8i16 = 2649,
ARM_VSUBS = 2650,
ARM_VSUBWsv2i64 = 2651,
ARM_VSUBWsv4i32 = 2652,
ARM_VSUBWsv8i16 = 2653,
ARM_VSUBWuv2i64 = 2654,
ARM_VSUBWuv4i32 = 2655,
ARM_VSUBWuv8i16 = 2656,
ARM_VSUBfd = 2657,
ARM_VSUBfq = 2658,
ARM_VSUBhd = 2659,
ARM_VSUBhq = 2660,
ARM_VSUBv16i8 = 2661,
ARM_VSUBv1i64 = 2662,
ARM_VSUBv2i32 = 2663,
ARM_VSUBv2i64 = 2664,
ARM_VSUBv4i16 = 2665,
ARM_VSUBv4i32 = 2666,
ARM_VSUBv8i16 = 2667,
ARM_VSUBv8i8 = 2668,
ARM_VSWPd = 2669,
ARM_VSWPq = 2670,
ARM_VTBL1 = 2671,
ARM_VTBL2 = 2672,
ARM_VTBL3 = 2673,
ARM_VTBL4 = 2675,
ARM_VTBX1 = 2677,
ARM_VTBX2 = 2678,
ARM_VTBX3 = 2679,
ARM_VTBX4 = 2681,
ARM_VTOSHD = 2683,
ARM_VTOSHH = 2684,
ARM_VTOSHS = 2685,
ARM_VTOSIRD = 2686,
ARM_VTOSIRH = 2687,
ARM_VTOSIRS = 2688,
ARM_VTOSIZD = 2689,
ARM_VTOSIZH = 2690,
ARM_VTOSIZS = 2691,
ARM_VTOSLD = 2692,
ARM_VTOSLH = 2693,
ARM_VTOSLS = 2694,
ARM_VTOUHD = 2695,
ARM_VTOUHH = 2696,
ARM_VTOUHS = 2697,
ARM_VTOUIRD = 2698,
ARM_VTOUIRH = 2699,
ARM_VTOUIRS = 2700,
ARM_VTOUIZD = 2701,
ARM_VTOUIZH = 2702,
ARM_VTOUIZS = 2703,
ARM_VTOULD = 2704,
ARM_VTOULH = 2705,
ARM_VTOULS = 2706,
ARM_VTRNd16 = 2707,
ARM_VTRNd32 = 2708,
ARM_VTRNd8 = 2709,
ARM_VTRNq16 = 2710,
ARM_VTRNq32 = 2711,
ARM_VTRNq8 = 2712,
ARM_VTSTv16i8 = 2713,
ARM_VTSTv2i32 = 2714,
ARM_VTSTv4i16 = 2715,
ARM_VTSTv4i32 = 2716,
ARM_VTSTv8i16 = 2717,
ARM_VTSTv8i8 = 2718,
ARM_VUDOTD = 2719,
ARM_VUDOTDI = 2720,
ARM_VUDOTQ = 2721,
ARM_VUDOTQI = 2722,
ARM_VUHTOD = 2723,
ARM_VUHTOH = 2724,
ARM_VUHTOS = 2725,
ARM_VUITOD = 2726,
ARM_VUITOH = 2727,
ARM_VUITOS = 2728,
ARM_VULTOD = 2729,
ARM_VULTOH = 2730,
ARM_VULTOS = 2731,
ARM_VUZPd16 = 2732,
ARM_VUZPd8 = 2733,
ARM_VUZPq16 = 2734,
ARM_VUZPq32 = 2735,
ARM_VUZPq8 = 2736,
ARM_VZIPd16 = 2737,
ARM_VZIPd8 = 2738,
ARM_VZIPq16 = 2739,
ARM_VZIPq32 = 2740,
ARM_VZIPq8 = 2741,
ARM_sysLDMDA = 2742,
ARM_sysLDMDA_UPD = 2743,
ARM_sysLDMDB = 2744,
ARM_sysLDMDB_UPD = 2745,
ARM_sysLDMIA = 2746,
ARM_sysLDMIA_UPD = 2747,
ARM_sysLDMIB = 2748,
ARM_sysLDMIB_UPD = 2749,
ARM_sysSTMDA = 2750,
ARM_sysSTMDA_UPD = 2751,
ARM_sysSTMDB = 2752,
ARM_sysSTMDB_UPD = 2753,
ARM_sysSTMIA = 2754,
ARM_sysSTMIA_UPD = 2755,
ARM_sysSTMIB = 2756,
ARM_sysSTMIB_UPD = 2757,
ARM_t2ADCri = 2758,
ARM_t2ADCrr = 2759,
ARM_t2ADCrs = 2760,
ARM_t2ADDri = 2761,
ARM_t2ADDri12 = 2762,
ARM_t2ADDrr = 2763,
ARM_t2ADDrs = 2764,
ARM_t2ADR = 2765,
ARM_t2ANDri = 2766,
ARM_t2ANDrr = 2767,
ARM_t2ANDrs = 2768,
ARM_t2ASRri = 2769,
ARM_t2ASRrr = 2770,
ARM_t2B = 2771,
ARM_t2BFC = 2772,
ARM_t2BFI = 2773,
ARM_t2BICri = 2774,
ARM_t2BICrr = 2775,
ARM_t2BICrs = 2776,
ARM_t2BXJ = 2777,
ARM_t2Bcc = 2778,
ARM_t2CDP = 2779,
ARM_t2CDP2 = 2780,
ARM_t2CLREX = 2781,
ARM_t2CLZ = 2782,
ARM_t2CMNri = 2783,
ARM_t2CMNzrr = 2784,
ARM_t2CMNzrs = 2785,
ARM_t2CMPri = 2786,
ARM_t2CMPrr = 2787,
ARM_t2CMPrs = 2788,
ARM_t2CPS1p = 2789,
ARM_t2CPS2p = 2790,
ARM_t2CPS3p = 2791,
ARM_t2CRC32B = 2792,
ARM_t2CRC32CB = 2793,
ARM_t2CRC32CH = 2794,
ARM_t2CRC32CW = 2795,
ARM_t2CRC32H = 2796,
ARM_t2CRC32W = 2797,
ARM_t2DBG = 2798,
ARM_t2DCPS1 = 2799,
ARM_t2DCPS2 = 2800,
ARM_t2DCPS3 = 2801,
ARM_t2DMB = 2802,
ARM_t2DSB = 2803,
ARM_t2EORri = 2804,
ARM_t2EORrr = 2805,
ARM_t2EORrs = 2806,
ARM_t2HINT = 2807,
ARM_t2HVC = 2808,
ARM_t2ISB = 2809,
ARM_t2IT = 2810,
ARM_t2LDA = 2813,
ARM_t2LDAB = 2814,
ARM_t2LDAEX = 2815,
ARM_t2LDAEXB = 2816,
ARM_t2LDAEXD = 2817,
ARM_t2LDAEXH = 2818,
ARM_t2LDAH = 2819,
ARM_t2LDC2L_OFFSET = 2820,
ARM_t2LDC2L_OPTION = 2821,
ARM_t2LDC2L_POST = 2822,
ARM_t2LDC2L_PRE = 2823,
ARM_t2LDC2_OFFSET = 2824,
ARM_t2LDC2_OPTION = 2825,
ARM_t2LDC2_POST = 2826,
ARM_t2LDC2_PRE = 2827,
ARM_t2LDCL_OFFSET = 2828,
ARM_t2LDCL_OPTION = 2829,
ARM_t2LDCL_POST = 2830,
ARM_t2LDCL_PRE = 2831,
ARM_t2LDC_OFFSET = 2832,
ARM_t2LDC_OPTION = 2833,
ARM_t2LDC_POST = 2834,
ARM_t2LDC_PRE = 2835,
ARM_t2LDMDB = 2836,
ARM_t2LDMDB_UPD = 2837,
ARM_t2LDMIA = 2838,
ARM_t2LDMIA_UPD = 2839,
ARM_t2LDRBT = 2840,
ARM_t2LDRB_POST = 2841,
ARM_t2LDRB_PRE = 2842,
ARM_t2LDRBi12 = 2843,
ARM_t2LDRBi8 = 2844,
ARM_t2LDRBpci = 2845,
ARM_t2LDRBs = 2846,
ARM_t2LDRD_POST = 2847,
ARM_t2LDRD_PRE = 2848,
ARM_t2LDRDi8 = 2849,
ARM_t2LDREX = 2850,
ARM_t2LDREXB = 2851,
ARM_t2LDREXD = 2852,
ARM_t2LDREXH = 2853,
ARM_t2LDRHT = 2854,
ARM_t2LDRH_POST = 2855,
ARM_t2LDRH_PRE = 2856,
ARM_t2LDRHi12 = 2857,
ARM_t2LDRHi8 = 2858,
ARM_t2LDRHpci = 2859,
ARM_t2LDRHs = 2860,
ARM_t2LDRSBT = 2861,
ARM_t2LDRSB_POST = 2862,
ARM_t2LDRSB_PRE = 2863,
ARM_t2LDRSBi12 = 2864,
ARM_t2LDRSBi8 = 2865,
ARM_t2LDRSBpci = 2866,
ARM_t2LDRSBs = 2867,
ARM_t2LDRSHT = 2868,
ARM_t2LDRSH_POST = 2869,
ARM_t2LDRSH_PRE = 2870,
ARM_t2LDRSHi12 = 2871,
ARM_t2LDRSHi8 = 2872,
ARM_t2LDRSHpci = 2873,
ARM_t2LDRSHs = 2874,
ARM_t2LDRT = 2875,
ARM_t2LDR_POST = 2876,
ARM_t2LDR_PRE = 2877,
ARM_t2LDRi12 = 2878,
ARM_t2LDRi8 = 2879,
ARM_t2LDRpci = 2880,
ARM_t2LDRs = 2881,
ARM_t2LSLri = 2882,
ARM_t2LSLrr = 2883,
ARM_t2LSRri = 2884,
ARM_t2LSRrr = 2885,
ARM_t2MCR = 2886,
ARM_t2MCR2 = 2887,
ARM_t2MCRR = 2888,
ARM_t2MCRR2 = 2889,
ARM_t2MLA = 2890,
ARM_t2MLS = 2891,
ARM_t2MOVTi16 = 2892,
ARM_t2MOVi = 2893,
ARM_t2MOVi16 = 2894,
ARM_t2MOVr = 2895,
ARM_t2MOVsra_flag = 2896,
ARM_t2MOVsrl_flag = 2897,
ARM_t2MRC = 2898,
ARM_t2MRC2 = 2899,
ARM_t2MRRC = 2900,
ARM_t2MRRC2 = 2901,
ARM_t2MRS_AR = 2902,
ARM_t2MRS_M = 2903,
ARM_t2MRSbanked = 2904,
ARM_t2MRSsys_AR = 2905,
ARM_t2MSR_AR = 2906,
ARM_t2MSR_M = 2907,
ARM_t2MSRbanked = 2908,
ARM_t2MUL = 2909,
ARM_t2MVNi = 2910,
ARM_t2MVNr = 2911,
ARM_t2MVNs = 2912,
ARM_t2ORNri = 2913,
ARM_t2ORNrr = 2914,
ARM_t2ORNrs = 2915,
ARM_t2ORRri = 2916,
ARM_t2ORRrr = 2917,
ARM_t2ORRrs = 2918,
ARM_t2PKHBT = 2919,
ARM_t2PKHTB = 2920,
ARM_t2PLDWi12 = 2921,
ARM_t2PLDWi8 = 2922,
ARM_t2PLDWs = 2923,
ARM_t2PLDi12 = 2924,
ARM_t2PLDi8 = 2925,
ARM_t2PLDpci = 2926,
ARM_t2PLDs = 2927,
ARM_t2PLIi12 = 2928,
ARM_t2PLIi8 = 2929,
ARM_t2PLIpci = 2930,
ARM_t2PLIs = 2931,
ARM_t2QADD = 2932,
ARM_t2QADD16 = 2933,
ARM_t2QADD8 = 2934,
ARM_t2QASX = 2935,
ARM_t2QDADD = 2936,
ARM_t2QDSUB = 2937,
ARM_t2QSAX = 2938,
ARM_t2QSUB = 2939,
ARM_t2QSUB16 = 2940,
ARM_t2QSUB8 = 2941,
ARM_t2RBIT = 2942,
ARM_t2REV = 2943,
ARM_t2REV16 = 2944,
ARM_t2REVSH = 2945,
ARM_t2RFEDB = 2946,
ARM_t2RFEDBW = 2947,
ARM_t2RFEIA = 2948,
ARM_t2RFEIAW = 2949,
ARM_t2RORri = 2950,
ARM_t2RORrr = 2951,
ARM_t2RRX = 2952,
ARM_t2RSBri = 2953,
ARM_t2RSBrr = 2954,
ARM_t2RSBrs = 2955,
ARM_t2SADD16 = 2956,
ARM_t2SADD8 = 2957,
ARM_t2SASX = 2958,
ARM_t2SBCri = 2959,
ARM_t2SBCrr = 2960,
ARM_t2SBCrs = 2961,
ARM_t2SBFX = 2962,
ARM_t2SDIV = 2963,
ARM_t2SEL = 2964,
ARM_t2SETPAN = 2965,
ARM_t2SG = 2966,
ARM_t2SHADD16 = 2967,
ARM_t2SHADD8 = 2968,
ARM_t2SHASX = 2969,
ARM_t2SHSAX = 2970,
ARM_t2SHSUB16 = 2971,
ARM_t2SHSUB8 = 2972,
ARM_t2SMC = 2973,
ARM_t2SMLABB = 2974,
ARM_t2SMLABT = 2975,
ARM_t2SMLAD = 2976,
ARM_t2SMLADX = 2977,
ARM_t2SMLAL = 2978,
ARM_t2SMLALBB = 2979,
ARM_t2SMLALBT = 2980,
ARM_t2SMLALD = 2981,
ARM_t2SMLALDX = 2982,
ARM_t2SMLALTB = 2983,
ARM_t2SMLALTT = 2984,
ARM_t2SMLATB = 2985,
ARM_t2SMLATT = 2986,
ARM_t2SMLAWB = 2987,
ARM_t2SMLAWT = 2988,
ARM_t2SMLSD = 2989,
ARM_t2SMLSDX = 2990,
ARM_t2SMLSLD = 2991,
ARM_t2SMLSLDX = 2992,
ARM_t2SMMLA = 2993,
ARM_t2SMMLAR = 2994,
ARM_t2SMMLS = 2995,
ARM_t2SMMLSR = 2996,
ARM_t2SMMUL = 2997,
ARM_t2SMMULR = 2998,
ARM_t2SMUAD = 2999,
ARM_t2SMUADX = 3000,
ARM_t2SMULBB = 3001,
ARM_t2SMULBT = 3002,
ARM_t2SMULL = 3003,
ARM_t2SMULTB = 3004,
ARM_t2SMULTT = 3005,
ARM_t2SMULWB = 3006,
ARM_t2SMULWT = 3007,
ARM_t2SMUSD = 3008,
ARM_t2SMUSDX = 3009,
ARM_t2SRSDB = 3010,
ARM_t2SRSDB_UPD = 3011,
ARM_t2SRSIA = 3012,
ARM_t2SRSIA_UPD = 3013,
ARM_t2SSAT = 3014,
ARM_t2SSAT16 = 3015,
ARM_t2SSAX = 3016,
ARM_t2SSUB16 = 3017,
ARM_t2SSUB8 = 3018,
ARM_t2STC2L_OFFSET = 3019,
ARM_t2STC2L_OPTION = 3020,
ARM_t2STC2L_POST = 3021,
ARM_t2STC2L_PRE = 3022,
ARM_t2STC2_OFFSET = 3023,
ARM_t2STC2_OPTION = 3024,
ARM_t2STC2_POST = 3025,
ARM_t2STC2_PRE = 3026,
ARM_t2STCL_OFFSET = 3027,
ARM_t2STCL_OPTION = 3028,
ARM_t2STCL_POST = 3029,
ARM_t2STCL_PRE = 3030,
ARM_t2STC_OFFSET = 3031,
ARM_t2STC_OPTION = 3032,
ARM_t2STC_POST = 3033,
ARM_t2STC_PRE = 3034,
ARM_t2STL = 3035,
ARM_t2STLB = 3036,
ARM_t2STLEX = 3037,
ARM_t2STLEXB = 3038,
ARM_t2STLEXD = 3039,
ARM_t2STLEXH = 3040,
ARM_t2STLH = 3041,
ARM_t2STMDB = 3042,
ARM_t2STMDB_UPD = 3043,
ARM_t2STMIA = 3044,
ARM_t2STMIA_UPD = 3045,
ARM_t2STRBT = 3046,
ARM_t2STRB_POST = 3047,
ARM_t2STRB_PRE = 3048,
ARM_t2STRBi12 = 3049,
ARM_t2STRBi8 = 3050,
ARM_t2STRBs = 3051,
ARM_t2STRD_POST = 3052,
ARM_t2STRD_PRE = 3053,
ARM_t2STRDi8 = 3054,
ARM_t2STREX = 3055,
ARM_t2STREXB = 3056,
ARM_t2STREXD = 3057,
ARM_t2STREXH = 3058,
ARM_t2STRHT = 3059,
ARM_t2STRH_POST = 3060,
ARM_t2STRH_PRE = 3061,
ARM_t2STRHi12 = 3062,
ARM_t2STRHi8 = 3063,
ARM_t2STRHs = 3064,
ARM_t2STRT = 3065,
ARM_t2STR_POST = 3066,
ARM_t2STR_PRE = 3067,
ARM_t2STRi12 = 3068,
ARM_t2STRi8 = 3069,
ARM_t2STRs = 3070,
ARM_t2SUBS_PC_LR = 3071,
ARM_t2SUBri = 3072,
ARM_t2SUBri12 = 3073,
ARM_t2SUBrr = 3074,
ARM_t2SUBrs = 3075,
ARM_t2SXTAB = 3076,
ARM_t2SXTAB16 = 3077,
ARM_t2SXTAH = 3078,
ARM_t2SXTB = 3079,
ARM_t2SXTB16 = 3080,
ARM_t2SXTH = 3081,
ARM_t2TBB = 3082,
ARM_t2TBH = 3083,
ARM_t2TEQri = 3084,
ARM_t2TEQrr = 3085,
ARM_t2TEQrs = 3086,
ARM_t2TSB = 3087,
ARM_t2TSTri = 3088,
ARM_t2TSTrr = 3089,
ARM_t2TSTrs = 3090,
ARM_t2TT = 3091,
ARM_t2TTA = 3092,
ARM_t2TTAT = 3093,
ARM_t2TTT = 3094,
ARM_t2UADD16 = 3095,
ARM_t2UADD8 = 3096,
ARM_t2UASX = 3097,
ARM_t2UBFX = 3098,
ARM_t2UDF = 3099,
ARM_t2UDIV = 3100,
ARM_t2UHADD16 = 3101,
ARM_t2UHADD8 = 3102,
ARM_t2UHASX = 3103,
ARM_t2UHSAX = 3104,
ARM_t2UHSUB16 = 3105,
ARM_t2UHSUB8 = 3106,
ARM_t2UMAAL = 3107,
ARM_t2UMLAL = 3108,
ARM_t2UMULL = 3109,
ARM_t2UQADD16 = 3110,
ARM_t2UQADD8 = 3111,
ARM_t2UQASX = 3112,
ARM_t2UQSAX = 3113,
ARM_t2UQSUB16 = 3114,
ARM_t2UQSUB8 = 3115,
ARM_t2USAD8 = 3116,
ARM_t2USADA8 = 3117,
ARM_t2USAT = 3118,
ARM_t2USAT16 = 3119,
ARM_t2USAX = 3120,
ARM_t2USUB16 = 3121,
ARM_t2USUB8 = 3122,
ARM_t2UXTAB = 3123,
ARM_t2UXTAB16 = 3124,
ARM_t2UXTAH = 3125,
ARM_t2UXTB = 3126,
ARM_t2UXTB16 = 3127,
ARM_t2UXTH = 3128,
ARM_tADC = 3129,
ARM_tADDhirr = 3130,
ARM_tADDi3 = 3131,
ARM_tADDi8 = 3132,
ARM_tADDrSP = 3133,
ARM_tADDrSPi = 3134,
ARM_tADDrr = 3135,
ARM_tADDspi = 3136,
ARM_tADDspr = 3137,
ARM_tADR = 3138,
ARM_tAND = 3139,
ARM_tASRri = 3140,
ARM_tASRrr = 3141,
ARM_tB = 3142,
ARM_tBIC = 3143,
ARM_tBKPT = 3144,
ARM_tBL = 3145,
ARM_tBLXNSr = 3146,
ARM_tBLXi = 3147,
ARM_tBLXr = 3148,
ARM_tBX = 3149,
ARM_tBXNS = 3150,
ARM_tBcc = 3151,
ARM_tCBNZ = 3152,
ARM_tCBZ = 3153,
ARM_tCMNz = 3154,
ARM_tCMPhir = 3155,
ARM_tCMPi8 = 3156,
ARM_tCMPr = 3157,
ARM_tCPS = 3158,
ARM_tEOR = 3159,
ARM_tHINT = 3160,
ARM_tHLT = 3161,
ARM_tLDMIA = 3165,
ARM_tLDRBi = 3166,
ARM_tLDRBr = 3167,
ARM_tLDRHi = 3168,
ARM_tLDRHr = 3169,
ARM_tLDRSB = 3170,
ARM_tLDRSH = 3171,
ARM_tLDRi = 3172,
ARM_tLDRpci = 3173,
ARM_tLDRr = 3174,
ARM_tLDRspi = 3175,
ARM_tLSLri = 3176,
ARM_tLSLrr = 3177,
ARM_tLSRri = 3178,
ARM_tLSRrr = 3179,
ARM_tMOVSr = 3180,
ARM_tMOVi8 = 3181,
ARM_tMOVr = 3182,
ARM_tMUL = 3183,
ARM_tMVN = 3184,
ARM_tORR = 3185,
ARM_tPICADD = 3186,
ARM_tPOP = 3187,
ARM_tPUSH = 3188,
ARM_tREV = 3189,
ARM_tREV16 = 3190,
ARM_tREVSH = 3191,
ARM_tROR = 3192,
ARM_tRSB = 3193,
ARM_tSBC = 3194,
ARM_tSETEND = 3195,
ARM_tSTMIA_UPD = 3196,
ARM_tSTRBi = 3197,
ARM_tSTRBr = 3198,
ARM_tSTRHi = 3199,
ARM_tSTRHr = 3200,
ARM_tSTRi = 3201,
ARM_tSTRr = 3202,
ARM_tSTRspi = 3203,
ARM_tSUBi3 = 3204,
ARM_tSUBi8 = 3205,
ARM_tSUBrr = 3206,
ARM_tSUBspi = 3207,
ARM_tSVC = 3208,
ARM_tSXTB = 3209,
ARM_tSXTH = 3210,
ARM_tTRAP = 3211,
ARM_tTST = 3212,
ARM_tUDF = 3213,
ARM_tUXTB = 3214,
ARM_tUXTH = 3215,
ARM_t__brkdiv0 = 3216,
ARM_INSTRUCTION_LIST_END = 3217
};
#endif // GET_INSTRINFO_ENUM
#ifdef GET_INSTRINFO_MC_DESC
#undef GET_INSTRINFO_MC_DESC
#define nullptr 0
static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
static const MCOperandInfo OperandInfo31[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo32[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo33[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo34[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo35[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo36[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo37[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo38[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo39[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
static const MCOperandInfo OperandInfo40[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
static const MCOperandInfo OperandInfo41[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
static const MCOperandInfo OperandInfo42[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo43[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo44[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo45[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo46[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo47[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo48[] = { { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo49[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo50[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo51[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo52[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo53[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo54[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo55[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo56[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo57[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo58[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo59[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo60[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo61[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo62[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo63[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo64[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo65[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo66[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo67[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo68[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo69[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo70[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo71[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo72[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo73[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo74[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo75[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo76[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo77[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo78[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo79[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo80[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo81[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo82[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo83[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo84[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo85[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo86[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo87[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo88[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo89[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo90[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo91[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo92[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo93[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo94[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo95[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo96[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo97[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo98[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo99[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo100[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo101[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo102[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo103[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo104[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo105[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo106[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo107[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo108[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo109[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo110[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo111[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo112[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo113[] = { { ARM_tGPRwithpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo114[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo115[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo116[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo117[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo118[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo119[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo120[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo121[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo122[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo123[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo124[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo125[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo126[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo127[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo128[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo129[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo130[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo131[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo132[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo133[] = { { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo134[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, };
static const MCOperandInfo OperandInfo135[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo136[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo137[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo138[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo139[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo140[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo141[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo142[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo143[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo144[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo145[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo146[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo147[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo148[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo149[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo150[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo151[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo152[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo153[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo154[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo155[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo156[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo157[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo158[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo159[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo160[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo161[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo162[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo163[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo164[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo165[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo166[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo167[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo168[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo169[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, };
static const MCOperandInfo OperandInfo170[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, };
static const MCOperandInfo OperandInfo171[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo172[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo173[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo174[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo175[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo176[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo177[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo178[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo179[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo180[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo181[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo182[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo183[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo184[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo185[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo186[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo187[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo188[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo189[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo190[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo191[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo192[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo193[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo194[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo195[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo196[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo197[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo198[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo199[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo200[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo201[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo202[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo203[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo204[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo205[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo206[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo207[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo208[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo209[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo210[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo211[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo212[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo213[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo214[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo215[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo216[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo217[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo218[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo219[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo220[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo221[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo222[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo223[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo224[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo225[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo226[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo227[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo228[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo229[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo230[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo231[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo232[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo233[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo234[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo235[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo236[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo237[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo238[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo239[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo240[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo241[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo242[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo243[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo244[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo245[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo246[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo247[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo248[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo249[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo250[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo251[] = { { ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo252[] = { { ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo253[] = { { ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo254[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo255[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo256[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo257[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo258[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo259[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo260[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo261[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo262[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo263[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo264[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo265[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo266[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((4 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo267[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo268[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((4 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo269[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo270[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo271[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo272[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo273[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo274[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo275[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo276[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo277[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo278[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo279[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo280[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo281[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo282[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo283[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo284[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo285[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo286[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo287[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo288[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo289[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo290[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo291[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo292[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo293[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo294[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo295[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo296[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo297[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo298[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo299[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo300[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo301[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo302[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo303[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo304[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo305[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo306[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo307[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo308[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo309[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo310[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo311[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo312[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo313[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo314[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo315[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo316[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo317[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo318[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo319[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo320[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo321[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo322[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo323[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo324[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo325[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo326[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo327[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo328[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo329[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo330[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo331[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo332[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo333[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo334[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo335[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo336[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo337[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo338[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo339[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo340[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo341[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo342[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo343[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo344[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo345[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo346[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo347[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo348[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo349[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo350[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo351[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo352[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo353[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo354[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo355[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo356[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo357[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo358[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo359[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo360[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo361[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo362[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo363[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo364[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo365[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo366[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo367[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo368[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo369[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo370[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo371[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo372[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo373[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo374[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo375[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo376[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo377[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo378[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo379[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo380[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo381[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo382[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo383[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo384[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo385[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo386[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo387[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo388[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo389[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo390[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo391[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo392[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo393[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo394[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo395[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo396[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo397[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo398[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo399[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo400[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo401[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo402[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo403[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo404[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo405[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo406[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
static const MCOperandInfo OperandInfo407[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo408[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo409[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
static const MCOperandInfo OperandInfo410[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo411[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo412[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo413[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo414[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo415[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo416[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo417[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo418[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo419[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static const MCInstrDesc ARMInsts[] = {
{ 1, OperandInfo2 },
{ 0, nullptr },
{ 1, OperandInfo3 },
{ 1, OperandInfo3 },
{ 1, OperandInfo3 },
{ 1, OperandInfo3 },
{ 0, nullptr },
{ 3, OperandInfo4 },
{ 4, OperandInfo5 },
{ 1, OperandInfo2 },
{ 4, OperandInfo6 },
{ 3, OperandInfo4 },
{ 0, nullptr },
{ 1, OperandInfo2 },
{ 2, OperandInfo7 },
{ 2, OperandInfo7 },
{ 0, nullptr },
{ 1, OperandInfo3 },
{ 1, OperandInfo3 },
{ 2, OperandInfo8 },
{ 1, OperandInfo2 },
{ 6, OperandInfo9 },
{ 1, OperandInfo10 },
{ 0, nullptr },
{ 2, OperandInfo11 },
{ 1, OperandInfo2 },
{ 1, OperandInfo2 },
{ 0, nullptr },
{ 0, nullptr },
{ 0, nullptr },
{ 0, nullptr },
{ 2, OperandInfo11 },
{ 3, OperandInfo12 },
{ 1, OperandInfo2 },
{ 3, OperandInfo13 },
{ 3, OperandInfo13 },
{ 3, OperandInfo13 },
{ 3, OperandInfo13 },
{ 3, OperandInfo13 },
{ 3, OperandInfo13 },
{ 3, OperandInfo13 },
{ 3, OperandInfo13 },
{ 3, OperandInfo13 },
{ 3, OperandInfo13 },
{ 1, OperandInfo14 },
{ 1, OperandInfo14 },
{ 2, OperandInfo15 },
{ 2, OperandInfo15 },
{ 3, OperandInfo16 },
{ 2, OperandInfo17 },
{ 4, OperandInfo18 },
{ 2, OperandInfo17 },
{ 2, OperandInfo17 },
{ 2, OperandInfo17 },
{ 2, OperandInfo17 },
{ 2, OperandInfo17 },
{ 2, OperandInfo17 },
{ 2, OperandInfo17 },
{ 2, OperandInfo17 },
{ 5, OperandInfo19 },
{ 4, OperandInfo20 },
{ 3, OperandInfo21 },
{ 3, OperandInfo21 },
{ 3, OperandInfo21 },
{ 3, OperandInfo21 },
{ 3, OperandInfo21 },
{ 3, OperandInfo21 },
{ 3, OperandInfo21 },
{ 3, OperandInfo21 },
{ 3, OperandInfo21 },
{ 3, OperandInfo21 },
{ 3, OperandInfo21 },
{ 2, OperandInfo15 },
{ 1, OperandInfo14 },
{ 1, OperandInfo2 },
{ 1, OperandInfo2 },
{ 2, OperandInfo17 },
{ 2, OperandInfo17 },
{ 2, OperandInfo15 },
{ 2, OperandInfo15 },
{ 1, OperandInfo14 },
{ 3, OperandInfo16 },
{ 2, OperandInfo17 },
{ 2, OperandInfo17 },
{ 3, OperandInfo13 },
{ 3, OperandInfo13 },
{ 3, OperandInfo13 },
{ 4, OperandInfo22 },
{ 4, OperandInfo22 },
{ 4, OperandInfo20 },
{ 5, OperandInfo23 },
{ 5, OperandInfo23 },
{ 4, OperandInfo20 },
{ 4, OperandInfo20 },
{ 4, OperandInfo20 },
{ 4, OperandInfo20 },
{ 3, OperandInfo13 },
{ 3, OperandInfo13 },
{ 3, OperandInfo13 },
{ 3, OperandInfo13 },
{ 3, OperandInfo13 },
{ 4, OperandInfo24 },
{ 3, OperandInfo13 },
{ 3, OperandInfo13 },
{ 3, OperandInfo13 },
{ 2, OperandInfo25 },
{ 2, OperandInfo25 },
{ 2, OperandInfo25 },
{ 2, OperandInfo25 },
{ 2, OperandInfo25 },
{ 2, OperandInfo17 },
{ 2, OperandInfo17 },
{ 2, OperandInfo17 },
{ 2, OperandInfo17 },
{ 2, OperandInfo17 },
{ 2, OperandInfo17 },
{ 2, OperandInfo25 },
{ 3, OperandInfo26 },
{ 3, OperandInfo27 },
{ 1, OperandInfo2 },
{ 4, OperandInfo28 },
{ 3, OperandInfo29 },
{ 4, OperandInfo30 },
{ 2, OperandInfo25 },
{ 2, OperandInfo17 },
{ 2, OperandInfo15 },
{ 2, OperandInfo31 },
{ 5, OperandInfo32 },
{ 5, OperandInfo33 },
{ 6, OperandInfo34 },
{ 7, OperandInfo35 },
{ 4, OperandInfo36 },
{ 4, OperandInfo36 },
{ 6, OperandInfo37 },
{ 6, OperandInfo38 },
{ 1, OperandInfo39 },
{ 4, OperandInfo40 },
{ 6, OperandInfo41 },
{ 1, OperandInfo39 },
{ 1, OperandInfo42 },
{ 3, OperandInfo43 },
{ 3, OperandInfo44 },
{ 4, OperandInfo45 },
{ 2, OperandInfo46 },
{ 1, OperandInfo42 },
{ 5, OperandInfo47 },
{ 5, OperandInfo47 },
{ 5, OperandInfo48 },
{ 5, OperandInfo47 },
{ 3, OperandInfo4 },
{ 4, OperandInfo49 },
{ 1, OperandInfo3 },
{ 2, OperandInfo7 },
{ 0, nullptr },
{ 2, OperandInfo31 },
{ 2, OperandInfo31 },
{ 2, OperandInfo31 },
{ 0, nullptr },
{ 3, OperandInfo4 },
{ 3, OperandInfo4 },
{ 3, OperandInfo4 },
{ 3, OperandInfo4 },
{ 5, OperandInfo50 },
{ 4, OperandInfo51 },
{ 4, OperandInfo52 },
{ 2, OperandInfo46 },
{ 2, OperandInfo46 },
{ 2, OperandInfo46 },
{ 4, OperandInfo51 },
{ 4, OperandInfo53 },
{ 4, OperandInfo53 },
{ 6, OperandInfo37 },
{ 6, OperandInfo38 },
{ 6, OperandInfo37 },
{ 6, OperandInfo38 },
{ 5, OperandInfo54 },
{ 7, OperandInfo55 },
{ 5, OperandInfo56 },
{ 5, OperandInfo56 },
{ 5, OperandInfo57 },
{ 5, OperandInfo58 },
{ 6, OperandInfo59 },
{ 7, OperandInfo60 },
{ 1, OperandInfo61 },
{ 4, OperandInfo62 },
{ 2, OperandInfo46 },
{ 2, OperandInfo46 },
{ 3, OperandInfo63 },
{ 2, OperandInfo46 },
{ 2, OperandInfo31 },
{ 2, OperandInfo31 },
{ 6, OperandInfo64 },
{ 5, OperandInfo56 },
{ 5, OperandInfo32 },
{ 5, OperandInfo65 },
{ 5, OperandInfo65 },
{ 5, OperandInfo65 },
{ 5, OperandInfo65 },
{ 5, OperandInfo65 },
{ 5, OperandInfo65 },
{ 5, OperandInfo65 },
{ 5, OperandInfo65 },
{ 6, OperandInfo37 },
{ 6, OperandInfo38 },
{ 2, OperandInfo31 },
{ 5, OperandInfo66 },
{ 5, OperandInfo32 },
{ 6, OperandInfo34 },
{ 7, OperandInfo35 },
{ 9, OperandInfo67 },
{ 7, OperandInfo68 },
{ 3, OperandInfo69 },
{ 4, OperandInfo51 },
{ 7, OperandInfo70 },
{ 7, OperandInfo70 },
{ 7, OperandInfo71 },
{ 4, OperandInfo51 },
{ 7, OperandInfo70 },
{ 7, OperandInfo70 },
{ 3, OperandInfo72 },
{ 5, OperandInfo32 },
{ 5, OperandInfo33 },
{ 6, OperandInfo34 },
{ 7, OperandInfo35 },
{ 1, OperandInfo39 },
{ 1, OperandInfo73 },
{ 1, OperandInfo61 },
{ 1, OperandInfo3 },
{ 1, OperandInfo73 },
{ 0, nullptr },
{ 9, OperandInfo67 },
{ 7, OperandInfo68 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 7, OperandInfo75 },
{ 7, OperandInfo75 },
{ 7, OperandInfo75 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 7, OperandInfo75 },
{ 7, OperandInfo75 },
{ 7, OperandInfo75 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 7, OperandInfo75 },
{ 7, OperandInfo75 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 6, OperandInfo77 },
{ 6, OperandInfo77 },
{ 6, OperandInfo77 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 6, OperandInfo77 },
{ 6, OperandInfo77 },
{ 6, OperandInfo77 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 7, OperandInfo75 },
{ 7, OperandInfo75 },
{ 7, OperandInfo75 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 7, OperandInfo75 },
{ 7, OperandInfo75 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 6, OperandInfo77 },
{ 6, OperandInfo77 },
{ 6, OperandInfo77 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 6, OperandInfo77 },
{ 6, OperandInfo77 },
{ 6, OperandInfo77 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 6, OperandInfo77 },
{ 6, OperandInfo77 },
{ 6, OperandInfo77 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 6, OperandInfo77 },
{ 6, OperandInfo77 },
{ 6, OperandInfo77 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 7, OperandInfo75 },
{ 7, OperandInfo75 },
{ 7, OperandInfo75 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 7, OperandInfo75 },
{ 7, OperandInfo75 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 6, OperandInfo77 },
{ 6, OperandInfo77 },
{ 6, OperandInfo77 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 6, OperandInfo77 },
{ 6, OperandInfo77 },
{ 6, OperandInfo77 },
{ 1, OperandInfo78 },
{ 5, OperandInfo79 },
{ 1, OperandInfo80 },
{ 5, OperandInfo81 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 7, OperandInfo75 },
{ 7, OperandInfo75 },
{ 7, OperandInfo75 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 7, OperandInfo75 },
{ 7, OperandInfo75 },
{ 7, OperandInfo75 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 7, OperandInfo75 },
{ 7, OperandInfo75 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 7, OperandInfo75 },
{ 7, OperandInfo75 },
{ 7, OperandInfo75 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 7, OperandInfo75 },
{ 7, OperandInfo75 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 6, OperandInfo77 },
{ 6, OperandInfo77 },
{ 6, OperandInfo77 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 6, OperandInfo77 },
{ 6, OperandInfo77 },
{ 6, OperandInfo77 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 7, OperandInfo75 },
{ 7, OperandInfo75 },
{ 7, OperandInfo75 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 6, OperandInfo74 },
{ 7, OperandInfo75 },
{ 7, OperandInfo75 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 6, OperandInfo77 },
{ 6, OperandInfo77 },
{ 6, OperandInfo77 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 5, OperandInfo76 },
{ 6, OperandInfo77 },
{ 6, OperandInfo77 },
{ 6, OperandInfo77 },
{ 0, nullptr },
{ 1, OperandInfo42 },
{ 2, OperandInfo82 },
{ 5, OperandInfo83 },
{ 5, OperandInfo84 },
{ 6, OperandInfo85 },
{ 3, OperandInfo43 },
{ 5, OperandInfo50 },
{ 4, OperandInfo86 },
{ 4, OperandInfo52 },
{ 4, OperandInfo86 },
{ 4, OperandInfo86 },
{ 4, OperandInfo86 },
{ 3, OperandInfo87 },
{ 4, OperandInfo52 },
{ 4, OperandInfo88 },
{ 4, OperandInfo88 },
{ 6, OperandInfo89 },
{ 5, OperandInfo90 },
{ 5, OperandInfo90 },
{ 5, OperandInfo91 },
{ 6, OperandInfo89 },
{ 6, OperandInfo89 },
{ 5, OperandInfo92 },
{ 6, OperandInfo89 },
{ 5, OperandInfo93 },
{ 6, OperandInfo94 },
{ 4, OperandInfo95 },
{ 2, OperandInfo96 },
{ 3, OperandInfo87 },
{ 2, OperandInfo96 },
{ 5, OperandInfo93 },
{ 6, OperandInfo94 },
{ 5, OperandInfo90 },
{ 5, OperandInfo97 },
{ 6, OperandInfo98 },
{ 6, OperandInfo99 },
{ 6, OperandInfo99 },
{ 6, OperandInfo99 },
{ 5, OperandInfo83 },
{ 5, OperandInfo84 },
{ 6, OperandInfo85 },
{ 4, OperandInfo49 },
{ 4, OperandInfo49 },
{ 3, OperandInfo100 },
{ 3, OperandInfo101 },
{ 3, OperandInfo101 },
{ 3, OperandInfo100 },
{ 3, OperandInfo102 },
{ 2, OperandInfo8 },
{ 2, OperandInfo8 },
{ 3, OperandInfo103 },
{ 2, OperandInfo104 },
{ 1, OperandInfo42 },
{ 2, OperandInfo105 },
{ 3, OperandInfo106 },
{ 3, OperandInfo107 },
{ 5, OperandInfo50 },
{ 4, OperandInfo108 },
{ 2, OperandInfo104 },
{ 2, OperandInfo104 },
{ 5, OperandInfo109 },
{ 3, OperandInfo63 },
{ 4, OperandInfo110 },
{ 4, OperandInfo110 },
{ 5, OperandInfo111 },
{ 3, OperandInfo112 },
{ 3, OperandInfo100 },
{ 3, OperandInfo101 },
{ 3, OperandInfo101 },
{ 3, OperandInfo100 },
{ 3, OperandInfo107 },
{ 3, OperandInfo107 },
{ 1, OperandInfo73 },
{ 4, OperandInfo113 },
{ 4, OperandInfo113 },
{ 0, nullptr },
{ 6, OperandInfo37 },
{ 6, OperandInfo114 },
{ 7, OperandInfo115 },
{ 8, OperandInfo116 },
{ 6, OperandInfo37 },
{ 6, OperandInfo114 },
{ 7, OperandInfo115 },
{ 8, OperandInfo117 },
{ 4, OperandInfo52 },
{ 3, OperandInfo118 },
{ 3, OperandInfo118 },
{ 2, OperandInfo119 },
{ 2, OperandInfo119 },
{ 6, OperandInfo37 },
{ 6, OperandInfo114 },
{ 7, OperandInfo115 },
{ 8, OperandInfo117 },
{ 5, OperandInfo56 },
{ 6, OperandInfo120 },
{ 6, OperandInfo37 },
{ 6, OperandInfo114 },
{ 7, OperandInfo115 },
{ 8, OperandInfo117 },
{ 1, OperandInfo2 },
{ 1, OperandInfo39 },
{ 1, OperandInfo61 },
{ 3, OperandInfo103 },
{ 1, OperandInfo39 },
{ 3, OperandInfo107 },
{ 1, OperandInfo61 },
{ 3, OperandInfo103 },
{ 2, OperandInfo105 },
{ 3, OperandInfo103 },
{ 3, OperandInfo107 },
{ 8, OperandInfo121 },
{ 6, OperandInfo122 },
{ 0, nullptr },
{ 4, OperandInfo123 },
{ 4, OperandInfo52 },
{ 4, OperandInfo123 },
{ 5, OperandInfo124 },
{ 6, OperandInfo125 },
{ 4, OperandInfo52 },
{ 4, OperandInfo123 },
{ 5, OperandInfo124 },
{ 6, OperandInfo125 },
{ 1, OperandInfo2 },
{ 2, OperandInfo7 },
{ 3, OperandInfo126 },
{ 3, OperandInfo127 },
{ 3, OperandInfo127 },
{ 3, OperandInfo127 },
{ 3, OperandInfo127 },
{ 3, OperandInfo127 },
{ 3, OperandInfo127 },
{ 3, OperandInfo128 },
{ 1, OperandInfo2 },
{ 1, OperandInfo2 },
{ 6, OperandInfo37 },
{ 6, OperandInfo114 },
{ 7, OperandInfo115 },
{ 8, OperandInfo117 },
{ 2, OperandInfo105 },
{ 4, OperandInfo129 },
{ 4, OperandInfo130 },
{ 4, OperandInfo131 },
{ 5, OperandInfo50 },
{ 4, OperandInfo132 },
{ 5, OperandInfo50 },
{ 2, OperandInfo105 },
{ 5, OperandInfo50 },
{ 4, OperandInfo132 },
{ 5, OperandInfo50 },
{ 3, OperandInfo128 },
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{ 6, OperandInfo369 },
{ 6, OperandInfo393 },
{ 5, OperandInfo388 },
{ 6, OperandInfo389 },
{ 5, OperandInfo388 },
{ 5, OperandInfo366 },
{ 6, OperandInfo390 },
{ 6, OperandInfo390 },
{ 5, OperandInfo366 },
{ 5, OperandInfo366 },
{ 6, OperandInfo391 },
{ 5, OperandInfo366 },
{ 6, OperandInfo394 },
{ 6, OperandInfo394 },
{ 5, OperandInfo65 },
{ 5, OperandInfo65 },
{ 6, OperandInfo371 },
{ 3, OperandInfo128 },
{ 6, OperandInfo353 },
{ 5, OperandInfo354 },
{ 6, OperandInfo355 },
{ 7, OperandInfo356 },
{ 6, OperandInfo381 },
{ 6, OperandInfo381 },
{ 6, OperandInfo381 },
{ 5, OperandInfo97 },
{ 5, OperandInfo97 },
{ 5, OperandInfo97 },
{ 4, OperandInfo395 },
{ 4, OperandInfo395 },
{ 4, OperandInfo86 },
{ 4, OperandInfo360 },
{ 5, OperandInfo361 },
{ 3, OperandInfo128 },
{ 4, OperandInfo86 },
{ 4, OperandInfo360 },
{ 5, OperandInfo361 },
{ 4, OperandInfo396 },
{ 4, OperandInfo396 },
{ 4, OperandInfo396 },
{ 4, OperandInfo396 },
{ 5, OperandInfo378 },
{ 5, OperandInfo378 },
{ 5, OperandInfo378 },
{ 6, OperandInfo384 },
{ 1, OperandInfo2 },
{ 5, OperandInfo378 },
{ 5, OperandInfo378 },
{ 5, OperandInfo378 },
{ 5, OperandInfo378 },
{ 5, OperandInfo378 },
{ 5, OperandInfo378 },
{ 5, OperandInfo378 },
{ 8, OperandInfo385 },
{ 8, OperandInfo385 },
{ 6, OperandInfo373 },
{ 5, OperandInfo378 },
{ 5, OperandInfo378 },
{ 5, OperandInfo378 },
{ 5, OperandInfo378 },
{ 5, OperandInfo378 },
{ 5, OperandInfo378 },
{ 5, OperandInfo378 },
{ 6, OperandInfo373 },
{ 6, OperandInfo386 },
{ 5, OperandInfo387 },
{ 5, OperandInfo378 },
{ 5, OperandInfo378 },
{ 5, OperandInfo378 },
{ 6, OperandInfo381 },
{ 6, OperandInfo381 },
{ 6, OperandInfo381 },
{ 5, OperandInfo97 },
{ 5, OperandInfo97 },
{ 5, OperandInfo97 },
{ 6, OperandInfo397 },
{ 5, OperandInfo58 },
{ 6, OperandInfo398 },
{ 6, OperandInfo399 },
{ 5, OperandInfo400 },
{ 5, OperandInfo401 },
{ 6, OperandInfo402 },
{ 5, OperandInfo403 },
{ 5, OperandInfo404 },
{ 4, OperandInfo405 },
{ 6, OperandInfo397 },
{ 6, OperandInfo398 },
{ 6, OperandInfo397 },
{ 3, OperandInfo107 },
{ 6, OperandInfo397 },
{ 1, OperandInfo2 },
{ 3, OperandInfo406 },
{ 3, OperandInfo407 },
{ 3, OperandInfo406 },
{ 3, OperandInfo408 },
{ 3, OperandInfo103 },
{ 3, OperandInfo103 },
{ 3, OperandInfo107 },
{ 2, OperandInfo409 },
{ 2, OperandInfo409 },
{ 4, OperandInfo410 },
{ 4, OperandInfo123 },
{ 4, OperandInfo108 },
{ 4, OperandInfo410 },
{ 2, OperandInfo7 },
{ 6, OperandInfo397 },
{ 3, OperandInfo128 },
{ 1, OperandInfo2 },
{ 2, OperandInfo31 },
{ 2, OperandInfo31 },
{ 2, OperandInfo363 },
{ 4, OperandInfo411 },
{ 5, OperandInfo412 },
{ 5, OperandInfo413 },
{ 5, OperandInfo412 },
{ 5, OperandInfo413 },
{ 5, OperandInfo413 },
{ 5, OperandInfo413 },
{ 5, OperandInfo412 },
{ 4, OperandInfo405 },
{ 5, OperandInfo413 },
{ 5, OperandInfo414 },
{ 6, OperandInfo398 },
{ 6, OperandInfo397 },
{ 6, OperandInfo398 },
{ 6, OperandInfo397 },
{ 2, OperandInfo363 },
{ 5, OperandInfo415 },
{ 4, OperandInfo123 },
{ 6, OperandInfo416 },
{ 5, OperandInfo417 },
{ 6, OperandInfo397 },
{ 3, OperandInfo418 },
{ 3, OperandInfo112 },
{ 3, OperandInfo112 },
{ 4, OperandInfo410 },
{ 4, OperandInfo410 },
{ 4, OperandInfo410 },
{ 6, OperandInfo397 },
{ 5, OperandInfo417 },
{ 6, OperandInfo397 },
{ 1, OperandInfo2 },
{ 5, OperandInfo419 },
{ 5, OperandInfo412 },
{ 5, OperandInfo413 },
{ 5, OperandInfo412 },
{ 5, OperandInfo413 },
{ 5, OperandInfo412 },
{ 5, OperandInfo413 },
{ 5, OperandInfo414 },
{ 6, OperandInfo398 },
{ 6, OperandInfo399 },
{ 6, OperandInfo402 },
{ 5, OperandInfo403 },
{ 3, OperandInfo128 },
{ 4, OperandInfo410 },
{ 4, OperandInfo410 },
{ 0, nullptr },
{ 4, OperandInfo410 },
{ 1, OperandInfo2 },
{ 4, OperandInfo410 },
{ 4, OperandInfo410 },
{ 0, nullptr },
};
#endif // GET_INSTRINFO_MC_DESC
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