mirror of
https://github.com/capstone-engine/capstone.git
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508 lines
12 KiB
C
508 lines
12 KiB
C
//===- TriCoreInstPrinter.cpp - Convert TriCore MCInst to assembly syntax -===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an TriCore MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
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#ifdef CAPSTONE_HAS_TRICORE
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#include <platform.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "../../MCInst.h"
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#include "../../MCRegisterInfo.h"
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#include "../../MathExtras.h"
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#include "../../SStream.h"
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#include "../../utils.h"
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#include "TriCoreInstPrinter.h"
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#include "TriCoreMapping.h"
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static const char *getRegisterName(unsigned RegNo);
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static void printInstruction(MCInst *, uint64_t, SStream *);
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static void printOperand(MCInst *MI, int OpNum, SStream *O);
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void TriCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
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{
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/*
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if (((cs_struct *)ud)->detail != CS_OPT_ON)
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return;
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*/
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}
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#define GET_INSTRINFO_ENUM
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#include "TriCoreGenInstrInfo.inc"
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#define GET_REGINFO_ENUM
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#include "TriCoreGenRegisterInfo.inc"
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static inline void fill_mem(cs_tricore *tc, uint8_t base, int32_t disp);
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static bool fixup_op_mem(MCInst *pInst, unsigned int reg, int32_t disp);
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static inline void fill_tricore_register(MCInst *MI, uint32_t reg)
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{
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if (!(MI->csh->detail == CS_OPT_ON && MI->flat_insn->detail))
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return;
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cs_tricore *tricore = &MI->flat_insn->detail->tricore;
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tricore->operands[tricore->op_count].type = TRICORE_OP_REG;
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tricore->operands[tricore->op_count].reg = reg;
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tricore->op_count++;
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}
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static inline void fill_tricore_imm(MCInst *MI, int32_t imm)
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{
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if (!(MI->csh->detail == CS_OPT_ON && MI->flat_insn->detail))
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return;
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cs_tricore *tricore = &MI->flat_insn->detail->tricore;
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if (tricore->op_count >= 1 &&
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tricore->operands[tricore->op_count - 1].type == TRICORE_OP_REG &&
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fixup_op_mem(MI, tricore->operands[tricore->op_count - 1].reg,
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imm)) {
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return;
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}
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tricore->operands[tricore->op_count].type = TRICORE_OP_IMM;
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tricore->operands[tricore->op_count].imm = imm;
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tricore->op_count++;
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}
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static bool fixup_op_mem(MCInst *pInst, unsigned int reg, int32_t disp)
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{
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switch (TriCore_map_insn_id(pInst->csh, pInst->Opcode)) {
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case TRICORE_INS_LDMST:
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case TRICORE_INS_LDLCX:
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case TRICORE_INS_LD_A:
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case TRICORE_INS_LD_B:
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case TRICORE_INS_LD_BU:
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case TRICORE_INS_LD_H:
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case TRICORE_INS_LD_HU:
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case TRICORE_INS_LD_D:
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case TRICORE_INS_LD_DA:
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case TRICORE_INS_LD_W:
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case TRICORE_INS_LD_Q:
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case TRICORE_INS_STLCX:
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case TRICORE_INS_STUCX:
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case TRICORE_INS_ST_A:
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case TRICORE_INS_ST_B:
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case TRICORE_INS_ST_H:
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case TRICORE_INS_ST_D:
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case TRICORE_INS_ST_DA:
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case TRICORE_INS_ST_W:
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case TRICORE_INS_ST_Q:
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case TRICORE_INS_CACHEI_I:
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case TRICORE_INS_CACHEI_W:
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case TRICORE_INS_CACHEI_WI:
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case TRICORE_INS_CACHEA_I:
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case TRICORE_INS_CACHEA_W:
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case TRICORE_INS_CACHEA_WI:
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case TRICORE_INS_CMPSWAP_W:
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case TRICORE_INS_SWAP_A:
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case TRICORE_INS_SWAP_W:
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case TRICORE_INS_SWAPMSK_W:
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case TRICORE_INS_LEA:
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case TRICORE_INS_LHA: {
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switch (MCInst_getOpcode(pInst)) {
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case TRICORE_LDMST_abs:
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case TRICORE_LDLCX_abs:
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case TRICORE_LD_A_abs:
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case TRICORE_LD_B_abs:
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case TRICORE_LD_BU_abs:
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case TRICORE_LD_H_abs:
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case TRICORE_LD_HU_abs:
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case TRICORE_LD_D_abs:
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case TRICORE_LD_DA_abs:
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case TRICORE_LD_W_abs:
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case TRICORE_LD_Q_abs:
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case TRICORE_STLCX_abs:
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case TRICORE_STUCX_abs:
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case TRICORE_ST_A_abs:
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case TRICORE_ST_B_abs:
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case TRICORE_ST_H_abs:
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case TRICORE_ST_D_abs:
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case TRICORE_ST_DA_abs:
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case TRICORE_ST_W_abs:
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case TRICORE_ST_Q_abs:
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case TRICORE_SWAP_A_abs:
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case TRICORE_SWAP_W_abs:
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case TRICORE_LEA_abs:
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case TRICORE_LHA_abs: {
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return false;
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}
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}
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cs_tricore *tc = &pInst->flat_insn->detail->tricore;
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fill_mem(tc, reg, disp);
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return true;
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}
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}
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return false;
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}
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static inline void fill_mem(cs_tricore *tc, uint8_t base, int32_t disp)
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{
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cs_tricore_op *op = &tc->operands[tc->op_count - 1];
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op->type = TRICORE_OP_MEM;
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op->mem.base = base;
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op->mem.disp = disp;
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}
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static void printOperand(MCInst *MI, int OpNum, SStream *O)
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{
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MCOperand *Op;
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if (OpNum >= MI->size)
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return;
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Op = MCInst_getOperand(MI, OpNum);
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if (MCOperand_isReg(Op)) {
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unsigned reg = MCOperand_getReg(Op);
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SStream_concat(O, "%%%s", getRegisterName(reg));
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fill_tricore_register(MI, reg);
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} else if (MCOperand_isImm(Op)) {
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int64_t Imm = MCOperand_getImm(Op);
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if (Imm >= 0) {
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if (Imm > HEX_THRESHOLD)
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SStream_concat(O, "0x%" PRIx64, Imm);
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else
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SStream_concat(O, "%" PRIu64, Imm);
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} else {
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if (Imm < -HEX_THRESHOLD)
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SStream_concat(O, "-0x%" PRIx64, -Imm);
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else
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SStream_concat(O, "-%" PRIu64, -Imm);
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}
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fill_tricore_imm(MI, (int32_t)Imm);
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}
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}
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static inline unsigned int get_msb(unsigned int value)
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{
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unsigned int msb = 0;
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while (value > 0) {
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value >>= 1; // Shift bits to the right
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msb++; // Increment the position of the MSB
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}
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return msb;
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}
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static inline int32_t sign_ext_n(int32_t imm, unsigned n)
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{
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n = get_msb(imm) > n ? get_msb(imm) : n;
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int32_t mask = 1 << (n - 1);
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int32_t sign_extended = (imm ^ mask) - mask;
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return sign_extended;
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}
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static void print_sign_ext(MCInst *MI, int OpNum, SStream *O, unsigned n)
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{
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MCOperand *MO = MCInst_getOperand(MI, OpNum);
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if (MCOperand_isImm(MO)) {
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int32_t imm = (int32_t)MCOperand_getImm(MO);
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imm = sign_ext_n(imm, n);
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printInt32(O, imm);
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fill_tricore_imm(MI, imm);
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} else
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printOperand(MI, OpNum, O);
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}
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static void off4_fixup(MCInst *MI, uint64_t *off4)
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{
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switch (MCInst_getOpcode(MI)) {
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case TRICORE_LD_A_slro:
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case TRICORE_LD_A_sro:
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case TRICORE_LD_W_slro:
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case TRICORE_LD_W_sro:
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case TRICORE_ST_A_sro:
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case TRICORE_ST_A_ssro:
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case TRICORE_ST_W_sro:
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case TRICORE_ST_W_ssro: {
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*off4 *= 4;
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break;
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}
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case TRICORE_LD_H_sro:
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case TRICORE_LD_H_slro:
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case TRICORE_ST_H_sro:
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case TRICORE_ST_H_ssro: {
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*off4 *= 2;
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break;
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}
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}
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}
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static void print_zero_ext(MCInst *MI, int OpNum, SStream *O, unsigned n)
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{
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MCOperand *MO = MCInst_getOperand(MI, OpNum);
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if (MCOperand_isImm(MO)) {
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uint64_t imm = MCOperand_getImm(MO);
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for (unsigned i = n + 1; i < 32; ++i) {
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imm &= ~(1 << i);
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}
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if (n == 4) {
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off4_fixup(MI, &imm);
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}
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if (imm >= 0) {
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if (imm > HEX_THRESHOLD)
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SStream_concat(O, "0x%x", imm);
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else
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SStream_concat(O, "%u", imm);
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} else {
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if (imm < -HEX_THRESHOLD)
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SStream_concat(O, "-0x%x", -imm);
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else
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SStream_concat(O, "-%u", -imm);
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}
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fill_tricore_imm(MI, imm);
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} else
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printOperand(MI, OpNum, O);
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}
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static void printOff18Imm(MCInst *MI, int OpNum, SStream *O)
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{
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MCOperand *MO = MCInst_getOperand(MI, OpNum);
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if (MCOperand_isImm(MO)) {
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uint32_t imm = (uint32_t)MCOperand_getImm(MO);
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imm = ((imm & 0x3C000) << 14) | (imm & 0x3fff);
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SStream_concat(O, "0x%x", imm);
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fill_tricore_imm(MI, (int32_t)imm);
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} else
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printOperand(MI, OpNum, O);
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}
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static void printDisp24Imm(MCInst *MI, int OpNum, SStream *O)
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{
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MCOperand *MO = MCInst_getOperand(MI, OpNum);
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if (MCOperand_isImm(MO)) {
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uint32_t disp = MCOperand_getImm(MO);
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switch (MCInst_getOpcode(MI)) {
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case TRICORE_CALL_b:
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case TRICORE_FCALL_b: {
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disp = (int32_t)MI->address + sign_ext_n(disp * 2, 24);
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break;
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}
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case TRICORE_CALLA_b:
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case TRICORE_FCALLA_b:
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case TRICORE_JA_b:
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case TRICORE_JLA_b:
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// = {disp24[23:20], 7’b0000000, disp24[19:0], 1’b0};
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disp = ((disp & 0xf00000) << 28) |
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((disp & 0xfffff) << 1);
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break;
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case TRICORE_J_b:
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case TRICORE_JL_b:
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disp = (int32_t)MI->address + sign_ext_n(disp, 24) * 2;
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break;
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}
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printUInt32(O, disp);
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fill_tricore_imm(MI, disp);
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} else
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printOperand(MI, OpNum, O);
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}
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static void printDisp15Imm(MCInst *MI, int OpNum, SStream *O)
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{
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MCOperand *MO = MCInst_getOperand(MI, OpNum);
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if (MCOperand_isImm(MO)) {
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uint32_t disp = MCOperand_getImm(MO);
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switch (MCInst_getOpcode(MI)) {
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case TRICORE_JEQ_brc:
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case TRICORE_JEQ_brr:
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case TRICORE_JEQ_A_brr:
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case TRICORE_JGE_brc:
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case TRICORE_JGE_brr:
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case TRICORE_JGE_U_brc:
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case TRICORE_JGE_U_brr:
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case TRICORE_JLT_brc:
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case TRICORE_JLT_brr:
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case TRICORE_JLT_U_brc:
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case TRICORE_JLT_U_brr:
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case TRICORE_JNE_brc:
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case TRICORE_JNE_brr:
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case TRICORE_JNE_A_brr:
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case TRICORE_JNED_brc:
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case TRICORE_JNED_brr:
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case TRICORE_JNEI_brc:
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case TRICORE_JNEI_brr:
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case TRICORE_JNZ_A_brr:
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case TRICORE_JNZ_T_brn:
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case TRICORE_JZ_A_brr:
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case TRICORE_JZ_T_brn:
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disp = (int32_t)MI->address + sign_ext_n(disp, 15) * 2;
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break;
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case TRICORE_LOOP_brr:
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case TRICORE_LOOPU_brr:
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disp = (int32_t)MI->address + sign_ext_n(disp * 2, 15);
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break;
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default:
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// handle other cases, if any
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break;
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}
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printUInt32(O, disp);
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fill_tricore_imm(MI, disp);
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} else
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printOperand(MI, OpNum, O);
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}
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static void printDisp8Imm(MCInst *MI, int OpNum, SStream *O)
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{
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MCOperand *MO = MCInst_getOperand(MI, OpNum);
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if (MCOperand_isImm(MO)) {
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uint32_t disp = MCOperand_getImm(MO);
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switch (MCInst_getOpcode(MI)) {
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case TRICORE_CALL_sb:
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disp = (int32_t)MI->address + sign_ext_n(2 * disp, 8);
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break;
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case TRICORE_J_sb:
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case TRICORE_JNZ_sb:
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case TRICORE_JZ_sb:
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disp = (int32_t)MI->address + sign_ext_n(disp, 8) * 2;
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break;
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default:
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// handle other cases, if any
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break;
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}
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printUInt32(O, disp);
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fill_tricore_imm(MI, disp);
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} else
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printOperand(MI, OpNum, O);
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}
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static void printDisp4Imm(MCInst *MI, int OpNum, SStream *O)
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{
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MCOperand *MO = MCInst_getOperand(MI, OpNum);
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if (MCOperand_isImm(MO)) {
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uint32_t disp = MCOperand_getImm(MO);
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switch (MCInst_getOpcode(MI)) {
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case TRICORE_JEQ_sbc1:
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case TRICORE_JEQ_sbr1:
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case TRICORE_JGEZ_sbr:
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case TRICORE_JGTZ_sbr:
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case TRICORE_JLEZ_sbr:
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case TRICORE_JLTZ_sbr:
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case TRICORE_JNE_sbc1:
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case TRICORE_JNE_sbr1:
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case TRICORE_JNZ_sbr:
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case TRICORE_JNZ_A_sbr:
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case TRICORE_JNZ_T_sbrn:
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case TRICORE_JZ_sbr:
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case TRICORE_JZ_A_sbr:
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case TRICORE_JZ_T_sbrn:
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disp = (int32_t)MI->address + disp * 2;
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break;
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case TRICORE_JEQ_sbc2:
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case TRICORE_JEQ_sbr2:
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case TRICORE_JNE_sbc2:
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case TRICORE_JNE_sbr2:
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disp = (int32_t)MI->address + (disp + 16) * 2;
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break;
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case TRICORE_LOOP_sbr:
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// {27b’111111111111111111111111111, disp4, 0};
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disp = (int32_t)MI->address +
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((0b111111111111111111111111111 << 5) |
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(disp << 1));
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break;
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default:
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// handle other cases, if any
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break;
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}
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printUInt32(O, disp);
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fill_tricore_imm(MI, disp);
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} else
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printOperand(MI, OpNum, O);
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}
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#define printSExtImm_(n) \
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static void printSExtImm_##n(MCInst *MI, int OpNum, SStream *O) \
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{ \
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print_sign_ext(MI, OpNum, O, n); \
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}
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#define printZExtImm_(n) \
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static void printZExtImm_##n(MCInst *MI, int OpNum, SStream *O) \
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{ \
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print_zero_ext(MI, OpNum, O, n); \
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}
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// clang-format off
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printSExtImm_(16)
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printSExtImm_(10)
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printSExtImm_(9)
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printSExtImm_(4)
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printZExtImm_(16)
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printZExtImm_(9)
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printZExtImm_(8)
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printZExtImm_(4)
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printZExtImm_(2);
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// clang-format on
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static void printOExtImm_4(MCInst *MI, int OpNum, SStream *O)
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{
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MCOperand *MO = MCInst_getOperand(MI, OpNum);
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if (MCOperand_isImm(MO)) {
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uint32_t imm = MCOperand_getImm(MO);
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// {27b’111111111111111111111111111, disp4, 0};
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imm = 0b11111111111111111111111111100000 | (imm << 1);
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printInt32(O, imm);
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fill_tricore_imm(MI, imm);
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} else
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printOperand(MI, OpNum, O);
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||
}
|
||
|
||
/// Returned by getMnemonic() of the AsmPrinters.
|
||
typedef struct {
|
||
const char *first; // Menmonic
|
||
uint64_t second; // Bits
|
||
} MnemonicBitsInfo;
|
||
|
||
static void set_mem_access(MCInst *MI, unsigned int access)
|
||
{
|
||
// TODO: TriCore
|
||
}
|
||
|
||
MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O);
|
||
bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *OS);
|
||
|
||
#define PRINT_ALIAS_INSTR
|
||
|
||
#include "TriCoreGenAsmWriter.inc"
|
||
|
||
const char *TriCore_getRegisterName(csh handle, unsigned int id)
|
||
{
|
||
#ifndef CAPSTONE_DIET
|
||
return getRegisterName(id);
|
||
#else
|
||
return NULL;
|
||
#endif
|
||
}
|
||
|
||
void TriCore_printInst(MCInst *MI, SStream *O, void *Info)
|
||
{
|
||
printInstruction(MI, MI->address, O);
|
||
}
|
||
|
||
#endif
|