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e8d1f1d4d2
* Added new M680X target. Supports M6800/1/2/3/9, HD6301 * M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT * M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec > k cpu type, no default. * M680X: Add python bindings. Added python tests. * M680X: Added cpu types to usage message. * cstool: Avoid segfault for invalid <arch+mode>. * Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched. * M680X: Update CMake/make for m680x support. Update .gitignore. * M680X: Reduce compiler warnings. * M680X: Reduce compiler warnings. * M680X: Reduce compiler warnings. * M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). * M680X: Add ocaml bindings and tests. * M680X: Add java bindings and tests. * M680X: Added tests for all indexed addressing modes. C/Python/Ocaml * M680X: Naming, use page1 for PAGE1 instructions (without prefix). * M680X: Naming, use page1 for PAGE1 instructions (without prefix). * M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml. * M680X: Added access property to cs_m680x_op. * M680X: Added operand size. * M680X: Remove compiler warnings. * M680X: Added READ/WRITE access property per operator. * M680X: Make reg_inherent_hdlr independent of CPU type. * M680X: Add HD6309 support + bug fixes * M680X: Remove errors and warning. * M680X: Add Bcc/LBcc to group BRAREL (relative branch). * M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN. * M680X: Remove LBRN from group BRAREL. * M680X: Refactored cpu_type initialization for better readability. * M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX. * M680X: Remove typo in cstool.c * M680X: Some format improvements in changed_regs. * M680X: Remove insn id string list from tests (C/python/java/ocaml). * M680X: SEXW, set access of reg. D to WRITE. * M680X: Sort changed_regs in increasing m680x_insn order. * M680X: Add M68HC11 support + Reduced from two to one INDEXED operand. * M680X: cstool, also write '(in mnemonic)' for second reg. operand. * M680X: Add BRN/LBRN to group JUMP and BRAREL. * M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access. * M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED. * M680X: Rename some instruction handlers. * M680X: Add M68HC05 support. * M680X: Dont print prefix '<' for direct addr. mode. * M680X: Add M68HC08 support + resorted tables + bug fixes. * M680X: Add Freescale HCS08 support. * M680X: Changed group names, avoid spaces. * M680X: Refactoring, rename addessing mode handlers. * M680X: indexed addr. mode, changed pre/post inc-/decrement representation. * M680X: Rename some M6809/HD6309 specific functions. * M680X: Add CPU12 (68HC12/HCS12) support. * M680X: Correctly display illegal instruction as FCB . * M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg. * M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing. * M680X: Better support for changing insn id within handler for addessing mode. * M680X: Remove warnings. * M680X: In set_changed_regs_read_write_counts use own access_mode. * M680X: Split cpu specific tables into separate *.inc files. * M680X: Remove warnings. * M680X: Removed address_mode. Addressing mode is available in operand.type * M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg. * M680X: Remove register TMP1. It is first visible in CPU12X. * M680X: Performance improvement + bug fixes. * M680X: Performance improvement, make cpu_tables const static. * M680X: Simplify operand decoding by using two handlers. * M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings. * M680X: Format with astyle. * M680X: Update documentation. * M680X: Corrected author for m680x specific files. * M680X: Make max. number of architectures single source.
49 lines
2.1 KiB
Plaintext
49 lines
2.1 KiB
Plaintext
Capstone source is organized as followings.
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. <- core engine + README + COMPILE.TXT etc
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├── arch <- code handling disasm engine for each arch
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│ ├── AArch64 <- ARM64 (aka ARMv8) engine
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│ ├── ARM <- ARM engine
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│ ├── M680X <- M680X engine
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│ ├── M68K <- M68K engine
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│ ├── Mips <- Mips engine
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│ ├── PowerPC <- PowerPC engine
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│ ├── Sparc <- Sparc engine
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│ ├── SystemZ <- SystemZ engine
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│ ├── X86 <- X86 engine
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│ └── XCore <- XCore engine
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├── bindings <- all bindings are under this dir
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│ ├── java <- Java bindings + test code
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│ ├── ocaml <- Ocaml bindings + test code
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│ └── python <- Python bindings + test code
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├── contrib <- Code contributed by community to help Capstone integration
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├── cstool <- Cstool
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├── docs <- Documentation
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├── include <- API headers in C language (*.h)
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├── msvc <- Microsoft Visual Studio support (for Windows compile)
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├── packages <- Packages for Linux/OSX/BSD.
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├── windows <- Windows support (for Windows kernel driver compile)
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├── suite <- Development test tools - for Capstone developers only
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├── tests <- Test code (in C language)
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└── xcode <- Xcode support (for MacOSX compile)
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Follow instructions in COMPILE.TXT for how to compile and run test code.
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Note: if you find some strange bugs, it is recommended to firstly clean
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the code and try to recompile/reinstall again. This can be done with:
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$ ./make.sh
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$ sudo ./make.sh install
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Then test Capstone with cstool, for example:
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$ cstool x32 "90 91"
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At the same time, for Java/Ocaml/Python bindings, be sure to always use
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the bindings coming with the core to avoid potential incompatibility issue
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with older versions.
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See bindings/<language>/README for detail instructions on how to compile &
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install the bindings.
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