mirror of
https://github.com/capstone-engine/capstone.git
synced 2025-02-13 02:33:34 +00:00
11251 lines
384 KiB
C
11251 lines
384 KiB
C
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|* *|
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|* Assembly Writer Source Fragment *|
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|* *|
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|* Automatically generated file, do not edit! *|
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|* *|
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\*===----------------------------------------------------------------------===*/
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/// printInstruction - This method is automatically generated by tablegen
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/// from the instruction set description.
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static void printInstruction(MCInst *MI, SStream *O)
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{
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#ifndef CAPSTONE_DIET
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static const char AsmStrs[] = {
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/* 0 */ '#', 'E', 'H', '_', 'S', 'j', 'L', 'j', '_', 'S', 'e', 't', 'u', 'p', 9, 0,
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/* 16 */ 'b', 'd', 'z', 'l', 'a', '+', 32, 0,
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/* 24 */ 'b', 'd', 'n', 'z', 'l', 'a', '+', 32, 0,
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/* 33 */ 'b', 'd', 'z', 'a', '+', 32, 0,
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/* 40 */ 'b', 'd', 'n', 'z', 'a', '+', 32, 0,
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/* 48 */ 'b', 'd', 'z', 'l', '+', 32, 0,
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/* 55 */ 'b', 'd', 'n', 'z', 'l', '+', 32, 0,
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/* 63 */ 'b', 'd', 'z', '+', 32, 0,
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/* 69 */ 'b', 'd', 'n', 'z', '+', 32, 0,
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/* 76 */ 'b', 'c', 'l', 32, '2', '0', ',', 32, '3', '1', ',', 32, 0,
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/* 89 */ 'b', 'c', 't', 'r', 'l', 10, 9, 'l', 'd', 32, '2', ',', 32, 0,
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/* 103 */ 'b', 'c', 32, '1', '2', ',', 32, 0,
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/* 111 */ 'b', 'c', 'l', 32, '1', '2', ',', 32, 0,
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/* 120 */ 'b', 'c', 'l', 'r', 'l', 32, '1', '2', ',', 32, 0,
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/* 131 */ 'b', 'c', 'c', 't', 'r', 'l', 32, '1', '2', ',', 32, 0,
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/* 143 */ 'b', 'c', 'l', 'r', 32, '1', '2', ',', 32, 0,
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/* 153 */ 'b', 'c', 'c', 't', 'r', 32, '1', '2', ',', 32, 0,
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/* 164 */ 'b', 'c', 32, '4', ',', 32, 0,
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/* 171 */ 'b', 'c', 'l', 32, '4', ',', 32, 0,
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/* 179 */ 'b', 'c', 'l', 'r', 'l', 32, '4', ',', 32, 0,
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/* 189 */ 'b', 'c', 'c', 't', 'r', 'l', 32, '4', ',', 32, 0,
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/* 200 */ 'b', 'c', 'l', 'r', 32, '4', ',', 32, 0,
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/* 209 */ 'b', 'c', 'c', 't', 'r', 32, '4', ',', 32, 0,
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/* 219 */ 'm', 't', 's', 'p', 'r', 32, '2', '5', '6', ',', 32, 0,
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/* 231 */ 'b', 'd', 'z', 'l', 'a', '-', 32, 0,
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/* 239 */ 'b', 'd', 'n', 'z', 'l', 'a', '-', 32, 0,
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/* 248 */ 'b', 'd', 'z', 'a', '-', 32, 0,
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/* 255 */ 'b', 'd', 'n', 'z', 'a', '-', 32, 0,
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/* 263 */ 'b', 'd', 'z', 'l', '-', 32, 0,
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/* 270 */ 'b', 'd', 'n', 'z', 'l', '-', 32, 0,
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/* 278 */ 'b', 'd', 'z', '-', 32, 0,
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/* 284 */ 'b', 'd', 'n', 'z', '-', 32, 0,
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/* 291 */ 'v', 'c', 'm', 'p', 'n', 'e', 'b', '.', 32, 0,
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/* 301 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'b', '.', 32, 0,
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/* 312 */ 'e', 'x', 't', 's', 'b', '.', 32, 0,
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/* 320 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'b', '.', 32, 0,
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/* 331 */ 'f', 's', 'u', 'b', '.', 32, 0,
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/* 338 */ 'f', 'm', 's', 'u', 'b', '.', 32, 0,
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/* 346 */ 'f', 'n', 'm', 's', 'u', 'b', '.', 32, 0,
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/* 355 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'b', '.', 32, 0,
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/* 366 */ 'v', 'c', 'm', 'p', 'n', 'e', 'z', 'b', '.', 32, 0,
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/* 377 */ 'a', 'd', 'd', 'c', '.', 32, 0,
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/* 384 */ 'a', 'n', 'd', 'c', '.', 32, 0,
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/* 391 */ 't', 'a', 'b', 'o', 'r', 't', 'd', 'c', '.', 32, 0,
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/* 402 */ 's', 'u', 'b', 'f', 'c', '.', 32, 0,
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/* 410 */ 's', 'u', 'b', 'i', 'c', '.', 32, 0,
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/* 418 */ 'a', 'd', 'd', 'i', 'c', '.', 32, 0,
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/* 426 */ 'r', 'l', 'd', 'i', 'c', '.', 32, 0,
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/* 434 */ 'b', 'c', 'd', 't', 'r', 'u', 'n', 'c', '.', 32, 0,
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/* 445 */ 'b', 'c', 'd', 'u', 't', 'r', 'u', 'n', 'c', '.', 32, 0,
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/* 457 */ 'o', 'r', 'c', '.', 32, 0,
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/* 463 */ 't', 'a', 'b', 'o', 'r', 't', 'w', 'c', '.', 32, 0,
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/* 474 */ 's', 'r', 'a', 'd', '.', 32, 0,
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/* 481 */ 'f', 'a', 'd', 'd', '.', 32, 0,
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/* 488 */ 'f', 'm', 'a', 'd', 'd', '.', 32, 0,
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/* 496 */ 'f', 'n', 'm', 'a', 'd', 'd', '.', 32, 0,
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/* 505 */ 'm', 'u', 'l', 'h', 'd', '.', 32, 0,
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/* 513 */ 'f', 'c', 'f', 'i', 'd', '.', 32, 0,
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/* 521 */ 'f', 'c', 't', 'i', 'd', '.', 32, 0,
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/* 529 */ 'm', 'u', 'l', 'l', 'd', '.', 32, 0,
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/* 537 */ 's', 'l', 'd', '.', 32, 0,
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/* 543 */ 'n', 'a', 'n', 'd', '.', 32, 0,
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/* 550 */ 't', 'e', 'n', 'd', '.', 32, 0,
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/* 557 */ 's', 'r', 'd', '.', 32, 0,
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/* 563 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'd', '.', 32, 0,
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/* 574 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'd', '.', 32, 0,
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/* 585 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'd', '.', 32, 0,
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/* 596 */ 'd', 'i', 'v', 'd', '.', 32, 0,
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/* 603 */ 'c', 'n', 't', 'l', 'z', 'd', '.', 32, 0,
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/* 612 */ 'c', 'n', 't', 't', 'z', 'd', '.', 32, 0,
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/* 621 */ 'a', 'd', 'd', 'e', '.', 32, 0,
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/* 628 */ 'd', 'i', 'v', 'd', 'e', '.', 32, 0,
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/* 636 */ 's', 'u', 'b', 'f', 'e', '.', 32, 0,
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/* 644 */ 'a', 'd', 'd', 'm', 'e', '.', 32, 0,
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/* 652 */ 's', 'u', 'b', 'f', 'm', 'e', '.', 32, 0,
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/* 661 */ 'f', 'r', 'e', '.', 32, 0,
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/* 667 */ 'f', 'r', 's', 'q', 'r', 't', 'e', '.', 32, 0,
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/* 677 */ 'p', 'a', 's', 't', 'e', '.', 32, 0,
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/* 685 */ 'd', 'i', 'v', 'w', 'e', '.', 32, 0,
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/* 693 */ 'a', 'd', 'd', 'z', 'e', '.', 32, 0,
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/* 701 */ 's', 'u', 'b', 'f', 'z', 'e', '.', 32, 0,
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/* 710 */ 's', 'u', 'b', 'f', '.', 32, 0,
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/* 717 */ 'm', 't', 'f', 's', 'f', '.', 32, 0,
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/* 725 */ 'f', 'n', 'e', 'g', '.', 32, 0,
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/* 732 */ 'v', 'c', 'm', 'p', 'n', 'e', 'h', '.', 32, 0,
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/* 742 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'h', '.', 32, 0,
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/* 753 */ 'e', 'x', 't', 's', 'h', '.', 32, 0,
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/* 761 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'h', '.', 32, 0,
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/* 772 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'h', '.', 32, 0,
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/* 783 */ 'v', 'c', 'm', 'p', 'n', 'e', 'z', 'h', '.', 32, 0,
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/* 794 */ 't', 'a', 'b', 'o', 'r', 't', 'd', 'c', 'i', '.', 32, 0,
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/* 806 */ 't', 'a', 'b', 'o', 'r', 't', 'w', 'c', 'i', '.', 32, 0,
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/* 818 */ 's', 'r', 'a', 'd', 'i', '.', 32, 0,
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/* 826 */ 'c', 'l', 'r', 'l', 's', 'l', 'd', 'i', '.', 32, 0,
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/* 837 */ 'e', 'x', 't', 'l', 'd', 'i', '.', 32, 0,
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/* 846 */ 'a', 'n', 'd', 'i', '.', 32, 0,
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/* 853 */ 'c', 'l', 'r', 'r', 'd', 'i', '.', 32, 0,
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/* 862 */ 'i', 'n', 's', 'r', 'd', 'i', '.', 32, 0,
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/* 871 */ 'r', 'o', 't', 'r', 'd', 'i', '.', 32, 0,
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/* 880 */ 'e', 'x', 't', 'r', 'd', 'i', '.', 32, 0,
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/* 889 */ 'm', 't', 'f', 's', 'f', 'i', '.', 32, 0,
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/* 898 */ 'e', 'x', 't', 's', 'w', 's', 'l', 'i', '.', 32, 0,
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/* 909 */ 'r', 'l', 'd', 'i', 'm', 'i', '.', 32, 0,
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/* 918 */ 'r', 'l', 'w', 'i', 'm', 'i', '.', 32, 0,
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/* 927 */ 's', 'r', 'a', 'w', 'i', '.', 32, 0,
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/* 935 */ 'c', 'l', 'r', 'l', 's', 'l', 'w', 'i', '.', 32, 0,
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/* 946 */ 'i', 'n', 's', 'l', 'w', 'i', '.', 32, 0,
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/* 955 */ 'e', 'x', 't', 'l', 'w', 'i', '.', 32, 0,
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/* 964 */ 'c', 'l', 'r', 'r', 'w', 'i', '.', 32, 0,
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/* 973 */ 'i', 'n', 's', 'r', 'w', 'i', '.', 32, 0,
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/* 982 */ 'r', 'o', 't', 'r', 'w', 'i', '.', 32, 0,
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/* 991 */ 'e', 'x', 't', 'r', 'w', 'i', '.', 32, 0,
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/* 1000 */ 'r', 'l', 'd', 'c', 'l', '.', 32, 0,
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/* 1008 */ 'r', 'l', 'd', 'i', 'c', 'l', '.', 32, 0,
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/* 1017 */ 'f', 's', 'e', 'l', '.', 32, 0,
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/* 1024 */ 'f', 'm', 'u', 'l', '.', 32, 0,
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/* 1031 */ 't', 'r', 'e', 'c', 'l', 'a', 'i', 'm', '.', 32, 0,
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/* 1042 */ 'f', 'r', 'i', 'm', '.', 32, 0,
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/* 1049 */ 'r', 'l', 'w', 'i', 'n', 'm', '.', 32, 0,
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/* 1058 */ 'r', 'l', 'w', 'n', 'm', '.', 32, 0,
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/* 1066 */ 'b', 'c', 'd', 'c', 'f', 'n', '.', 32, 0,
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/* 1075 */ 'b', 'c', 'd', 'c', 'p', 's', 'g', 'n', '.', 32, 0,
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/* 1086 */ 'f', 'c', 'p', 's', 'g', 'n', '.', 32, 0,
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/* 1095 */ 'b', 'c', 'd', 's', 'e', 't', 's', 'g', 'n', '.', 32, 0,
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/* 1107 */ 't', 'b', 'e', 'g', 'i', 'n', '.', 32, 0,
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/* 1116 */ 'f', 'r', 'i', 'n', '.', 32, 0,
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/* 1123 */ 'b', 'c', 'd', 'c', 't', 'n', '.', 32, 0,
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/* 1132 */ 'x', 'v', 'c', 'm', 'p', 'g', 'e', 'd', 'p', '.', 32, 0,
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/* 1144 */ 'x', 'v', 'c', 'm', 'p', 'e', 'q', 'd', 'p', '.', 32, 0,
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/* 1156 */ 'x', 'v', 'c', 'm', 'p', 'g', 't', 'd', 'p', '.', 32, 0,
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/* 1168 */ 'v', 'c', 'm', 'p', 'b', 'f', 'p', '.', 32, 0,
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/* 1178 */ 'v', 'c', 'm', 'p', 'g', 'e', 'f', 'p', '.', 32, 0,
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/* 1189 */ 'v', 'c', 'm', 'p', 'e', 'q', 'f', 'p', '.', 32, 0,
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/* 1200 */ 'v', 'c', 'm', 'p', 'g', 't', 'f', 'p', '.', 32, 0,
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/* 1211 */ 'f', 'r', 'i', 'p', '.', 32, 0,
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/* 1218 */ 'x', 'v', 'c', 'm', 'p', 'g', 'e', 's', 'p', '.', 32, 0,
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/* 1230 */ 'x', 'v', 'c', 'm', 'p', 'e', 'q', 's', 'p', '.', 32, 0,
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/* 1242 */ 'f', 'r', 's', 'p', '.', 32, 0,
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/* 1249 */ 'x', 'v', 'c', 'm', 'p', 'g', 't', 's', 'p', '.', 32, 0,
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/* 1261 */ 'i', 'c', 'b', 'l', 'q', '.', 32, 0,
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/* 1269 */ 'b', 'c', 'd', 'c', 'f', 's', 'q', '.', 32, 0,
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/* 1279 */ 'b', 'c', 'd', 'c', 't', 's', 'q', '.', 32, 0,
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/* 1289 */ 'r', 'l', 'd', 'c', 'r', '.', 32, 0,
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/* 1297 */ 'r', 'l', 'd', 'i', 'c', 'r', '.', 32, 0,
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/* 1306 */ 'f', 'm', 'r', '.', 32, 0,
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/* 1312 */ 'n', 'o', 'r', '.', 32, 0,
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/* 1318 */ 'x', 'o', 'r', '.', 32, 0,
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/* 1324 */ 'b', 'c', 'd', 's', 'r', '.', 32, 0,
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/* 1332 */ 't', 's', 'r', '.', 32, 0,
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/* 1338 */ 'f', 'a', 'b', 's', '.', 32, 0,
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/* 1345 */ 'f', 'n', 'a', 'b', 's', '.', 32, 0,
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/* 1353 */ 'f', 's', 'u', 'b', 's', '.', 32, 0,
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/* 1361 */ 'f', 'm', 's', 'u', 'b', 's', '.', 32, 0,
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/* 1370 */ 'f', 'n', 'm', 's', 'u', 'b', 's', '.', 32, 0,
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/* 1380 */ 'b', 'c', 'd', 's', '.', 32, 0,
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/* 1387 */ 'f', 'a', 'd', 'd', 's', '.', 32, 0,
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/* 1395 */ 'f', 'm', 'a', 'd', 'd', 's', '.', 32, 0,
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/* 1404 */ 'f', 'n', 'm', 'a', 'd', 'd', 's', '.', 32, 0,
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/* 1414 */ 'f', 'c', 'f', 'i', 'd', 's', '.', 32, 0,
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/* 1423 */ 'f', 'r', 'e', 's', '.', 32, 0,
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/* 1430 */ 'f', 'r', 's', 'q', 'r', 't', 'e', 's', '.', 32, 0,
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/* 1441 */ 'm', 'f', 'f', 's', '.', 32, 0,
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|
/* 1448 */ 'a', 'n', 'd', 'i', 's', '.', 32, 0,
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|
/* 1456 */ 'f', 'm', 'u', 'l', 's', '.', 32, 0,
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|
/* 1464 */ 'f', 's', 'q', 'r', 't', 's', '.', 32, 0,
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|
/* 1473 */ 'b', 'c', 'd', 'u', 's', '.', 32, 0,
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|
/* 1481 */ 'f', 'c', 'f', 'i', 'd', 'u', 's', '.', 32, 0,
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|
/* 1491 */ 'f', 'd', 'i', 'v', 's', '.', 32, 0,
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|
/* 1499 */ 't', 'a', 'b', 'o', 'r', 't', '.', 32, 0,
|
|
/* 1508 */ 'f', 's', 'q', 'r', 't', '.', 32, 0,
|
|
/* 1516 */ 'm', 'u', 'l', 'h', 'd', 'u', '.', 32, 0,
|
|
/* 1525 */ 'f', 'c', 'f', 'i', 'd', 'u', '.', 32, 0,
|
|
/* 1534 */ 'f', 'c', 't', 'i', 'd', 'u', '.', 32, 0,
|
|
/* 1543 */ 'd', 'i', 'v', 'd', 'u', '.', 32, 0,
|
|
/* 1551 */ 'd', 'i', 'v', 'd', 'e', 'u', '.', 32, 0,
|
|
/* 1560 */ 'd', 'i', 'v', 'w', 'e', 'u', '.', 32, 0,
|
|
/* 1569 */ 'm', 'u', 'l', 'h', 'w', 'u', '.', 32, 0,
|
|
/* 1578 */ 'f', 'c', 't', 'i', 'w', 'u', '.', 32, 0,
|
|
/* 1587 */ 'd', 'i', 'v', 'w', 'u', '.', 32, 0,
|
|
/* 1595 */ 'f', 'd', 'i', 'v', '.', 32, 0,
|
|
/* 1602 */ 'e', 'q', 'v', '.', 32, 0,
|
|
/* 1608 */ 's', 'r', 'a', 'w', '.', 32, 0,
|
|
/* 1615 */ 'v', 'c', 'm', 'p', 'n', 'e', 'w', '.', 32, 0,
|
|
/* 1625 */ 'm', 'u', 'l', 'h', 'w', '.', 32, 0,
|
|
/* 1633 */ 'f', 'c', 't', 'i', 'w', '.', 32, 0,
|
|
/* 1641 */ 'm', 'u', 'l', 'l', 'w', '.', 32, 0,
|
|
/* 1649 */ 's', 'l', 'w', '.', 32, 0,
|
|
/* 1655 */ 's', 'r', 'w', '.', 32, 0,
|
|
/* 1661 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'w', '.', 32, 0,
|
|
/* 1672 */ 'e', 'x', 't', 's', 'w', '.', 32, 0,
|
|
/* 1680 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'w', '.', 32, 0,
|
|
/* 1691 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'w', '.', 32, 0,
|
|
/* 1702 */ 'd', 'i', 'v', 'w', '.', 32, 0,
|
|
/* 1709 */ 'v', 'c', 'm', 'p', 'n', 'e', 'z', 'w', '.', 32, 0,
|
|
/* 1720 */ 'c', 'n', 't', 'l', 'z', 'w', '.', 32, 0,
|
|
/* 1729 */ 'c', 'n', 't', 't', 'z', 'w', '.', 32, 0,
|
|
/* 1738 */ 's', 't', 'b', 'c', 'x', '.', 32, 0,
|
|
/* 1746 */ 's', 't', 'd', 'c', 'x', '.', 32, 0,
|
|
/* 1754 */ 's', 't', 'h', 'c', 'x', '.', 32, 0,
|
|
/* 1762 */ 's', 't', 'w', 'c', 'x', '.', 32, 0,
|
|
/* 1770 */ 't', 'l', 'b', 's', 'x', '.', 32, 0,
|
|
/* 1778 */ 'f', 'c', 't', 'i', 'd', 'z', '.', 32, 0,
|
|
/* 1787 */ 'b', 'c', 'd', 'c', 'f', 'z', '.', 32, 0,
|
|
/* 1796 */ 'f', 'r', 'i', 'z', '.', 32, 0,
|
|
/* 1803 */ 'b', 'c', 'd', 'c', 't', 'z', '.', 32, 0,
|
|
/* 1812 */ 'f', 'c', 't', 'i', 'd', 'u', 'z', '.', 32, 0,
|
|
/* 1822 */ 'f', 'c', 't', 'i', 'w', 'u', 'z', '.', 32, 0,
|
|
/* 1832 */ 'f', 'c', 't', 'i', 'w', 'z', '.', 32, 0,
|
|
/* 1841 */ 'm', 't', 'f', 's', 'b', '0', 32, 0,
|
|
/* 1849 */ 'm', 't', 'f', 's', 'b', '1', 32, 0,
|
|
/* 1857 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '3', '2', 32, 0,
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/* 1879 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '1', '6', 32, 0,
|
|
/* 1901 */ '#', 'T', 'C', '_', 'R', 'E', 'T', 'U', 'R', 'N', 'a', '8', 32, 0,
|
|
/* 1915 */ '#', 'T', 'C', '_', 'R', 'E', 'T', 'U', 'R', 'N', 'd', '8', 32, 0,
|
|
/* 1929 */ '#', 'T', 'C', '_', 'R', 'E', 'T', 'U', 'R', 'N', 'r', '8', 32, 0,
|
|
/* 1943 */ 'U', 'P', 'D', 'A', 'T', 'E', '_', 'V', 'R', 'S', 'A', 'V', 'E', 32, 0,
|
|
/* 1958 */ '#', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0,
|
|
/* 1977 */ '#', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0,
|
|
/* 1994 */ '#', 'T', 'C', '_', 'R', 'E', 'T', 'U', 'R', 'N', 'a', 32, 0,
|
|
/* 2007 */ 'e', 'v', 'm', 'h', 'e', 'g', 's', 'm', 'f', 'a', 'a', 32, 0,
|
|
/* 2020 */ 'e', 'v', 'm', 'h', 'o', 'g', 's', 'm', 'f', 'a', 'a', 32, 0,
|
|
/* 2033 */ 'e', 'v', 'm', 'w', 's', 'm', 'f', 'a', 'a', 32, 0,
|
|
/* 2044 */ 'e', 'v', 'm', 'w', 's', 's', 'f', 'a', 'a', 32, 0,
|
|
/* 2055 */ 'e', 'v', 'm', 'h', 'e', 'g', 's', 'm', 'i', 'a', 'a', 32, 0,
|
|
/* 2068 */ 'e', 'v', 'm', 'h', 'o', 'g', 's', 'm', 'i', 'a', 'a', 32, 0,
|
|
/* 2081 */ 'e', 'v', 'm', 'w', 's', 'm', 'i', 'a', 'a', 32, 0,
|
|
/* 2092 */ 'e', 'v', 'm', 'h', 'e', 'g', 'u', 'm', 'i', 'a', 'a', 32, 0,
|
|
/* 2105 */ 'e', 'v', 'm', 'h', 'o', 'g', 'u', 'm', 'i', 'a', 'a', 32, 0,
|
|
/* 2118 */ 'e', 'v', 'm', 'w', 'u', 'm', 'i', 'a', 'a', 32, 0,
|
|
/* 2129 */ 'd', 'c', 'b', 'a', 32, 0,
|
|
/* 2135 */ 'b', 'c', 'a', 32, 0,
|
|
/* 2140 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'f', 'a', 32, 0,
|
|
/* 2151 */ 'e', 'v', 'm', 'w', 'h', 's', 'm', 'f', 'a', 32, 0,
|
|
/* 2162 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'f', 'a', 32, 0,
|
|
/* 2173 */ 'e', 'v', 'm', 'w', 's', 'm', 'f', 'a', 32, 0,
|
|
/* 2183 */ 'e', 'v', 'm', 'h', 'e', 's', 's', 'f', 'a', 32, 0,
|
|
/* 2194 */ 'e', 'v', 'm', 'w', 'h', 's', 's', 'f', 'a', 32, 0,
|
|
/* 2205 */ 'e', 'v', 'm', 'h', 'o', 's', 's', 'f', 'a', 32, 0,
|
|
/* 2216 */ 'e', 'v', 'm', 'w', 's', 's', 'f', 'a', 32, 0,
|
|
/* 2226 */ 'l', 'h', 'a', 32, 0,
|
|
/* 2231 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'i', 'a', 32, 0,
|
|
/* 2242 */ 'e', 'v', 'm', 'w', 'h', 's', 'm', 'i', 'a', 32, 0,
|
|
/* 2253 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'i', 'a', 32, 0,
|
|
/* 2264 */ 'e', 'v', 'm', 'w', 's', 'm', 'i', 'a', 32, 0,
|
|
/* 2274 */ 'e', 'v', 'm', 'h', 'e', 'u', 'm', 'i', 'a', 32, 0,
|
|
/* 2285 */ 'e', 'v', 'm', 'w', 'h', 'u', 'm', 'i', 'a', 32, 0,
|
|
/* 2296 */ 'e', 'v', 'm', 'w', 'l', 'u', 'm', 'i', 'a', 32, 0,
|
|
/* 2307 */ 'e', 'v', 'm', 'h', 'o', 'u', 'm', 'i', 'a', 32, 0,
|
|
/* 2318 */ 'e', 'v', 'm', 'w', 'u', 'm', 'i', 'a', 32, 0,
|
|
/* 2328 */ 'q', 'v', 's', 't', 'f', 'c', 'd', 'x', 'i', 'a', 32, 0,
|
|
/* 2340 */ 'q', 'v', 's', 't', 'f', 'd', 'x', 'i', 'a', 32, 0,
|
|
/* 2351 */ 'q', 'v', 's', 't', 'f', 'c', 's', 'x', 'i', 'a', 32, 0,
|
|
/* 2363 */ 'q', 'v', 's', 't', 'f', 's', 'x', 'i', 'a', 32, 0,
|
|
/* 2374 */ 'q', 'v', 's', 't', 'f', 'c', 'd', 'u', 'x', 'i', 'a', 32, 0,
|
|
/* 2387 */ 'q', 'v', 's', 't', 'f', 'd', 'u', 'x', 'i', 'a', 32, 0,
|
|
/* 2399 */ 'q', 'v', 's', 't', 'f', 'c', 's', 'u', 'x', 'i', 'a', 32, 0,
|
|
/* 2412 */ 'q', 'v', 's', 't', 'f', 's', 'u', 'x', 'i', 'a', 32, 0,
|
|
/* 2424 */ 'b', 'l', 'a', 32, 0,
|
|
/* 2429 */ 'b', 'c', 'l', 'a', 32, 0,
|
|
/* 2435 */ 'b', 'd', 'z', 'l', 'a', 32, 0,
|
|
/* 2442 */ 'b', 'd', 'n', 'z', 'l', 'a', 32, 0,
|
|
/* 2450 */ 'e', 'v', 'm', 'r', 'a', 32, 0,
|
|
/* 2457 */ 'l', 'w', 'a', 32, 0,
|
|
/* 2462 */ 'm', 't', 'v', 's', 'r', 'w', 'a', 32, 0,
|
|
/* 2471 */ 'q', 'v', 'l', 'f', 'i', 'w', 'a', 'x', 'a', 32, 0,
|
|
/* 2482 */ 'q', 'v', 'l', 'f', 'c', 'd', 'x', 'a', 32, 0,
|
|
/* 2492 */ 'q', 'v', 's', 't', 'f', 'c', 'd', 'x', 'a', 32, 0,
|
|
/* 2503 */ 'q', 'v', 'l', 'f', 'd', 'x', 'a', 32, 0,
|
|
/* 2512 */ 'q', 'v', 's', 't', 'f', 'd', 'x', 'a', 32, 0,
|
|
/* 2522 */ 'q', 'v', 'l', 'f', 'c', 's', 'x', 'a', 32, 0,
|
|
/* 2532 */ 'q', 'v', 's', 't', 'f', 'c', 's', 'x', 'a', 32, 0,
|
|
/* 2543 */ 'q', 'v', 'l', 'f', 's', 'x', 'a', 32, 0,
|
|
/* 2552 */ 'q', 'v', 's', 't', 'f', 's', 'x', 'a', 32, 0,
|
|
/* 2562 */ 'q', 'v', 'l', 'f', 'c', 'd', 'u', 'x', 'a', 32, 0,
|
|
/* 2573 */ 'q', 'v', 's', 't', 'f', 'c', 'd', 'u', 'x', 'a', 32, 0,
|
|
/* 2585 */ 'q', 'v', 'l', 'f', 'd', 'u', 'x', 'a', 32, 0,
|
|
/* 2595 */ 'q', 'v', 's', 't', 'f', 'd', 'u', 'x', 'a', 32, 0,
|
|
/* 2606 */ 'q', 'v', 'l', 'f', 'c', 's', 'u', 'x', 'a', 32, 0,
|
|
/* 2617 */ 'q', 'v', 's', 't', 'f', 'c', 's', 'u', 'x', 'a', 32, 0,
|
|
/* 2629 */ 'q', 'v', 'l', 'f', 's', 'u', 'x', 'a', 32, 0,
|
|
/* 2639 */ 'q', 'v', 's', 't', 'f', 's', 'u', 'x', 'a', 32, 0,
|
|
/* 2650 */ 'q', 'v', 's', 't', 'f', 'i', 'w', 'x', 'a', 32, 0,
|
|
/* 2661 */ 'q', 'v', 'l', 'f', 'i', 'w', 'z', 'x', 'a', 32, 0,
|
|
/* 2672 */ 'b', 'd', 'z', 'a', 32, 0,
|
|
/* 2678 */ 'b', 'd', 'n', 'z', 'a', 32, 0,
|
|
/* 2685 */ 'v', 's', 'r', 'a', 'b', 32, 0,
|
|
/* 2692 */ 'r', 'f', 'e', 'b', 'b', 32, 0,
|
|
/* 2699 */ 'v', 'c', 'l', 'z', 'l', 's', 'b', 'b', 32, 0,
|
|
/* 2709 */ 'v', 'c', 't', 'z', 'l', 's', 'b', 'b', 32, 0,
|
|
/* 2719 */ 'v', 'c', 'm', 'p', 'n', 'e', 'b', 32, 0,
|
|
/* 2728 */ 'v', 'm', 'r', 'g', 'h', 'b', 32, 0,
|
|
/* 2736 */ 'x', 'x', 's', 'p', 'l', 't', 'i', 'b', 32, 0,
|
|
/* 2746 */ 'v', 'm', 'r', 'g', 'l', 'b', 32, 0,
|
|
/* 2754 */ 'v', 'r', 'l', 'b', 32, 0,
|
|
/* 2760 */ 'v', 's', 'l', 'b', 32, 0,
|
|
/* 2766 */ 'v', 'p', 'm', 's', 'u', 'm', 'b', 32, 0,
|
|
/* 2775 */ 'c', 'm', 'p', 'b', 32, 0,
|
|
/* 2781 */ 'c', 'm', 'p', 'e', 'q', 'b', 32, 0,
|
|
/* 2789 */ 'c', 'm', 'p', 'r', 'b', 32, 0,
|
|
/* 2796 */ 'v', 's', 'r', 'b', 32, 0,
|
|
/* 2802 */ 'v', 'm', 'u', 'l', 'e', 's', 'b', 32, 0,
|
|
/* 2811 */ 'v', 'a', 'v', 'g', 's', 'b', 32, 0,
|
|
/* 2819 */ 'v', 'u', 'p', 'k', 'h', 's', 'b', 32, 0,
|
|
/* 2828 */ 'v', 's', 'p', 'l', 't', 'i', 's', 'b', 32, 0,
|
|
/* 2838 */ 'v', 'u', 'p', 'k', 'l', 's', 'b', 32, 0,
|
|
/* 2847 */ 'v', 'm', 'i', 'n', 's', 'b', 32, 0,
|
|
/* 2855 */ 'v', 'm', 'u', 'l', 'o', 's', 'b', 32, 0,
|
|
/* 2864 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'b', 32, 0,
|
|
/* 2874 */ 'e', 'v', 'e', 'x', 't', 's', 'b', 32, 0,
|
|
/* 2883 */ 'v', 'm', 'a', 'x', 's', 'b', 32, 0,
|
|
/* 2891 */ 's', 'e', 't', 'b', 32, 0,
|
|
/* 2897 */ 'm', 'f', 't', 'b', 32, 0,
|
|
/* 2903 */ 'v', 's', 'p', 'l', 't', 'b', 32, 0,
|
|
/* 2911 */ 'v', 'p', 'o', 'p', 'c', 'n', 't', 'b', 32, 0,
|
|
/* 2921 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'b', 32, 0,
|
|
/* 2931 */ 's', 't', 'b', 32, 0,
|
|
/* 2936 */ 'v', 'a', 'b', 's', 'd', 'u', 'b', 32, 0,
|
|
/* 2945 */ 'v', 'm', 'u', 'l', 'e', 'u', 'b', 32, 0,
|
|
/* 2954 */ 'v', 'a', 'v', 'g', 'u', 'b', 32, 0,
|
|
/* 2962 */ 'v', 'm', 'i', 'n', 'u', 'b', 32, 0,
|
|
/* 2970 */ 'v', 'm', 'u', 'l', 'o', 'u', 'b', 32, 0,
|
|
/* 2979 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'b', 32, 0,
|
|
/* 2989 */ 'e', 'f', 'd', 's', 'u', 'b', 32, 0,
|
|
/* 2997 */ 'q', 'v', 'f', 's', 'u', 'b', 32, 0,
|
|
/* 3005 */ 'q', 'v', 'f', 'm', 's', 'u', 'b', 32, 0,
|
|
/* 3014 */ 'q', 'v', 'f', 'n', 'm', 's', 'u', 'b', 32, 0,
|
|
/* 3024 */ 'e', 'f', 's', 's', 'u', 'b', 32, 0,
|
|
/* 3032 */ 'e', 'v', 'f', 's', 's', 'u', 'b', 32, 0,
|
|
/* 3041 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'u', 'b', 32, 0,
|
|
/* 3053 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'b', 32, 0,
|
|
/* 3063 */ 'v', 'm', 'a', 'x', 'u', 'b', 32, 0,
|
|
/* 3071 */ 'v', 'c', 'm', 'p', 'n', 'e', 'z', 'b', 32, 0,
|
|
/* 3081 */ 'v', 'c', 'l', 'z', 'b', 32, 0,
|
|
/* 3088 */ 'v', 'c', 't', 'z', 'b', 32, 0,
|
|
/* 3095 */ 'b', 'c', 32, 0,
|
|
/* 3099 */ 'a', 'd', 'd', 'c', 32, 0,
|
|
/* 3105 */ 'x', 'x', 'l', 'a', 'n', 'd', 'c', 32, 0,
|
|
/* 3114 */ 'c', 'r', 'a', 'n', 'd', 'c', 32, 0,
|
|
/* 3122 */ 'e', 'v', 'a', 'n', 'd', 'c', 32, 0,
|
|
/* 3130 */ 's', 'u', 'b', 'f', 'c', 32, 0,
|
|
/* 3137 */ 's', 'u', 'b', 'i', 'c', 32, 0,
|
|
/* 3144 */ 'a', 'd', 'd', 'i', 'c', 32, 0,
|
|
/* 3151 */ 'r', 'l', 'd', 'i', 'c', 32, 0,
|
|
/* 3158 */ 's', 'u', 'b', 'f', 'i', 'c', 32, 0,
|
|
/* 3166 */ 'x', 's', 'r', 'd', 'p', 'i', 'c', 32, 0,
|
|
/* 3175 */ 'x', 'v', 'r', 'd', 'p', 'i', 'c', 32, 0,
|
|
/* 3184 */ 'x', 'v', 'r', 's', 'p', 'i', 'c', 32, 0,
|
|
/* 3193 */ 'i', 'c', 'b', 'l', 'c', 32, 0,
|
|
/* 3200 */ 'b', 'r', 'i', 'n', 'c', 32, 0,
|
|
/* 3207 */ 's', 'y', 'n', 'c', 32, 0,
|
|
/* 3213 */ 'x', 'x', 'l', 'o', 'r', 'c', 32, 0,
|
|
/* 3221 */ 'c', 'r', 'o', 'r', 'c', 32, 0,
|
|
/* 3228 */ 'e', 'v', 'o', 'r', 'c', 32, 0,
|
|
/* 3235 */ 's', 'c', 32, 0,
|
|
/* 3239 */ 'v', 'e', 'x', 't', 's', 'b', '2', 'd', 32, 0,
|
|
/* 3249 */ 'v', 'e', 'x', 't', 's', 'h', '2', 'd', 32, 0,
|
|
/* 3259 */ 'v', 'e', 'x', 't', 's', 'w', '2', 'd', 32, 0,
|
|
/* 3269 */ '#', 'T', 'C', '_', 'R', 'E', 'T', 'U', 'R', 'N', 'd', 32, 0,
|
|
/* 3282 */ 'v', 's', 'h', 'a', 's', 'i', 'g', 'm', 'a', 'd', 32, 0,
|
|
/* 3294 */ 'v', 's', 'r', 'a', 'd', 32, 0,
|
|
/* 3301 */ 'v', 'g', 'b', 'b', 'd', 32, 0,
|
|
/* 3308 */ 'v', 'p', 'r', 't', 'y', 'b', 'd', 32, 0,
|
|
/* 3317 */ 'e', 'f', 'd', 'a', 'd', 'd', 32, 0,
|
|
/* 3325 */ 'q', 'v', 'f', 'a', 'd', 'd', 32, 0,
|
|
/* 3333 */ 'q', 'v', 'f', 'm', 'a', 'd', 'd', 32, 0,
|
|
/* 3342 */ 'q', 'v', 'f', 'n', 'm', 'a', 'd', 'd', 32, 0,
|
|
/* 3352 */ 'q', 'v', 'f', 'x', 'x', 'c', 'p', 'n', 'm', 'a', 'd', 'd', 32, 0,
|
|
/* 3366 */ 'q', 'v', 'f', 'x', 'x', 'n', 'p', 'm', 'a', 'd', 'd', 32, 0,
|
|
/* 3379 */ 'q', 'v', 'f', 'x', 'm', 'a', 'd', 'd', 32, 0,
|
|
/* 3389 */ 'q', 'v', 'f', 'x', 'x', 'm', 'a', 'd', 'd', 32, 0,
|
|
/* 3400 */ 'e', 'f', 's', 'a', 'd', 'd', 32, 0,
|
|
/* 3408 */ 'e', 'v', 'f', 's', 'a', 'd', 'd', 32, 0,
|
|
/* 3417 */ 'e', 'v', 'l', 'd', 'd', 32, 0,
|
|
/* 3424 */ 'm', 't', 'v', 's', 'r', 'd', 'd', 32, 0,
|
|
/* 3433 */ 'e', 'v', 's', 't', 'd', 'd', 32, 0,
|
|
/* 3441 */ 'e', 'f', 's', 'c', 'f', 'd', 32, 0,
|
|
/* 3449 */ 'l', 'f', 'd', 32, 0,
|
|
/* 3454 */ 's', 't', 'f', 'd', 32, 0,
|
|
/* 3460 */ 'v', 'n', 'e', 'g', 'd', 32, 0,
|
|
/* 3467 */ 'm', 'a', 'd', 'd', 'h', 'd', 32, 0,
|
|
/* 3475 */ 'm', 'u', 'l', 'h', 'd', 32, 0,
|
|
/* 3482 */ 'q', 'v', 'f', 'c', 'f', 'i', 'd', 32, 0,
|
|
/* 3491 */ 'e', 'f', 'd', 'c', 'f', 's', 'i', 'd', 32, 0,
|
|
/* 3501 */ 'q', 'v', 'f', 'c', 't', 'i', 'd', 32, 0,
|
|
/* 3510 */ 'e', 'f', 'd', 'c', 'f', 'u', 'i', 'd', 32, 0,
|
|
/* 3520 */ 't', 'l', 'b', 'l', 'd', 32, 0,
|
|
/* 3527 */ 'm', 'a', 'd', 'd', 'l', 'd', 32, 0,
|
|
/* 3535 */ 'm', 'u', 'l', 'l', 'd', 32, 0,
|
|
/* 3542 */ 'c', 'm', 'p', 'l', 'd', 32, 0,
|
|
/* 3549 */ 'm', 'f', 'v', 's', 'r', 'l', 'd', 32, 0,
|
|
/* 3558 */ 'v', 'r', 'l', 'd', 32, 0,
|
|
/* 3564 */ 'v', 's', 'l', 'd', 32, 0,
|
|
/* 3570 */ 'v', 'b', 'p', 'e', 'r', 'm', 'd', 32, 0,
|
|
/* 3579 */ 'v', 'p', 'm', 's', 'u', 'm', 'd', 32, 0,
|
|
/* 3588 */ 'x', 'x', 'l', 'a', 'n', 'd', 32, 0,
|
|
/* 3596 */ 'x', 'x', 'l', 'n', 'a', 'n', 'd', 32, 0,
|
|
/* 3605 */ 'c', 'r', 'n', 'a', 'n', 'd', 32, 0,
|
|
/* 3613 */ 'e', 'v', 'n', 'a', 'n', 'd', 32, 0,
|
|
/* 3621 */ 'c', 'r', 'a', 'n', 'd', 32, 0,
|
|
/* 3628 */ 'e', 'v', 'a', 'n', 'd', 32, 0,
|
|
/* 3635 */ 'c', 'm', 'p', 'd', 32, 0,
|
|
/* 3641 */ 'x', 'x', 'b', 'r', 'd', 32, 0,
|
|
/* 3648 */ 'm', 't', 'm', 's', 'r', 'd', 32, 0,
|
|
/* 3656 */ 'm', 'f', 'v', 's', 'r', 'd', 32, 0,
|
|
/* 3664 */ 'm', 't', 'v', 's', 'r', 'd', 32, 0,
|
|
/* 3672 */ 'm', 'o', 'd', 's', 'd', 32, 0,
|
|
/* 3679 */ 'v', 'm', 'i', 'n', 's', 'd', 32, 0,
|
|
/* 3687 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'd', 32, 0,
|
|
/* 3697 */ 'v', 'm', 'a', 'x', 's', 'd', 32, 0,
|
|
/* 3705 */ 'l', 'x', 's', 'd', 32, 0,
|
|
/* 3711 */ 's', 't', 'x', 's', 'd', 32, 0,
|
|
/* 3718 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'd', 32, 0,
|
|
/* 3729 */ 'v', 'p', 'o', 'p', 'c', 'n', 't', 'd', 32, 0,
|
|
/* 3739 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'd', 32, 0,
|
|
/* 3749 */ 's', 't', 'd', 32, 0,
|
|
/* 3754 */ 'm', 'o', 'd', 'u', 'd', 32, 0,
|
|
/* 3761 */ 'v', 'm', 'i', 'n', 'u', 'd', 32, 0,
|
|
/* 3769 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'd', 32, 0,
|
|
/* 3779 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'd', 32, 0,
|
|
/* 3789 */ 'v', 'm', 'a', 'x', 'u', 'd', 32, 0,
|
|
/* 3797 */ 'd', 'i', 'v', 'd', 32, 0,
|
|
/* 3803 */ 'v', 'c', 'l', 'z', 'd', 32, 0,
|
|
/* 3810 */ 'c', 'n', 't', 'l', 'z', 'd', 32, 0,
|
|
/* 3818 */ 'v', 'c', 't', 'z', 'd', 32, 0,
|
|
/* 3825 */ 'c', 'n', 't', 't', 'z', 'd', 32, 0,
|
|
/* 3833 */ 'm', 'f', 'b', 'h', 'r', 'b', 'e', 32, 0,
|
|
/* 3842 */ 'm', 'f', 'f', 's', 'c', 'e', 32, 0,
|
|
/* 3850 */ 'a', 'd', 'd', 'e', 32, 0,
|
|
/* 3856 */ 'd', 'i', 'v', 'd', 'e', 32, 0,
|
|
/* 3863 */ 's', 'l', 'b', 'm', 'f', 'e', 'e', 32, 0,
|
|
/* 3872 */ 'w', 'r', 't', 'e', 'e', 32, 0,
|
|
/* 3879 */ 's', 'u', 'b', 'f', 'e', 32, 0,
|
|
/* 3886 */ 'e', 'v', 'l', 'w', 'h', 'e', 32, 0,
|
|
/* 3894 */ 'e', 'v', 's', 't', 'w', 'h', 'e', 32, 0,
|
|
/* 3903 */ 's', 'l', 'b', 'i', 'e', 32, 0,
|
|
/* 3910 */ 't', 'l', 'b', 'i', 'e', 32, 0,
|
|
/* 3917 */ 'a', 'd', 'd', 'm', 'e', 32, 0,
|
|
/* 3924 */ 's', 'u', 'b', 'f', 'm', 'e', 32, 0,
|
|
/* 3932 */ 't', 'l', 'b', 'r', 'e', 32, 0,
|
|
/* 3939 */ 'q', 'v', 'f', 'r', 'e', 32, 0,
|
|
/* 3946 */ 's', 'l', 'b', 'm', 't', 'e', 32, 0,
|
|
/* 3954 */ 'q', 'v', 'f', 'r', 's', 'q', 'r', 't', 'e', 32, 0,
|
|
/* 3965 */ 'p', 'a', 's', 't', 'e', 32, 0,
|
|
/* 3972 */ 't', 'l', 'b', 'w', 'e', 32, 0,
|
|
/* 3979 */ 'd', 'i', 'v', 'w', 'e', 32, 0,
|
|
/* 3986 */ 'e', 'v', 's', 't', 'w', 'w', 'e', 32, 0,
|
|
/* 3995 */ 'a', 'd', 'd', 'z', 'e', 32, 0,
|
|
/* 4002 */ 's', 'u', 'b', 'f', 'z', 'e', 32, 0,
|
|
/* 4010 */ 'd', 'c', 'b', 'f', 32, 0,
|
|
/* 4016 */ 's', 'u', 'b', 'f', 32, 0,
|
|
/* 4022 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'f', 32, 0,
|
|
/* 4032 */ 'e', 'v', 'm', 'w', 'h', 's', 'm', 'f', 32, 0,
|
|
/* 4042 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'f', 32, 0,
|
|
/* 4052 */ 'e', 'v', 'm', 'w', 's', 'm', 'f', 32, 0,
|
|
/* 4061 */ 'm', 'c', 'r', 'f', 32, 0,
|
|
/* 4067 */ 'm', 'f', 'o', 'c', 'r', 'f', 32, 0,
|
|
/* 4075 */ 'm', 't', 'o', 'c', 'r', 'f', 32, 0,
|
|
/* 4083 */ 'm', 't', 'c', 'r', 'f', 32, 0,
|
|
/* 4090 */ 'e', 'f', 'd', 'c', 'f', 's', 'f', 32, 0,
|
|
/* 4099 */ 'e', 'f', 's', 'c', 'f', 's', 'f', 32, 0,
|
|
/* 4108 */ 'e', 'v', 'f', 's', 'c', 'f', 's', 'f', 32, 0,
|
|
/* 4118 */ 'm', 't', 'f', 's', 'f', 32, 0,
|
|
/* 4125 */ 'e', 'v', 'm', 'h', 'e', 's', 's', 'f', 32, 0,
|
|
/* 4135 */ 'e', 'v', 'm', 'w', 'h', 's', 's', 'f', 32, 0,
|
|
/* 4145 */ 'e', 'v', 'm', 'h', 'o', 's', 's', 'f', 32, 0,
|
|
/* 4155 */ 'e', 'v', 'm', 'w', 's', 's', 'f', 32, 0,
|
|
/* 4164 */ 'e', 'f', 'd', 'c', 't', 's', 'f', 32, 0,
|
|
/* 4173 */ 'e', 'f', 's', 'c', 't', 's', 'f', 32, 0,
|
|
/* 4182 */ 'e', 'v', 'f', 's', 'c', 't', 's', 'f', 32, 0,
|
|
/* 4192 */ 'e', 'f', 'd', 'c', 'f', 'u', 'f', 32, 0,
|
|
/* 4201 */ 'e', 'f', 's', 'c', 'f', 'u', 'f', 32, 0,
|
|
/* 4210 */ 'e', 'v', 'f', 's', 'c', 'f', 'u', 'f', 32, 0,
|
|
/* 4220 */ 'e', 'f', 'd', 'c', 't', 'u', 'f', 32, 0,
|
|
/* 4229 */ 'e', 'f', 's', 'c', 't', 'u', 'f', 32, 0,
|
|
/* 4238 */ 's', 'l', 'b', 'i', 'e', 'g', 32, 0,
|
|
/* 4246 */ 'e', 'f', 'd', 'n', 'e', 'g', 32, 0,
|
|
/* 4254 */ 'q', 'v', 'f', 'n', 'e', 'g', 32, 0,
|
|
/* 4262 */ 'e', 'f', 's', 'n', 'e', 'g', 32, 0,
|
|
/* 4270 */ 'e', 'v', 'f', 's', 'n', 'e', 'g', 32, 0,
|
|
/* 4279 */ 'e', 'v', 'n', 'e', 'g', 32, 0,
|
|
/* 4286 */ 'v', 's', 'r', 'a', 'h', 32, 0,
|
|
/* 4293 */ 'e', 'v', 'l', 'd', 'h', 32, 0,
|
|
/* 4300 */ 'e', 'v', 's', 't', 'd', 'h', 32, 0,
|
|
/* 4308 */ 'v', 'c', 'm', 'p', 'n', 'e', 'h', 32, 0,
|
|
/* 4317 */ 'v', 'm', 'r', 'g', 'h', 'h', 32, 0,
|
|
/* 4325 */ 'v', 'm', 'r', 'g', 'l', 'h', 32, 0,
|
|
/* 4333 */ 'v', 'r', 'l', 'h', 32, 0,
|
|
/* 4339 */ 'v', 's', 'l', 'h', 32, 0,
|
|
/* 4345 */ 'v', 'p', 'm', 's', 'u', 'm', 'h', 32, 0,
|
|
/* 4354 */ 'x', 'x', 'b', 'r', 'h', 32, 0,
|
|
/* 4361 */ 'v', 's', 'r', 'h', 32, 0,
|
|
/* 4367 */ 'v', 'm', 'u', 'l', 'e', 's', 'h', 32, 0,
|
|
/* 4376 */ 'v', 'a', 'v', 'g', 's', 'h', 32, 0,
|
|
/* 4384 */ 'v', 'u', 'p', 'k', 'h', 's', 'h', 32, 0,
|
|
/* 4393 */ 'v', 's', 'p', 'l', 't', 'i', 's', 'h', 32, 0,
|
|
/* 4403 */ 'v', 'u', 'p', 'k', 'l', 's', 'h', 32, 0,
|
|
/* 4412 */ 'v', 'm', 'i', 'n', 's', 'h', 32, 0,
|
|
/* 4420 */ 'v', 'm', 'u', 'l', 'o', 's', 'h', 32, 0,
|
|
/* 4429 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'h', 32, 0,
|
|
/* 4439 */ 'e', 'v', 'e', 'x', 't', 's', 'h', 32, 0,
|
|
/* 4448 */ 'v', 'm', 'a', 'x', 's', 'h', 32, 0,
|
|
/* 4456 */ 'v', 's', 'p', 'l', 't', 'h', 32, 0,
|
|
/* 4464 */ 'v', 'p', 'o', 'p', 'c', 'n', 't', 'h', 32, 0,
|
|
/* 4474 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'h', 32, 0,
|
|
/* 4484 */ 's', 't', 'h', 32, 0,
|
|
/* 4489 */ 'v', 'a', 'b', 's', 'd', 'u', 'h', 32, 0,
|
|
/* 4498 */ 'v', 'm', 'u', 'l', 'e', 'u', 'h', 32, 0,
|
|
/* 4507 */ 'v', 'a', 'v', 'g', 'u', 'h', 32, 0,
|
|
/* 4515 */ 'v', 'm', 'i', 'n', 'u', 'h', 32, 0,
|
|
/* 4523 */ 'v', 'm', 'u', 'l', 'o', 'u', 'h', 32, 0,
|
|
/* 4532 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'h', 32, 0,
|
|
/* 4542 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'u', 'h', 32, 0,
|
|
/* 4554 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'h', 32, 0,
|
|
/* 4564 */ 'v', 'm', 'a', 'x', 'u', 'h', 32, 0,
|
|
/* 4572 */ 'v', 'c', 'm', 'p', 'n', 'e', 'z', 'h', 32, 0,
|
|
/* 4582 */ 'v', 'c', 'l', 'z', 'h', 32, 0,
|
|
/* 4589 */ 'v', 'c', 't', 'z', 'h', 32, 0,
|
|
/* 4596 */ 'd', 'c', 'b', 'i', 32, 0,
|
|
/* 4602 */ 'i', 'c', 'b', 'i', 32, 0,
|
|
/* 4608 */ 's', 'u', 'b', 'i', 32, 0,
|
|
/* 4614 */ 'd', 'c', 'c', 'c', 'i', 32, 0,
|
|
/* 4621 */ 'i', 'c', 'c', 'c', 'i', 32, 0,
|
|
/* 4628 */ 'q', 'v', 'g', 'p', 'c', 'i', 32, 0,
|
|
/* 4636 */ 's', 'r', 'a', 'd', 'i', 32, 0,
|
|
/* 4643 */ 'a', 'd', 'd', 'i', 32, 0,
|
|
/* 4649 */ 'c', 'm', 'p', 'l', 'd', 'i', 32, 0,
|
|
/* 4657 */ 'c', 'l', 'r', 'l', 's', 'l', 'd', 'i', 32, 0,
|
|
/* 4667 */ 'e', 'x', 't', 'l', 'd', 'i', 32, 0,
|
|
/* 4675 */ 'x', 'x', 'p', 'e', 'r', 'm', 'd', 'i', 32, 0,
|
|
/* 4685 */ 'c', 'm', 'p', 'd', 'i', 32, 0,
|
|
/* 4692 */ 'c', 'l', 'r', 'r', 'd', 'i', 32, 0,
|
|
/* 4700 */ 'i', 'n', 's', 'r', 'd', 'i', 32, 0,
|
|
/* 4708 */ 'r', 'o', 't', 'r', 'd', 'i', 32, 0,
|
|
/* 4716 */ 'e', 'x', 't', 'r', 'd', 'i', 32, 0,
|
|
/* 4724 */ 't', 'd', 'i', 32, 0,
|
|
/* 4729 */ 'w', 'r', 't', 'e', 'e', 'i', 32, 0,
|
|
/* 4737 */ 'm', 't', 'f', 's', 'f', 'i', 32, 0,
|
|
/* 4745 */ 'e', 'v', 's', 'p', 'l', 'a', 't', 'f', 'i', 32, 0,
|
|
/* 4756 */ 'e', 'v', 'm', 'e', 'r', 'g', 'e', 'h', 'i', 32, 0,
|
|
/* 4767 */ 'e', 'v', 'm', 'e', 'r', 'g', 'e', 'l', 'o', 'h', 'i', 32, 0,
|
|
/* 4780 */ 't', 'l', 'b', 'l', 'i', 32, 0,
|
|
/* 4787 */ 'm', 'u', 'l', 'l', 'i', 32, 0,
|
|
/* 4794 */ 'e', 'x', 't', 's', 'w', 's', 'l', 'i', 32, 0,
|
|
/* 4804 */ 'v', 'r', 'l', 'd', 'm', 'i', 32, 0,
|
|
/* 4812 */ 'r', 'l', 'd', 'i', 'm', 'i', 32, 0,
|
|
/* 4820 */ 'r', 'l', 'w', 'i', 'm', 'i', 32, 0,
|
|
/* 4828 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'i', 32, 0,
|
|
/* 4838 */ 'e', 'v', 'm', 'w', 'h', 's', 'm', 'i', 32, 0,
|
|
/* 4848 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'i', 32, 0,
|
|
/* 4858 */ 'e', 'v', 'm', 'w', 's', 'm', 'i', 32, 0,
|
|
/* 4867 */ 'e', 'v', 'm', 'h', 'e', 'u', 'm', 'i', 32, 0,
|
|
/* 4877 */ 'e', 'v', 'm', 'w', 'h', 'u', 'm', 'i', 32, 0,
|
|
/* 4887 */ 'e', 'v', 'm', 'w', 'l', 'u', 'm', 'i', 32, 0,
|
|
/* 4897 */ 'e', 'v', 'm', 'h', 'o', 'u', 'm', 'i', 32, 0,
|
|
/* 4907 */ 'e', 'v', 'm', 'w', 'u', 'm', 'i', 32, 0,
|
|
/* 4916 */ 'v', 'r', 'l', 'w', 'm', 'i', 32, 0,
|
|
/* 4924 */ 'q', 'v', 'a', 'l', 'i', 'g', 'n', 'i', 32, 0,
|
|
/* 4934 */ 'm', 'f', 'f', 's', 'c', 'r', 'n', 'i', 32, 0,
|
|
/* 4944 */ 'm', 'f', 'f', 's', 'c', 'd', 'r', 'n', 'i', 32, 0,
|
|
/* 4955 */ 'v', 's', 'l', 'd', 'o', 'i', 32, 0,
|
|
/* 4963 */ 'x', 's', 'r', 'd', 'p', 'i', 32, 0,
|
|
/* 4971 */ 'x', 'v', 'r', 'd', 'p', 'i', 32, 0,
|
|
/* 4979 */ 'x', 's', 'r', 'q', 'p', 'i', 32, 0,
|
|
/* 4987 */ 'x', 'v', 'r', 's', 'p', 'i', 32, 0,
|
|
/* 4995 */ 'x', 'o', 'r', 'i', 32, 0,
|
|
/* 5001 */ 'e', 'f', 'd', 'c', 'f', 's', 'i', 32, 0,
|
|
/* 5010 */ 'e', 'f', 's', 'c', 'f', 's', 'i', 32, 0,
|
|
/* 5019 */ 'e', 'v', 'f', 's', 'c', 'f', 's', 'i', 32, 0,
|
|
/* 5029 */ 'e', 'f', 'd', 'c', 't', 's', 'i', 32, 0,
|
|
/* 5038 */ 'e', 'f', 's', 'c', 't', 's', 'i', 32, 0,
|
|
/* 5047 */ 'e', 'v', 'f', 's', 'c', 't', 's', 'i', 32, 0,
|
|
/* 5057 */ 'q', 'v', 'e', 's', 'p', 'l', 'a', 't', 'i', 32, 0,
|
|
/* 5068 */ 'e', 'v', 's', 'p', 'l', 'a', 't', 'i', 32, 0,
|
|
/* 5078 */ 'e', 'f', 'd', 'c', 'f', 'u', 'i', 32, 0,
|
|
/* 5087 */ 'e', 'f', 's', 'c', 'f', 'u', 'i', 32, 0,
|
|
/* 5096 */ 'e', 'v', 'f', 's', 'c', 'f', 'u', 'i', 32, 0,
|
|
/* 5106 */ 'e', 'f', 'd', 'c', 't', 'u', 'i', 32, 0,
|
|
/* 5115 */ 'e', 'f', 's', 'c', 't', 'u', 'i', 32, 0,
|
|
/* 5124 */ 'e', 'v', 'f', 's', 'c', 't', 'u', 'i', 32, 0,
|
|
/* 5134 */ 's', 'r', 'a', 'w', 'i', 32, 0,
|
|
/* 5141 */ 'x', 'x', 's', 'l', 'd', 'w', 'i', 32, 0,
|
|
/* 5150 */ 'c', 'm', 'p', 'l', 'w', 'i', 32, 0,
|
|
/* 5158 */ 'e', 'v', 'r', 'l', 'w', 'i', 32, 0,
|
|
/* 5166 */ 'c', 'l', 'r', 'l', 's', 'l', 'w', 'i', 32, 0,
|
|
/* 5176 */ 'i', 'n', 's', 'l', 'w', 'i', 32, 0,
|
|
/* 5184 */ 'e', 'v', 's', 'l', 'w', 'i', 32, 0,
|
|
/* 5192 */ 'e', 'x', 't', 'l', 'w', 'i', 32, 0,
|
|
/* 5200 */ 'c', 'm', 'p', 'w', 'i', 32, 0,
|
|
/* 5207 */ 'c', 'l', 'r', 'r', 'w', 'i', 32, 0,
|
|
/* 5215 */ 'i', 'n', 's', 'r', 'w', 'i', 32, 0,
|
|
/* 5223 */ 'r', 'o', 't', 'r', 'w', 'i', 32, 0,
|
|
/* 5231 */ 'e', 'x', 't', 'r', 'w', 'i', 32, 0,
|
|
/* 5239 */ 'l', 's', 'w', 'i', 32, 0,
|
|
/* 5245 */ 's', 't', 's', 'w', 'i', 32, 0,
|
|
/* 5252 */ 't', 'w', 'i', 32, 0,
|
|
/* 5257 */ 'q', 'v', 's', 't', 'f', 'c', 'd', 'x', 'i', 32, 0,
|
|
/* 5268 */ 'q', 'v', 's', 't', 'f', 'd', 'x', 'i', 32, 0,
|
|
/* 5278 */ 'q', 'v', 's', 't', 'f', 'c', 's', 'x', 'i', 32, 0,
|
|
/* 5289 */ 'q', 'v', 's', 't', 'f', 's', 'x', 'i', 32, 0,
|
|
/* 5299 */ 'q', 'v', 's', 't', 'f', 'c', 'd', 'u', 'x', 'i', 32, 0,
|
|
/* 5311 */ 'q', 'v', 's', 't', 'f', 'd', 'u', 'x', 'i', 32, 0,
|
|
/* 5322 */ 'q', 'v', 's', 't', 'f', 'c', 's', 'u', 'x', 'i', 32, 0,
|
|
/* 5334 */ 'q', 'v', 's', 't', 'f', 's', 'u', 'x', 'i', 32, 0,
|
|
/* 5345 */ 't', 'c', 'h', 'e', 'c', 'k', 32, 0,
|
|
/* 5353 */ 'q', 'v', 'f', 'l', 'o', 'g', 'i', 'c', 'a', 'l', 32, 0,
|
|
/* 5365 */ 'b', 'l', 32, 0,
|
|
/* 5369 */ 'b', 'c', 'l', 32, 0,
|
|
/* 5374 */ 'r', 'l', 'd', 'c', 'l', 32, 0,
|
|
/* 5381 */ 'r', 'l', 'd', 'i', 'c', 'l', 32, 0,
|
|
/* 5389 */ 't', 'l', 'b', 'i', 'e', 'l', 32, 0,
|
|
/* 5397 */ 'q', 'v', 'f', 's', 'e', 'l', 32, 0,
|
|
/* 5405 */ 'i', 's', 'e', 'l', 32, 0,
|
|
/* 5411 */ 'v', 's', 'e', 'l', 32, 0,
|
|
/* 5417 */ 'x', 'x', 's', 'e', 'l', 32, 0,
|
|
/* 5424 */ 'd', 'c', 'b', 'f', 'l', 32, 0,
|
|
/* 5431 */ 'l', 'x', 'v', 'l', 'l', 32, 0,
|
|
/* 5438 */ 's', 't', 'x', 'v', 'l', 'l', 32, 0,
|
|
/* 5446 */ 'b', 'c', 'l', 'r', 'l', 32, 0,
|
|
/* 5453 */ 'b', 'c', 'c', 't', 'r', 'l', 32, 0,
|
|
/* 5461 */ 'm', 'f', 'f', 's', 'l', 32, 0,
|
|
/* 5468 */ 'l', 'v', 's', 'l', 32, 0,
|
|
/* 5474 */ 'e', 'f', 'd', 'm', 'u', 'l', 32, 0,
|
|
/* 5482 */ 'q', 'v', 'f', 'm', 'u', 'l', 32, 0,
|
|
/* 5490 */ 'e', 'f', 's', 'm', 'u', 'l', 32, 0,
|
|
/* 5498 */ 'e', 'v', 'f', 's', 'm', 'u', 'l', 32, 0,
|
|
/* 5507 */ 'q', 'v', 'f', 'x', 'm', 'u', 'l', 32, 0,
|
|
/* 5516 */ 'l', 'x', 'v', 'l', 32, 0,
|
|
/* 5522 */ 's', 't', 'x', 'v', 'l', 32, 0,
|
|
/* 5529 */ 'l', 'v', 'x', 'l', 32, 0,
|
|
/* 5535 */ 's', 't', 'v', 'x', 'l', 32, 0,
|
|
/* 5542 */ 'd', 'c', 'b', 'z', 'l', 32, 0,
|
|
/* 5549 */ 'b', 'd', 'z', 'l', 32, 0,
|
|
/* 5555 */ 'b', 'd', 'n', 'z', 'l', 32, 0,
|
|
/* 5562 */ 'v', 'm', 's', 'u', 'm', 'm', 'b', 'm', 32, 0,
|
|
/* 5572 */ 'v', 's', 'u', 'b', 'u', 'b', 'm', 32, 0,
|
|
/* 5581 */ 'v', 'a', 'd', 'd', 'u', 'b', 'm', 32, 0,
|
|
/* 5590 */ 'v', 'm', 's', 'u', 'm', 'u', 'b', 'm', 32, 0,
|
|
/* 5600 */ 'v', 's', 'u', 'b', 'u', 'd', 'm', 32, 0,
|
|
/* 5609 */ 'v', 'a', 'd', 'd', 'u', 'd', 'm', 32, 0,
|
|
/* 5618 */ 'v', 'm', 's', 'u', 'm', 's', 'h', 'm', 32, 0,
|
|
/* 5628 */ 'v', 's', 'u', 'b', 'u', 'h', 'm', 32, 0,
|
|
/* 5637 */ 'v', 'm', 'l', 'a', 'd', 'd', 'u', 'h', 'm', 32, 0,
|
|
/* 5648 */ 'v', 'a', 'd', 'd', 'u', 'h', 'm', 32, 0,
|
|
/* 5657 */ 'v', 'm', 's', 'u', 'm', 'u', 'h', 'm', 32, 0,
|
|
/* 5667 */ 'v', 'r', 'f', 'i', 'm', 32, 0,
|
|
/* 5674 */ 'x', 's', 'r', 'd', 'p', 'i', 'm', 32, 0,
|
|
/* 5683 */ 'x', 'v', 'r', 'd', 'p', 'i', 'm', 32, 0,
|
|
/* 5692 */ 'x', 'v', 'r', 's', 'p', 'i', 'm', 32, 0,
|
|
/* 5701 */ 'q', 'v', 'f', 'r', 'i', 'm', 32, 0,
|
|
/* 5709 */ 'v', 'r', 'l', 'd', 'n', 'm', 32, 0,
|
|
/* 5717 */ 'r', 'l', 'w', 'i', 'n', 'm', 32, 0,
|
|
/* 5725 */ 'v', 'r', 'l', 'w', 'n', 'm', 32, 0,
|
|
/* 5733 */ 'v', 's', 'u', 'b', 'u', 'q', 'm', 32, 0,
|
|
/* 5742 */ 'v', 'a', 'd', 'd', 'u', 'q', 'm', 32, 0,
|
|
/* 5751 */ 'v', 's', 'u', 'b', 'e', 'u', 'q', 'm', 32, 0,
|
|
/* 5761 */ 'v', 'a', 'd', 'd', 'e', 'u', 'q', 'm', 32, 0,
|
|
/* 5771 */ 'q', 'v', 'f', 'p', 'e', 'r', 'm', 32, 0,
|
|
/* 5780 */ 'v', 'p', 'e', 'r', 'm', 32, 0,
|
|
/* 5787 */ 'x', 'x', 'p', 'e', 'r', 'm', 32, 0,
|
|
/* 5795 */ 'v', 'p', 'k', 'u', 'd', 'u', 'm', 32, 0,
|
|
/* 5804 */ 'v', 'p', 'k', 'u', 'h', 'u', 'm', 32, 0,
|
|
/* 5813 */ 'v', 'p', 'k', 'u', 'w', 'u', 'm', 32, 0,
|
|
/* 5822 */ 'v', 's', 'u', 'b', 'u', 'w', 'm', 32, 0,
|
|
/* 5831 */ 'v', 'a', 'd', 'd', 'u', 'w', 'm', 32, 0,
|
|
/* 5840 */ 'v', 'm', 'u', 'l', 'u', 'w', 'm', 32, 0,
|
|
/* 5849 */ 'e', 'v', 'm', 'h', 'e', 'g', 's', 'm', 'f', 'a', 'n', 32, 0,
|
|
/* 5862 */ 'e', 'v', 'm', 'h', 'o', 'g', 's', 'm', 'f', 'a', 'n', 32, 0,
|
|
/* 5875 */ 'e', 'v', 'm', 'w', 's', 'm', 'f', 'a', 'n', 32, 0,
|
|
/* 5886 */ 'e', 'v', 'm', 'w', 's', 's', 'f', 'a', 'n', 32, 0,
|
|
/* 5897 */ 'e', 'v', 'm', 'h', 'e', 'g', 's', 'm', 'i', 'a', 'n', 32, 0,
|
|
/* 5910 */ 'e', 'v', 'm', 'h', 'o', 'g', 's', 'm', 'i', 'a', 'n', 32, 0,
|
|
/* 5923 */ 'e', 'v', 'm', 'w', 's', 'm', 'i', 'a', 'n', 32, 0,
|
|
/* 5934 */ 'e', 'v', 'm', 'h', 'e', 'g', 'u', 'm', 'i', 'a', 'n', 32, 0,
|
|
/* 5947 */ 'e', 'v', 'm', 'h', 'o', 'g', 'u', 'm', 'i', 'a', 'n', 32, 0,
|
|
/* 5960 */ 'e', 'v', 'm', 'w', 'u', 'm', 'i', 'a', 'n', 32, 0,
|
|
/* 5971 */ 'q', 'v', 'f', 't', 's', 't', 'n', 'a', 'n', 32, 0,
|
|
/* 5982 */ 'q', 'v', 'f', 'c', 'p', 's', 'g', 'n', 32, 0,
|
|
/* 5992 */ 'v', 'r', 'f', 'i', 'n', 32, 0,
|
|
/* 5999 */ 'q', 'v', 'f', 'r', 'i', 'n', 32, 0,
|
|
/* 6007 */ 'm', 'f', 's', 'r', 'i', 'n', 32, 0,
|
|
/* 6015 */ 'm', 't', 's', 'r', 'i', 'n', 32, 0,
|
|
/* 6023 */ 'x', 's', 'c', 'v', 's', 'p', 'd', 'p', 'n', 32, 0,
|
|
/* 6034 */ 'x', 's', 'c', 'v', 'd', 'p', 's', 'p', 'n', 32, 0,
|
|
/* 6045 */ 'd', 'a', 'r', 'n', 32, 0,
|
|
/* 6051 */ 'm', 'f', 'f', 's', 'c', 'r', 'n', 32, 0,
|
|
/* 6060 */ 'm', 'f', 'f', 's', 'c', 'd', 'r', 'n', 32, 0,
|
|
/* 6070 */ 'e', 'v', 's', 't', 'w', 'h', 'o', 32, 0,
|
|
/* 6079 */ 'e', 'v', 'm', 'e', 'r', 'g', 'e', 'l', 'o', 32, 0,
|
|
/* 6090 */ 'e', 'v', 'm', 'e', 'r', 'g', 'e', 'h', 'i', 'l', 'o', 32, 0,
|
|
/* 6103 */ 'v', 's', 'l', 'o', 32, 0,
|
|
/* 6109 */ 'x', 's', 'c', 'v', 'q', 'p', 'd', 'p', 'o', 32, 0,
|
|
/* 6120 */ 'x', 's', 'n', 'm', 's', 'u', 'b', 'q', 'p', 'o', 32, 0,
|
|
/* 6132 */ 'x', 's', 'm', 's', 'u', 'b', 'q', 'p', 'o', 32, 0,
|
|
/* 6143 */ 'x', 's', 's', 'u', 'b', 'q', 'p', 'o', 32, 0,
|
|
/* 6153 */ 'x', 's', 'n', 'm', 'a', 'd', 'd', 'q', 'p', 'o', 32, 0,
|
|
/* 6165 */ 'x', 's', 'm', 'a', 'd', 'd', 'q', 'p', 'o', 32, 0,
|
|
/* 6176 */ 'x', 's', 'a', 'd', 'd', 'q', 'p', 'o', 32, 0,
|
|
/* 6186 */ 'x', 's', 'm', 'u', 'l', 'q', 'p', 'o', 32, 0,
|
|
/* 6196 */ 'x', 's', 's', 'q', 'r', 't', 'q', 'p', 'o', 32, 0,
|
|
/* 6207 */ 'x', 's', 'd', 'i', 'v', 'q', 'p', 'o', 32, 0,
|
|
/* 6217 */ 'v', 's', 'r', 'o', 32, 0,
|
|
/* 6223 */ 'e', 'v', 's', 't', 'w', 'w', 'o', 32, 0,
|
|
/* 6232 */ 'x', 's', 'n', 'm', 's', 'u', 'b', 'a', 'd', 'p', 32, 0,
|
|
/* 6244 */ 'x', 'v', 'n', 'm', 's', 'u', 'b', 'a', 'd', 'p', 32, 0,
|
|
/* 6256 */ 'x', 's', 'm', 's', 'u', 'b', 'a', 'd', 'p', 32, 0,
|
|
/* 6267 */ 'x', 'v', 'm', 's', 'u', 'b', 'a', 'd', 'p', 32, 0,
|
|
/* 6278 */ 'x', 's', 'n', 'm', 'a', 'd', 'd', 'a', 'd', 'p', 32, 0,
|
|
/* 6290 */ 'x', 'v', 'n', 'm', 'a', 'd', 'd', 'a', 'd', 'p', 32, 0,
|
|
/* 6302 */ 'x', 's', 'm', 'a', 'd', 'd', 'a', 'd', 'p', 32, 0,
|
|
/* 6313 */ 'x', 'v', 'm', 'a', 'd', 'd', 'a', 'd', 'p', 32, 0,
|
|
/* 6324 */ 'x', 's', 's', 'u', 'b', 'd', 'p', 32, 0,
|
|
/* 6333 */ 'x', 'v', 's', 'u', 'b', 'd', 'p', 32, 0,
|
|
/* 6342 */ 'x', 's', 't', 's', 't', 'd', 'c', 'd', 'p', 32, 0,
|
|
/* 6353 */ 'x', 'v', 't', 's', 't', 'd', 'c', 'd', 'p', 32, 0,
|
|
/* 6364 */ 'x', 's', 'm', 'i', 'n', 'c', 'd', 'p', 32, 0,
|
|
/* 6374 */ 'x', 's', 'm', 'a', 'x', 'c', 'd', 'p', 32, 0,
|
|
/* 6384 */ 'x', 's', 'a', 'd', 'd', 'd', 'p', 32, 0,
|
|
/* 6393 */ 'x', 'v', 'a', 'd', 'd', 'd', 'p', 32, 0,
|
|
/* 6402 */ 'x', 's', 'c', 'v', 's', 'x', 'd', 'd', 'p', 32, 0,
|
|
/* 6413 */ 'x', 'v', 'c', 'v', 's', 'x', 'd', 'd', 'p', 32, 0,
|
|
/* 6424 */ 'x', 's', 'c', 'v', 'u', 'x', 'd', 'd', 'p', 32, 0,
|
|
/* 6435 */ 'x', 'v', 'c', 'v', 'u', 'x', 'd', 'd', 'p', 32, 0,
|
|
/* 6446 */ 'x', 's', 'c', 'm', 'p', 'g', 'e', 'd', 'p', 32, 0,
|
|
/* 6457 */ 'x', 'v', 'c', 'm', 'p', 'g', 'e', 'd', 'p', 32, 0,
|
|
/* 6468 */ 'x', 's', 'r', 'e', 'd', 'p', 32, 0,
|
|
/* 6476 */ 'x', 'v', 'r', 'e', 'd', 'p', 32, 0,
|
|
/* 6484 */ 'x', 's', 'r', 's', 'q', 'r', 't', 'e', 'd', 'p', 32, 0,
|
|
/* 6496 */ 'x', 'v', 'r', 's', 'q', 'r', 't', 'e', 'd', 'p', 32, 0,
|
|
/* 6508 */ 'x', 's', 'n', 'e', 'g', 'd', 'p', 32, 0,
|
|
/* 6517 */ 'x', 'v', 'n', 'e', 'g', 'd', 'p', 32, 0,
|
|
/* 6526 */ 'x', 's', 'x', 's', 'i', 'g', 'd', 'p', 32, 0,
|
|
/* 6536 */ 'x', 'v', 'x', 's', 'i', 'g', 'd', 'p', 32, 0,
|
|
/* 6546 */ 'x', 's', 'm', 'i', 'n', 'j', 'd', 'p', 32, 0,
|
|
/* 6556 */ 'x', 's', 'm', 'a', 'x', 'j', 'd', 'p', 32, 0,
|
|
/* 6566 */ 'x', 's', 'm', 'u', 'l', 'd', 'p', 32, 0,
|
|
/* 6575 */ 'x', 'v', 'm', 'u', 'l', 'd', 'p', 32, 0,
|
|
/* 6584 */ 'x', 's', 'n', 'm', 's', 'u', 'b', 'm', 'd', 'p', 32, 0,
|
|
/* 6596 */ 'x', 'v', 'n', 'm', 's', 'u', 'b', 'm', 'd', 'p', 32, 0,
|
|
/* 6608 */ 'x', 's', 'm', 's', 'u', 'b', 'm', 'd', 'p', 32, 0,
|
|
/* 6619 */ 'x', 'v', 'm', 's', 'u', 'b', 'm', 'd', 'p', 32, 0,
|
|
/* 6630 */ 'x', 's', 'n', 'm', 'a', 'd', 'd', 'm', 'd', 'p', 32, 0,
|
|
/* 6642 */ 'x', 'v', 'n', 'm', 'a', 'd', 'd', 'm', 'd', 'p', 32, 0,
|
|
/* 6654 */ 'x', 's', 'm', 'a', 'd', 'd', 'm', 'd', 'p', 32, 0,
|
|
/* 6665 */ 'x', 'v', 'm', 'a', 'd', 'd', 'm', 'd', 'p', 32, 0,
|
|
/* 6676 */ 'x', 's', 'c', 'p', 's', 'g', 'n', 'd', 'p', 32, 0,
|
|
/* 6687 */ 'x', 'v', 'c', 'p', 's', 'g', 'n', 'd', 'p', 32, 0,
|
|
/* 6698 */ 'x', 's', 'm', 'i', 'n', 'd', 'p', 32, 0,
|
|
/* 6707 */ 'x', 'v', 'm', 'i', 'n', 'd', 'p', 32, 0,
|
|
/* 6716 */ 'x', 's', 'c', 'm', 'p', 'o', 'd', 'p', 32, 0,
|
|
/* 6726 */ 'x', 's', 'c', 'v', 'h', 'p', 'd', 'p', 32, 0,
|
|
/* 6736 */ 'x', 's', 'c', 'v', 'q', 'p', 'd', 'p', 32, 0,
|
|
/* 6746 */ 'x', 's', 'c', 'v', 's', 'p', 'd', 'p', 32, 0,
|
|
/* 6756 */ 'x', 'v', 'c', 'v', 's', 'p', 'd', 'p', 32, 0,
|
|
/* 6766 */ 'x', 's', 'i', 'e', 'x', 'p', 'd', 'p', 32, 0,
|
|
/* 6776 */ 'x', 'v', 'i', 'e', 'x', 'p', 'd', 'p', 32, 0,
|
|
/* 6786 */ 'x', 's', 'c', 'm', 'p', 'e', 'x', 'p', 'd', 'p', 32, 0,
|
|
/* 6798 */ 'x', 's', 'x', 'e', 'x', 'p', 'd', 'p', 32, 0,
|
|
/* 6808 */ 'x', 'v', 'x', 'e', 'x', 'p', 'd', 'p', 32, 0,
|
|
/* 6818 */ 'x', 's', 'c', 'm', 'p', 'e', 'q', 'd', 'p', 32, 0,
|
|
/* 6829 */ 'x', 'v', 'c', 'm', 'p', 'e', 'q', 'd', 'p', 32, 0,
|
|
/* 6840 */ 'x', 's', 'n', 'a', 'b', 's', 'd', 'p', 32, 0,
|
|
/* 6850 */ 'x', 'v', 'n', 'a', 'b', 's', 'd', 'p', 32, 0,
|
|
/* 6860 */ 'x', 's', 'a', 'b', 's', 'd', 'p', 32, 0,
|
|
/* 6869 */ 'x', 'v', 'a', 'b', 's', 'd', 'p', 32, 0,
|
|
/* 6878 */ 'x', 's', 'c', 'm', 'p', 'g', 't', 'd', 'p', 32, 0,
|
|
/* 6889 */ 'x', 'v', 'c', 'm', 'p', 'g', 't', 'd', 'p', 32, 0,
|
|
/* 6900 */ 'x', 's', 's', 'q', 'r', 't', 'd', 'p', 32, 0,
|
|
/* 6910 */ 'x', 's', 't', 's', 'q', 'r', 't', 'd', 'p', 32, 0,
|
|
/* 6921 */ 'x', 'v', 't', 's', 'q', 'r', 't', 'd', 'p', 32, 0,
|
|
/* 6932 */ 'x', 'v', 's', 'q', 'r', 't', 'd', 'p', 32, 0,
|
|
/* 6942 */ 'x', 's', 'c', 'm', 'p', 'u', 'd', 'p', 32, 0,
|
|
/* 6952 */ 'x', 's', 'd', 'i', 'v', 'd', 'p', 32, 0,
|
|
/* 6961 */ 'x', 's', 't', 'd', 'i', 'v', 'd', 'p', 32, 0,
|
|
/* 6971 */ 'x', 'v', 't', 'd', 'i', 'v', 'd', 'p', 32, 0,
|
|
/* 6981 */ 'x', 'v', 'd', 'i', 'v', 'd', 'p', 32, 0,
|
|
/* 6990 */ 'x', 'v', 'c', 'v', 's', 'x', 'w', 'd', 'p', 32, 0,
|
|
/* 7001 */ 'x', 'v', 'c', 'v', 'u', 'x', 'w', 'd', 'p', 32, 0,
|
|
/* 7012 */ 'x', 's', 'm', 'a', 'x', 'd', 'p', 32, 0,
|
|
/* 7021 */ 'x', 'v', 'm', 'a', 'x', 'd', 'p', 32, 0,
|
|
/* 7030 */ 'd', 'c', 'b', 'f', 'e', 'p', 32, 0,
|
|
/* 7038 */ 'i', 'c', 'b', 'i', 'e', 'p', 32, 0,
|
|
/* 7046 */ 'd', 'c', 'b', 'z', 'l', 'e', 'p', 32, 0,
|
|
/* 7055 */ 'd', 'c', 'b', 't', 'e', 'p', 32, 0,
|
|
/* 7063 */ 'd', 'c', 'b', 's', 't', 'e', 'p', 32, 0,
|
|
/* 7072 */ 'd', 'c', 'b', 't', 's', 't', 'e', 'p', 32, 0,
|
|
/* 7082 */ 'd', 'c', 'b', 'z', 'e', 'p', 32, 0,
|
|
/* 7090 */ 'v', 'c', 'm', 'p', 'b', 'f', 'p', 32, 0,
|
|
/* 7099 */ 'v', 'n', 'm', 's', 'u', 'b', 'f', 'p', 32, 0,
|
|
/* 7109 */ 'v', 's', 'u', 'b', 'f', 'p', 32, 0,
|
|
/* 7117 */ 'v', 'm', 'a', 'd', 'd', 'f', 'p', 32, 0,
|
|
/* 7126 */ 'v', 'a', 'd', 'd', 'f', 'p', 32, 0,
|
|
/* 7134 */ 'v', 'l', 'o', 'g', 'e', 'f', 'p', 32, 0,
|
|
/* 7143 */ 'v', 'c', 'm', 'p', 'g', 'e', 'f', 'p', 32, 0,
|
|
/* 7153 */ 'v', 'r', 'e', 'f', 'p', 32, 0,
|
|
/* 7160 */ 'v', 'e', 'x', 'p', 't', 'e', 'f', 'p', 32, 0,
|
|
/* 7170 */ 'v', 'r', 's', 'q', 'r', 't', 'e', 'f', 'p', 32, 0,
|
|
/* 7181 */ 'v', 'm', 'i', 'n', 'f', 'p', 32, 0,
|
|
/* 7189 */ 'v', 'c', 'm', 'p', 'e', 'q', 'f', 'p', 32, 0,
|
|
/* 7199 */ 'v', 'c', 'm', 'p', 'g', 't', 'f', 'p', 32, 0,
|
|
/* 7209 */ 'v', 'm', 'a', 'x', 'f', 'p', 32, 0,
|
|
/* 7217 */ 'x', 's', 'c', 'v', 'd', 'p', 'h', 'p', 32, 0,
|
|
/* 7227 */ 'x', 'v', 'c', 'v', 's', 'p', 'h', 'p', 32, 0,
|
|
/* 7237 */ 'v', 'r', 'f', 'i', 'p', 32, 0,
|
|
/* 7244 */ 'x', 's', 'r', 'd', 'p', 'i', 'p', 32, 0,
|
|
/* 7253 */ 'x', 'v', 'r', 'd', 'p', 'i', 'p', 32, 0,
|
|
/* 7262 */ 'x', 'v', 'r', 's', 'p', 'i', 'p', 32, 0,
|
|
/* 7271 */ 'q', 'v', 'f', 'r', 'i', 'p', 32, 0,
|
|
/* 7279 */ 'd', 'c', 'b', 'f', 'l', 'p', 32, 0,
|
|
/* 7287 */ 'x', 's', 'n', 'm', 's', 'u', 'b', 'q', 'p', 32, 0,
|
|
/* 7298 */ 'x', 's', 'm', 's', 'u', 'b', 'q', 'p', 32, 0,
|
|
/* 7308 */ 'x', 's', 's', 'u', 'b', 'q', 'p', 32, 0,
|
|
/* 7317 */ 'x', 's', 't', 's', 't', 'd', 'c', 'q', 'p', 32, 0,
|
|
/* 7328 */ 'x', 's', 'n', 'm', 'a', 'd', 'd', 'q', 'p', 32, 0,
|
|
/* 7339 */ 'x', 's', 'm', 'a', 'd', 'd', 'q', 'p', 32, 0,
|
|
/* 7349 */ 'x', 's', 'a', 'd', 'd', 'q', 'p', 32, 0,
|
|
/* 7358 */ 'x', 's', 'c', 'v', 's', 'd', 'q', 'p', 32, 0,
|
|
/* 7368 */ 'x', 's', 'c', 'v', 'u', 'd', 'q', 'p', 32, 0,
|
|
/* 7378 */ 'x', 's', 'n', 'e', 'g', 'q', 'p', 32, 0,
|
|
/* 7387 */ 'x', 's', 'x', 's', 'i', 'g', 'q', 'p', 32, 0,
|
|
/* 7397 */ 'x', 's', 'm', 'u', 'l', 'q', 'p', 32, 0,
|
|
/* 7406 */ 'x', 's', 'c', 'p', 's', 'g', 'n', 'q', 'p', 32, 0,
|
|
/* 7417 */ 'x', 's', 'c', 'm', 'p', 'o', 'q', 'p', 32, 0,
|
|
/* 7427 */ 'x', 's', 'c', 'v', 'd', 'p', 'q', 'p', 32, 0,
|
|
/* 7437 */ 'x', 's', 'i', 'e', 'x', 'p', 'q', 'p', 32, 0,
|
|
/* 7447 */ 'x', 's', 'c', 'm', 'p', 'e', 'x', 'p', 'q', 'p', 32, 0,
|
|
/* 7459 */ 'x', 's', 'x', 'e', 'x', 'p', 'q', 'p', 32, 0,
|
|
/* 7469 */ 'x', 's', 'n', 'a', 'b', 's', 'q', 'p', 32, 0,
|
|
/* 7479 */ 'x', 's', 'a', 'b', 's', 'q', 'p', 32, 0,
|
|
/* 7488 */ 'x', 's', 's', 'q', 'r', 't', 'q', 'p', 32, 0,
|
|
/* 7498 */ 'x', 's', 'c', 'm', 'p', 'u', 'q', 'p', 32, 0,
|
|
/* 7508 */ 'x', 's', 'd', 'i', 'v', 'q', 'p', 32, 0,
|
|
/* 7517 */ 'x', 's', 'n', 'm', 's', 'u', 'b', 'a', 's', 'p', 32, 0,
|
|
/* 7529 */ 'x', 'v', 'n', 'm', 's', 'u', 'b', 'a', 's', 'p', 32, 0,
|
|
/* 7541 */ 'x', 's', 'm', 's', 'u', 'b', 'a', 's', 'p', 32, 0,
|
|
/* 7552 */ 'x', 'v', 'm', 's', 'u', 'b', 'a', 's', 'p', 32, 0,
|
|
/* 7563 */ 'x', 's', 'n', 'm', 'a', 'd', 'd', 'a', 's', 'p', 32, 0,
|
|
/* 7575 */ 'x', 'v', 'n', 'm', 'a', 'd', 'd', 'a', 's', 'p', 32, 0,
|
|
/* 7587 */ 'x', 's', 'm', 'a', 'd', 'd', 'a', 's', 'p', 32, 0,
|
|
/* 7598 */ 'x', 'v', 'm', 'a', 'd', 'd', 'a', 's', 'p', 32, 0,
|
|
/* 7609 */ 'x', 's', 's', 'u', 'b', 's', 'p', 32, 0,
|
|
/* 7618 */ 'x', 'v', 's', 'u', 'b', 's', 'p', 32, 0,
|
|
/* 7627 */ 'x', 's', 't', 's', 't', 'd', 'c', 's', 'p', 32, 0,
|
|
/* 7638 */ 'x', 'v', 't', 's', 't', 'd', 'c', 's', 'p', 32, 0,
|
|
/* 7649 */ 'x', 's', 'a', 'd', 'd', 's', 'p', 32, 0,
|
|
/* 7658 */ 'x', 'v', 'a', 'd', 'd', 's', 'p', 32, 0,
|
|
/* 7667 */ 'x', 's', 'c', 'v', 's', 'x', 'd', 's', 'p', 32, 0,
|
|
/* 7678 */ 'x', 'v', 'c', 'v', 's', 'x', 'd', 's', 'p', 32, 0,
|
|
/* 7689 */ 'x', 's', 'c', 'v', 'u', 'x', 'd', 's', 'p', 32, 0,
|
|
/* 7700 */ 'x', 'v', 'c', 'v', 'u', 'x', 'd', 's', 'p', 32, 0,
|
|
/* 7711 */ 'x', 'v', 'c', 'm', 'p', 'g', 'e', 's', 'p', 32, 0,
|
|
/* 7722 */ 'x', 's', 'r', 'e', 's', 'p', 32, 0,
|
|
/* 7730 */ 'x', 'v', 'r', 'e', 's', 'p', 32, 0,
|
|
/* 7738 */ 'x', 's', 'r', 's', 'q', 'r', 't', 'e', 's', 'p', 32, 0,
|
|
/* 7750 */ 'x', 'v', 'r', 's', 'q', 'r', 't', 'e', 's', 'p', 32, 0,
|
|
/* 7762 */ 'x', 'v', 'n', 'e', 'g', 's', 'p', 32, 0,
|
|
/* 7771 */ 'x', 'v', 'x', 's', 'i', 'g', 's', 'p', 32, 0,
|
|
/* 7781 */ 'x', 's', 'm', 'u', 'l', 's', 'p', 32, 0,
|
|
/* 7790 */ 'x', 'v', 'm', 'u', 'l', 's', 'p', 32, 0,
|
|
/* 7799 */ 'x', 's', 'n', 'm', 's', 'u', 'b', 'm', 's', 'p', 32, 0,
|
|
/* 7811 */ 'x', 'v', 'n', 'm', 's', 'u', 'b', 'm', 's', 'p', 32, 0,
|
|
/* 7823 */ 'x', 's', 'm', 's', 'u', 'b', 'm', 's', 'p', 32, 0,
|
|
/* 7834 */ 'x', 'v', 'm', 's', 'u', 'b', 'm', 's', 'p', 32, 0,
|
|
/* 7845 */ 'x', 's', 'n', 'm', 'a', 'd', 'd', 'm', 's', 'p', 32, 0,
|
|
/* 7857 */ 'x', 'v', 'n', 'm', 'a', 'd', 'd', 'm', 's', 'p', 32, 0,
|
|
/* 7869 */ 'x', 's', 'm', 'a', 'd', 'd', 'm', 's', 'p', 32, 0,
|
|
/* 7880 */ 'x', 'v', 'm', 'a', 'd', 'd', 'm', 's', 'p', 32, 0,
|
|
/* 7891 */ 'x', 'v', 'c', 'p', 's', 'g', 'n', 's', 'p', 32, 0,
|
|
/* 7902 */ 'x', 'v', 'm', 'i', 'n', 's', 'p', 32, 0,
|
|
/* 7911 */ 'x', 's', 'c', 'v', 'd', 'p', 's', 'p', 32, 0,
|
|
/* 7921 */ 'x', 'v', 'c', 'v', 'd', 'p', 's', 'p', 32, 0,
|
|
/* 7931 */ 'x', 'v', 'c', 'v', 'h', 'p', 's', 'p', 32, 0,
|
|
/* 7941 */ 'x', 'v', 'i', 'e', 'x', 'p', 's', 'p', 32, 0,
|
|
/* 7951 */ 'x', 'v', 'x', 'e', 'x', 'p', 's', 'p', 32, 0,
|
|
/* 7961 */ 'x', 'v', 'c', 'm', 'p', 'e', 'q', 's', 'p', 32, 0,
|
|
/* 7972 */ 'q', 'v', 'f', 'r', 's', 'p', 32, 0,
|
|
/* 7980 */ 'x', 's', 'r', 's', 'p', 32, 0,
|
|
/* 7987 */ 'x', 'v', 'n', 'a', 'b', 's', 's', 'p', 32, 0,
|
|
/* 7997 */ 'x', 'v', 'a', 'b', 's', 's', 'p', 32, 0,
|
|
/* 8006 */ 'l', 'x', 's', 's', 'p', 32, 0,
|
|
/* 8013 */ 's', 't', 'x', 's', 's', 'p', 32, 0,
|
|
/* 8021 */ 'x', 'v', 'c', 'm', 'p', 'g', 't', 's', 'p', 32, 0,
|
|
/* 8032 */ 'x', 's', 's', 'q', 'r', 't', 's', 'p', 32, 0,
|
|
/* 8042 */ 'x', 'v', 't', 's', 'q', 'r', 't', 's', 'p', 32, 0,
|
|
/* 8053 */ 'x', 'v', 's', 'q', 'r', 't', 's', 'p', 32, 0,
|
|
/* 8063 */ 'x', 's', 'd', 'i', 'v', 's', 'p', 32, 0,
|
|
/* 8072 */ 'x', 'v', 't', 'd', 'i', 'v', 's', 'p', 32, 0,
|
|
/* 8082 */ 'x', 'v', 'd', 'i', 'v', 's', 'p', 32, 0,
|
|
/* 8091 */ 'x', 'v', 'c', 'v', 's', 'x', 'w', 's', 'p', 32, 0,
|
|
/* 8102 */ 'x', 'v', 'c', 'v', 'u', 'x', 'w', 's', 'p', 32, 0,
|
|
/* 8113 */ 'x', 'v', 'm', 'a', 'x', 's', 'p', 32, 0,
|
|
/* 8122 */ 'x', 's', 'r', 'q', 'p', 'x', 'p', 32, 0,
|
|
/* 8131 */ 'v', 'p', 'r', 't', 'y', 'b', 'q', 32, 0,
|
|
/* 8140 */ 'e', 'f', 'd', 'c', 'm', 'p', 'e', 'q', 32, 0,
|
|
/* 8150 */ 'q', 'v', 'f', 'c', 'm', 'p', 'e', 'q', 32, 0,
|
|
/* 8160 */ 'e', 'f', 's', 'c', 'm', 'p', 'e', 'q', 32, 0,
|
|
/* 8170 */ 'e', 'v', 'f', 's', 'c', 'm', 'p', 'e', 'q', 32, 0,
|
|
/* 8181 */ 'e', 'v', 'c', 'm', 'p', 'e', 'q', 32, 0,
|
|
/* 8190 */ 'e', 'f', 'd', 't', 's', 't', 'e', 'q', 32, 0,
|
|
/* 8200 */ 'e', 'f', 's', 't', 's', 't', 'e', 'q', 32, 0,
|
|
/* 8210 */ 'e', 'v', 'f', 's', 't', 's', 't', 'e', 'q', 32, 0,
|
|
/* 8221 */ 'v', 'b', 'p', 'e', 'r', 'm', 'q', 32, 0,
|
|
/* 8230 */ 'x', 'x', 'b', 'r', 'q', 32, 0,
|
|
/* 8237 */ 'v', 'm', 'u', 'l', '1', '0', 'u', 'q', 32, 0,
|
|
/* 8247 */ 'v', 'm', 'u', 'l', '1', '0', 'c', 'u', 'q', 32, 0,
|
|
/* 8258 */ 'v', 's', 'u', 'b', 'c', 'u', 'q', 32, 0,
|
|
/* 8267 */ 'v', 'a', 'd', 'd', 'c', 'u', 'q', 32, 0,
|
|
/* 8276 */ 'v', 'm', 'u', 'l', '1', '0', 'e', 'c', 'u', 'q', 32, 0,
|
|
/* 8288 */ 'v', 's', 'u', 'b', 'e', 'c', 'u', 'q', 32, 0,
|
|
/* 8298 */ 'v', 'a', 'd', 'd', 'e', 'c', 'u', 'q', 32, 0,
|
|
/* 8308 */ 'v', 'm', 'u', 'l', '1', '0', 'e', 'u', 'q', 32, 0,
|
|
/* 8319 */ '#', 'T', 'C', '_', 'R', 'E', 'T', 'U', 'R', 'N', 'r', 32, 0,
|
|
/* 8332 */ 'm', 'b', 'a', 'r', 32, 0,
|
|
/* 8338 */ 'm', 'f', 'd', 'c', 'r', 32, 0,
|
|
/* 8345 */ 'r', 'l', 'd', 'c', 'r', 32, 0,
|
|
/* 8352 */ 'm', 't', 'd', 'c', 'r', 32, 0,
|
|
/* 8359 */ 'm', 'f', 'c', 'r', 32, 0,
|
|
/* 8365 */ 'r', 'l', 'd', 'i', 'c', 'r', 32, 0,
|
|
/* 8373 */ 'm', 'f', 'v', 's', 'c', 'r', 32, 0,
|
|
/* 8381 */ 'm', 't', 'v', 's', 'c', 'r', 32, 0,
|
|
/* 8389 */ 'v', 'n', 'c', 'i', 'p', 'h', 'e', 'r', 32, 0,
|
|
/* 8399 */ 'v', 'c', 'i', 'p', 'h', 'e', 'r', 32, 0,
|
|
/* 8408 */ 'b', 'c', 'l', 'r', 32, 0,
|
|
/* 8414 */ 'm', 'f', 'l', 'r', 32, 0,
|
|
/* 8420 */ 'm', 't', 'l', 'r', 32, 0,
|
|
/* 8426 */ 'q', 'v', 'f', 'm', 'r', 32, 0,
|
|
/* 8433 */ 'm', 'f', 'p', 'm', 'r', 32, 0,
|
|
/* 8440 */ 'm', 't', 'p', 'm', 'r', 32, 0,
|
|
/* 8447 */ 'v', 'p', 'e', 'r', 'm', 'r', 32, 0,
|
|
/* 8455 */ 'x', 'x', 'p', 'e', 'r', 'm', 'r', 32, 0,
|
|
/* 8464 */ 'x', 'x', 'l', 'o', 'r', 32, 0,
|
|
/* 8471 */ 'x', 'x', 'l', 'n', 'o', 'r', 32, 0,
|
|
/* 8479 */ 'c', 'r', 'n', 'o', 'r', 32, 0,
|
|
/* 8486 */ 'e', 'v', 'n', 'o', 'r', 32, 0,
|
|
/* 8493 */ 'c', 'r', 'o', 'r', 32, 0,
|
|
/* 8499 */ 'e', 'v', 'o', 'r', 32, 0,
|
|
/* 8505 */ 'x', 'x', 'l', 'x', 'o', 'r', 32, 0,
|
|
/* 8513 */ 'v', 'p', 'e', 'r', 'm', 'x', 'o', 'r', 32, 0,
|
|
/* 8523 */ 'c', 'r', 'x', 'o', 'r', 32, 0,
|
|
/* 8530 */ 'e', 'v', 'x', 'o', 'r', 32, 0,
|
|
/* 8537 */ 'm', 'f', 's', 'p', 'r', 32, 0,
|
|
/* 8544 */ 'm', 't', 's', 'p', 'r', 32, 0,
|
|
/* 8551 */ 'm', 'f', 's', 'r', 32, 0,
|
|
/* 8557 */ 'm', 'f', 'm', 's', 'r', 32, 0,
|
|
/* 8564 */ 'm', 't', 'm', 's', 'r', 32, 0,
|
|
/* 8571 */ 'm', 't', 's', 'r', 32, 0,
|
|
/* 8577 */ 'l', 'v', 's', 'r', 32, 0,
|
|
/* 8583 */ 'b', 'c', 'c', 't', 'r', 32, 0,
|
|
/* 8590 */ 'm', 'f', 'c', 't', 'r', 32, 0,
|
|
/* 8597 */ 'm', 't', 'c', 't', 'r', 32, 0,
|
|
/* 8604 */ 'e', 'f', 'd', 'a', 'b', 's', 32, 0,
|
|
/* 8612 */ 'q', 'v', 'f', 'a', 'b', 's', 32, 0,
|
|
/* 8620 */ 'e', 'f', 'd', 'n', 'a', 'b', 's', 32, 0,
|
|
/* 8629 */ 'q', 'v', 'f', 'n', 'a', 'b', 's', 32, 0,
|
|
/* 8638 */ 'e', 'f', 's', 'n', 'a', 'b', 's', 32, 0,
|
|
/* 8647 */ 'e', 'v', 'f', 's', 'n', 'a', 'b', 's', 32, 0,
|
|
/* 8657 */ 'e', 'f', 's', 'a', 'b', 's', 32, 0,
|
|
/* 8665 */ 'e', 'v', 'f', 's', 'a', 'b', 's', 32, 0,
|
|
/* 8674 */ 'e', 'v', 'a', 'b', 's', 32, 0,
|
|
/* 8681 */ 'v', 's', 'u', 'm', '4', 's', 'b', 's', 32, 0,
|
|
/* 8691 */ 'v', 's', 'u', 'b', 's', 'b', 's', 32, 0,
|
|
/* 8700 */ 'v', 'a', 'd', 'd', 's', 'b', 's', 32, 0,
|
|
/* 8709 */ 'v', 's', 'u', 'm', '4', 'u', 'b', 's', 32, 0,
|
|
/* 8719 */ 'v', 's', 'u', 'b', 'u', 'b', 's', 32, 0,
|
|
/* 8728 */ 'v', 'a', 'd', 'd', 'u', 'b', 's', 32, 0,
|
|
/* 8737 */ 'q', 'v', 'f', 's', 'u', 'b', 's', 32, 0,
|
|
/* 8746 */ 'q', 'v', 'f', 'm', 's', 'u', 'b', 's', 32, 0,
|
|
/* 8756 */ 'q', 'v', 'f', 'n', 'm', 's', 'u', 'b', 's', 32, 0,
|
|
/* 8767 */ 'q', 'v', 'f', 'a', 'd', 'd', 's', 32, 0,
|
|
/* 8776 */ 'q', 'v', 'f', 'm', 'a', 'd', 'd', 's', 32, 0,
|
|
/* 8786 */ 'q', 'v', 'f', 'n', 'm', 'a', 'd', 'd', 's', 32, 0,
|
|
/* 8797 */ 'q', 'v', 'f', 'x', 'x', 'c', 'p', 'n', 'm', 'a', 'd', 'd', 's', 32, 0,
|
|
/* 8812 */ 'q', 'v', 'f', 'x', 'x', 'n', 'p', 'm', 'a', 'd', 'd', 's', 32, 0,
|
|
/* 8826 */ 'q', 'v', 'f', 'x', 'm', 'a', 'd', 'd', 's', 32, 0,
|
|
/* 8837 */ 'q', 'v', 'f', 'x', 'x', 'm', 'a', 'd', 'd', 's', 32, 0,
|
|
/* 8849 */ 'q', 'v', 'f', 'c', 'f', 'i', 'd', 's', 32, 0,
|
|
/* 8859 */ 'd', 'c', 'b', 't', 'd', 's', 32, 0,
|
|
/* 8867 */ 'd', 'c', 'b', 't', 's', 't', 'd', 's', 32, 0,
|
|
/* 8877 */ 'x', 's', 'c', 'v', 'd', 'p', 's', 'x', 'd', 's', 32, 0,
|
|
/* 8889 */ 'x', 'v', 'c', 'v', 'd', 'p', 's', 'x', 'd', 's', 32, 0,
|
|
/* 8901 */ 'x', 'v', 'c', 'v', 's', 'p', 's', 'x', 'd', 's', 32, 0,
|
|
/* 8913 */ 'x', 's', 'c', 'v', 'd', 'p', 'u', 'x', 'd', 's', 32, 0,
|
|
/* 8925 */ 'x', 'v', 'c', 'v', 'd', 'p', 'u', 'x', 'd', 's', 32, 0,
|
|
/* 8937 */ 'x', 'v', 'c', 'v', 's', 'p', 'u', 'x', 'd', 's', 32, 0,
|
|
/* 8949 */ 'q', 'v', 'f', 'r', 'e', 's', 32, 0,
|
|
/* 8957 */ 'q', 'v', 'f', 'r', 's', 'q', 'r', 't', 'e', 's', 32, 0,
|
|
/* 8969 */ 'e', 'f', 'd', 'c', 'f', 's', 32, 0,
|
|
/* 8977 */ 'm', 'f', 'f', 's', 32, 0,
|
|
/* 8983 */ 'l', 'f', 's', 32, 0,
|
|
/* 8988 */ 'm', 'c', 'r', 'f', 's', 32, 0,
|
|
/* 8995 */ 's', 't', 'f', 's', 32, 0,
|
|
/* 9001 */ 'v', 's', 'u', 'm', '4', 's', 'h', 's', 32, 0,
|
|
/* 9011 */ 'v', 's', 'u', 'b', 's', 'h', 's', 32, 0,
|
|
/* 9020 */ 'v', 'm', 'h', 'a', 'd', 'd', 's', 'h', 's', 32, 0,
|
|
/* 9031 */ 'v', 'm', 'h', 'r', 'a', 'd', 'd', 's', 'h', 's', 32, 0,
|
|
/* 9043 */ 'v', 'a', 'd', 'd', 's', 'h', 's', 32, 0,
|
|
/* 9052 */ 'v', 'm', 's', 'u', 'm', 's', 'h', 's', 32, 0,
|
|
/* 9062 */ 'v', 's', 'u', 'b', 'u', 'h', 's', 32, 0,
|
|
/* 9071 */ 'v', 'a', 'd', 'd', 'u', 'h', 's', 32, 0,
|
|
/* 9080 */ 'v', 'm', 's', 'u', 'm', 'u', 'h', 's', 32, 0,
|
|
/* 9090 */ 's', 'u', 'b', 'i', 's', 32, 0,
|
|
/* 9097 */ 's', 'u', 'b', 'p', 'c', 'i', 's', 32, 0,
|
|
/* 9106 */ 'a', 'd', 'd', 'p', 'c', 'i', 's', 32, 0,
|
|
/* 9115 */ 'a', 'd', 'd', 'i', 's', 32, 0,
|
|
/* 9122 */ 'l', 'i', 's', 32, 0,
|
|
/* 9127 */ 'x', 'o', 'r', 'i', 's', 32, 0,
|
|
/* 9134 */ 'e', 'v', 's', 'r', 'w', 'i', 's', 32, 0,
|
|
/* 9143 */ 'i', 'c', 'b', 't', 'l', 's', 32, 0,
|
|
/* 9151 */ 'q', 'v', 'f', 'm', 'u', 'l', 's', 32, 0,
|
|
/* 9160 */ 'q', 'v', 'f', 'x', 'm', 'u', 'l', 's', 32, 0,
|
|
/* 9170 */ 'e', 'v', 'l', 'w', 'h', 'o', 's', 32, 0,
|
|
/* 9179 */ 'v', 'p', 'k', 's', 'd', 's', 's', 32, 0,
|
|
/* 9188 */ 'v', 'p', 'k', 's', 'h', 's', 's', 32, 0,
|
|
/* 9197 */ 'v', 'p', 'k', 's', 'w', 's', 's', 32, 0,
|
|
/* 9206 */ 'e', 'v', 'c', 'm', 'p', 'g', 't', 's', 32, 0,
|
|
/* 9216 */ 'e', 'v', 'c', 'm', 'p', 'l', 't', 's', 32, 0,
|
|
/* 9226 */ 'f', 's', 'q', 'r', 't', 's', 32, 0,
|
|
/* 9234 */ 'q', 'v', 'f', 'c', 'f', 'i', 'd', 'u', 's', 32, 0,
|
|
/* 9245 */ 'v', 'p', 'k', 's', 'd', 'u', 's', 32, 0,
|
|
/* 9254 */ 'v', 'p', 'k', 'u', 'd', 'u', 's', 32, 0,
|
|
/* 9263 */ 'v', 'p', 'k', 's', 'h', 'u', 's', 32, 0,
|
|
/* 9272 */ 'v', 'p', 'k', 'u', 'h', 'u', 's', 32, 0,
|
|
/* 9281 */ 'v', 'p', 'k', 's', 'w', 'u', 's', 32, 0,
|
|
/* 9290 */ 'v', 'p', 'k', 'u', 'w', 'u', 's', 32, 0,
|
|
/* 9299 */ 'f', 'd', 'i', 'v', 's', 32, 0,
|
|
/* 9306 */ 'e', 'v', 's', 'r', 'w', 's', 32, 0,
|
|
/* 9314 */ 'm', 't', 'v', 's', 'r', 'w', 's', 32, 0,
|
|
/* 9323 */ 'v', 's', 'u', 'm', '2', 's', 'w', 's', 32, 0,
|
|
/* 9333 */ 'v', 's', 'u', 'b', 's', 'w', 's', 32, 0,
|
|
/* 9342 */ 'v', 'a', 'd', 'd', 's', 'w', 's', 32, 0,
|
|
/* 9351 */ 'v', 's', 'u', 'm', 's', 'w', 's', 32, 0,
|
|
/* 9360 */ 'v', 's', 'u', 'b', 'u', 'w', 's', 32, 0,
|
|
/* 9369 */ 'v', 'a', 'd', 'd', 'u', 'w', 's', 32, 0,
|
|
/* 9378 */ 'e', 'v', 'd', 'i', 'v', 'w', 's', 32, 0,
|
|
/* 9387 */ 'x', 's', 'c', 'v', 'd', 'p', 's', 'x', 'w', 's', 32, 0,
|
|
/* 9399 */ 'x', 'v', 'c', 'v', 'd', 'p', 's', 'x', 'w', 's', 32, 0,
|
|
/* 9411 */ 'x', 'v', 'c', 'v', 's', 'p', 's', 'x', 'w', 's', 32, 0,
|
|
/* 9423 */ 'x', 's', 'c', 'v', 'd', 'p', 'u', 'x', 'w', 's', 32, 0,
|
|
/* 9435 */ 'x', 'v', 'c', 'v', 'd', 'p', 'u', 'x', 'w', 's', 32, 0,
|
|
/* 9447 */ 'x', 'v', 'c', 'v', 's', 'p', 'u', 'x', 'w', 's', 32, 0,
|
|
/* 9459 */ 'v', 'c', 't', 's', 'x', 's', 32, 0,
|
|
/* 9467 */ 'v', 'c', 't', 'u', 'x', 's', 32, 0,
|
|
/* 9475 */ 'l', 'd', 'a', 't', 32, 0,
|
|
/* 9481 */ 's', 't', 'd', 'a', 't', 32, 0,
|
|
/* 9488 */ 'e', 'v', 'l', 'h', 'h', 'e', 's', 'p', 'l', 'a', 't', 32, 0,
|
|
/* 9501 */ 'e', 'v', 'l', 'w', 'h', 's', 'p', 'l', 'a', 't', 32, 0,
|
|
/* 9513 */ 'e', 'v', 'l', 'h', 'h', 'o', 's', 's', 'p', 'l', 'a', 't', 32, 0,
|
|
/* 9527 */ 'e', 'v', 'l', 'h', 'h', 'o', 'u', 's', 'p', 'l', 'a', 't', 32, 0,
|
|
/* 9541 */ 'e', 'v', 'l', 'w', 'w', 's', 'p', 'l', 'a', 't', 32, 0,
|
|
/* 9553 */ 'l', 'w', 'a', 't', 32, 0,
|
|
/* 9559 */ 's', 't', 'w', 'a', 't', 32, 0,
|
|
/* 9566 */ 'd', 'c', 'b', 't', 32, 0,
|
|
/* 9572 */ 'i', 'c', 'b', 't', 32, 0,
|
|
/* 9578 */ 'd', 'c', 'b', 't', 'c', 't', 32, 0,
|
|
/* 9586 */ 'd', 'c', 'b', 't', 's', 't', 'c', 't', 32, 0,
|
|
/* 9596 */ 'e', 'f', 'd', 'c', 'm', 'p', 'g', 't', 32, 0,
|
|
/* 9606 */ 'q', 'v', 'f', 'c', 'm', 'p', 'g', 't', 32, 0,
|
|
/* 9616 */ 'e', 'f', 's', 'c', 'm', 'p', 'g', 't', 32, 0,
|
|
/* 9626 */ 'e', 'v', 'f', 's', 'c', 'm', 'p', 'g', 't', 32, 0,
|
|
/* 9637 */ 'e', 'f', 'd', 't', 's', 't', 'g', 't', 32, 0,
|
|
/* 9647 */ 'e', 'f', 's', 't', 's', 't', 'g', 't', 32, 0,
|
|
/* 9657 */ 'e', 'v', 'f', 's', 't', 's', 't', 'g', 't', 32, 0,
|
|
/* 9668 */ 'w', 'a', 'i', 't', 32, 0,
|
|
/* 9674 */ 'e', 'f', 'd', 'c', 'm', 'p', 'l', 't', 32, 0,
|
|
/* 9684 */ 'q', 'v', 'f', 'c', 'm', 'p', 'l', 't', 32, 0,
|
|
/* 9694 */ 'e', 'f', 's', 'c', 'm', 'p', 'l', 't', 32, 0,
|
|
/* 9704 */ 'e', 'v', 'f', 's', 'c', 'm', 'p', 'l', 't', 32, 0,
|
|
/* 9715 */ 'e', 'f', 'd', 't', 's', 't', 'l', 't', 32, 0,
|
|
/* 9725 */ 'e', 'f', 's', 't', 's', 't', 'l', 't', 32, 0,
|
|
/* 9735 */ 'e', 'v', 'f', 's', 't', 's', 't', 'l', 't', 32, 0,
|
|
/* 9746 */ 'f', 's', 'q', 'r', 't', 32, 0,
|
|
/* 9753 */ 'f', 't', 's', 'q', 'r', 't', 32, 0,
|
|
/* 9761 */ 'p', 'a', 's', 't', 'e', '_', 'l', 'a', 's', 't', 32, 0,
|
|
/* 9773 */ 'v', 'n', 'c', 'i', 'p', 'h', 'e', 'r', 'l', 'a', 's', 't', 32, 0,
|
|
/* 9787 */ 'v', 'c', 'i', 'p', 'h', 'e', 'r', 'l', 'a', 's', 't', 32, 0,
|
|
/* 9800 */ 'd', 'c', 'b', 's', 't', 32, 0,
|
|
/* 9807 */ 'd', 's', 't', 32, 0,
|
|
/* 9812 */ 'c', 'o', 'p', 'y', '_', 'f', 'i', 'r', 's', 't', 32, 0,
|
|
/* 9824 */ 'd', 'c', 'b', 't', 's', 't', 32, 0,
|
|
/* 9832 */ 'd', 's', 't', 's', 't', 32, 0,
|
|
/* 9839 */ 'd', 'c', 'b', 't', 't', 32, 0,
|
|
/* 9846 */ 'd', 's', 't', 't', 32, 0,
|
|
/* 9852 */ 'd', 'c', 'b', 't', 's', 't', 't', 32, 0,
|
|
/* 9861 */ 'd', 's', 't', 's', 't', 't', 32, 0,
|
|
/* 9869 */ 'l', 'h', 'a', 'u', 32, 0,
|
|
/* 9875 */ 's', 't', 'b', 'u', 32, 0,
|
|
/* 9881 */ 'l', 'f', 'd', 'u', 32, 0,
|
|
/* 9887 */ 's', 't', 'f', 'd', 'u', 32, 0,
|
|
/* 9894 */ 'm', 'a', 'd', 'd', 'h', 'd', 'u', 32, 0,
|
|
/* 9903 */ 'm', 'u', 'l', 'h', 'd', 'u', 32, 0,
|
|
/* 9911 */ 'q', 'v', 'f', 'c', 'f', 'i', 'd', 'u', 32, 0,
|
|
/* 9921 */ 'q', 'v', 'f', 'c', 't', 'i', 'd', 'u', 32, 0,
|
|
/* 9931 */ 'l', 'd', 'u', 32, 0,
|
|
/* 9936 */ 's', 't', 'd', 'u', 32, 0,
|
|
/* 9942 */ 'd', 'i', 'v', 'd', 'u', 32, 0,
|
|
/* 9949 */ 'd', 'i', 'v', 'd', 'e', 'u', 32, 0,
|
|
/* 9957 */ 'd', 'i', 'v', 'w', 'e', 'u', 32, 0,
|
|
/* 9965 */ 's', 't', 'h', 'u', 32, 0,
|
|
/* 9971 */ 'e', 'v', 's', 'r', 'w', 'i', 'u', 32, 0,
|
|
/* 9980 */ 'e', 'v', 'l', 'w', 'h', 'o', 'u', 32, 0,
|
|
/* 9989 */ 'f', 'c', 'm', 'p', 'u', 32, 0,
|
|
/* 9996 */ 'l', 'f', 's', 'u', 32, 0,
|
|
/* 10002 */ 's', 't', 'f', 's', 'u', 32, 0,
|
|
/* 10009 */ 'e', 'v', 'c', 'm', 'p', 'g', 't', 'u', 32, 0,
|
|
/* 10019 */ 'e', 'v', 'c', 'm', 'p', 'l', 't', 'u', 32, 0,
|
|
/* 10029 */ 'm', 'u', 'l', 'h', 'w', 'u', 32, 0,
|
|
/* 10037 */ 'q', 'v', 'f', 'c', 't', 'i', 'w', 'u', 32, 0,
|
|
/* 10047 */ 'e', 'v', 's', 'r', 'w', 'u', 32, 0,
|
|
/* 10055 */ 's', 't', 'w', 'u', 32, 0,
|
|
/* 10061 */ 'e', 'v', 'd', 'i', 'v', 'w', 'u', 32, 0,
|
|
/* 10070 */ 'l', 'b', 'z', 'u', 32, 0,
|
|
/* 10076 */ 'l', 'h', 'z', 'u', 32, 0,
|
|
/* 10082 */ 'l', 'w', 'z', 'u', 32, 0,
|
|
/* 10088 */ 's', 'l', 'b', 'm', 'f', 'e', 'v', 32, 0,
|
|
/* 10097 */ 'e', 'f', 'd', 'd', 'i', 'v', 32, 0,
|
|
/* 10105 */ 'f', 'd', 'i', 'v', 32, 0,
|
|
/* 10111 */ 'e', 'f', 's', 'd', 'i', 'v', 32, 0,
|
|
/* 10119 */ 'e', 'v', 'f', 's', 'd', 'i', 'v', 32, 0,
|
|
/* 10128 */ 'f', 't', 'd', 'i', 'v', 32, 0,
|
|
/* 10135 */ 'v', 's', 'l', 'v', 32, 0,
|
|
/* 10141 */ 'x', 'x', 'l', 'e', 'q', 'v', 32, 0,
|
|
/* 10149 */ 'c', 'r', 'e', 'q', 'v', 32, 0,
|
|
/* 10156 */ 'e', 'v', 'e', 'q', 'v', 32, 0,
|
|
/* 10163 */ 'v', 's', 'r', 'v', 32, 0,
|
|
/* 10169 */ 'l', 'x', 'v', 32, 0,
|
|
/* 10174 */ 's', 't', 'x', 'v', 32, 0,
|
|
/* 10180 */ 'v', 'e', 'x', 't', 's', 'b', '2', 'w', 32, 0,
|
|
/* 10190 */ 'v', 'e', 'x', 't', 's', 'h', '2', 'w', 32, 0,
|
|
/* 10200 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'f', 'a', 'a', 'w', 32, 0,
|
|
/* 10213 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'f', 'a', 'a', 'w', 32, 0,
|
|
/* 10226 */ 'e', 'v', 'm', 'h', 'e', 's', 's', 'f', 'a', 'a', 'w', 32, 0,
|
|
/* 10239 */ 'e', 'v', 'm', 'h', 'o', 's', 's', 'f', 'a', 'a', 'w', 32, 0,
|
|
/* 10252 */ 'e', 'v', 'a', 'd', 'd', 's', 'm', 'i', 'a', 'a', 'w', 32, 0,
|
|
/* 10265 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'i', 'a', 'a', 'w', 32, 0,
|
|
/* 10278 */ 'e', 'v', 's', 'u', 'b', 'f', 's', 'm', 'i', 'a', 'a', 'w', 32, 0,
|
|
/* 10292 */ 'e', 'v', 'm', 'w', 'l', 's', 'm', 'i', 'a', 'a', 'w', 32, 0,
|
|
/* 10305 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'i', 'a', 'a', 'w', 32, 0,
|
|
/* 10318 */ 'e', 'v', 'a', 'd', 'd', 'u', 'm', 'i', 'a', 'a', 'w', 32, 0,
|
|
/* 10331 */ 'e', 'v', 'm', 'h', 'e', 'u', 'm', 'i', 'a', 'a', 'w', 32, 0,
|
|
/* 10344 */ 'e', 'v', 's', 'u', 'b', 'f', 'u', 'm', 'i', 'a', 'a', 'w', 32, 0,
|
|
/* 10358 */ 'e', 'v', 'm', 'w', 'l', 'u', 'm', 'i', 'a', 'a', 'w', 32, 0,
|
|
/* 10371 */ 'e', 'v', 'm', 'h', 'o', 'u', 'm', 'i', 'a', 'a', 'w', 32, 0,
|
|
/* 10384 */ 'e', 'v', 'a', 'd', 'd', 's', 's', 'i', 'a', 'a', 'w', 32, 0,
|
|
/* 10397 */ 'e', 'v', 'm', 'h', 'e', 's', 's', 'i', 'a', 'a', 'w', 32, 0,
|
|
/* 10410 */ 'e', 'v', 's', 'u', 'b', 'f', 's', 's', 'i', 'a', 'a', 'w', 32, 0,
|
|
/* 10424 */ 'e', 'v', 'm', 'w', 'l', 's', 's', 'i', 'a', 'a', 'w', 32, 0,
|
|
/* 10437 */ 'e', 'v', 'm', 'h', 'o', 's', 's', 'i', 'a', 'a', 'w', 32, 0,
|
|
/* 10450 */ 'e', 'v', 'a', 'd', 'd', 'u', 's', 'i', 'a', 'a', 'w', 32, 0,
|
|
/* 10463 */ 'e', 'v', 'm', 'h', 'e', 'u', 's', 'i', 'a', 'a', 'w', 32, 0,
|
|
/* 10476 */ 'e', 'v', 's', 'u', 'b', 'f', 'u', 's', 'i', 'a', 'a', 'w', 32, 0,
|
|
/* 10490 */ 'e', 'v', 'm', 'w', 'l', 'u', 's', 'i', 'a', 'a', 'w', 32, 0,
|
|
/* 10503 */ 'e', 'v', 'm', 'h', 'o', 'u', 's', 'i', 'a', 'a', 'w', 32, 0,
|
|
/* 10516 */ 'v', 's', 'h', 'a', 's', 'i', 'g', 'm', 'a', 'w', 32, 0,
|
|
/* 10528 */ 'v', 's', 'r', 'a', 'w', 32, 0,
|
|
/* 10535 */ 'v', 'p', 'r', 't', 'y', 'b', 'w', 32, 0,
|
|
/* 10544 */ 'e', 'v', 'a', 'd', 'd', 'w', 32, 0,
|
|
/* 10552 */ 'e', 'v', 'l', 'd', 'w', 32, 0,
|
|
/* 10559 */ 'e', 'v', 'r', 'n', 'd', 'w', 32, 0,
|
|
/* 10567 */ 'e', 'v', 's', 't', 'd', 'w', 32, 0,
|
|
/* 10575 */ 'v', 'm', 'r', 'g', 'e', 'w', 32, 0,
|
|
/* 10583 */ 'v', 'c', 'm', 'p', 'n', 'e', 'w', 32, 0,
|
|
/* 10592 */ 'e', 'v', 's', 'u', 'b', 'f', 'w', 32, 0,
|
|
/* 10601 */ 'e', 'v', 's', 'u', 'b', 'i', 'f', 'w', 32, 0,
|
|
/* 10611 */ 'v', 'n', 'e', 'g', 'w', 32, 0,
|
|
/* 10618 */ 'v', 'm', 'r', 'g', 'h', 'w', 32, 0,
|
|
/* 10626 */ 'x', 'x', 'm', 'r', 'g', 'h', 'w', 32, 0,
|
|
/* 10635 */ 'm', 'u', 'l', 'h', 'w', 32, 0,
|
|
/* 10642 */ 'e', 'v', 'a', 'd', 'd', 'i', 'w', 32, 0,
|
|
/* 10651 */ 'q', 'v', 'f', 'c', 't', 'i', 'w', 32, 0,
|
|
/* 10660 */ 'v', 'm', 'r', 'g', 'l', 'w', 32, 0,
|
|
/* 10668 */ 'x', 'x', 'm', 'r', 'g', 'l', 'w', 32, 0,
|
|
/* 10677 */ 'm', 'u', 'l', 'l', 'w', 32, 0,
|
|
/* 10684 */ 'c', 'm', 'p', 'l', 'w', 32, 0,
|
|
/* 10691 */ 'e', 'v', 'r', 'l', 'w', 32, 0,
|
|
/* 10698 */ 'e', 'v', 's', 'l', 'w', 32, 0,
|
|
/* 10705 */ 'l', 'm', 'w', 32, 0,
|
|
/* 10710 */ 's', 't', 'm', 'w', 32, 0,
|
|
/* 10716 */ 'v', 'p', 'm', 's', 'u', 'm', 'w', 32, 0,
|
|
/* 10725 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'f', 'a', 'n', 'w', 32, 0,
|
|
/* 10738 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'f', 'a', 'n', 'w', 32, 0,
|
|
/* 10751 */ 'e', 'v', 'm', 'h', 'e', 's', 's', 'f', 'a', 'n', 'w', 32, 0,
|
|
/* 10764 */ 'e', 'v', 'm', 'h', 'o', 's', 's', 'f', 'a', 'n', 'w', 32, 0,
|
|
/* 10777 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'i', 'a', 'n', 'w', 32, 0,
|
|
/* 10790 */ 'e', 'v', 'm', 'w', 'l', 's', 'm', 'i', 'a', 'n', 'w', 32, 0,
|
|
/* 10803 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'i', 'a', 'n', 'w', 32, 0,
|
|
/* 10816 */ 'e', 'v', 'm', 'h', 'e', 'u', 'm', 'i', 'a', 'n', 'w', 32, 0,
|
|
/* 10829 */ 'e', 'v', 'm', 'w', 'l', 'u', 'm', 'i', 'a', 'n', 'w', 32, 0,
|
|
/* 10842 */ 'e', 'v', 'm', 'h', 'o', 'u', 'm', 'i', 'a', 'n', 'w', 32, 0,
|
|
/* 10855 */ 'e', 'v', 'm', 'h', 'e', 's', 's', 'i', 'a', 'n', 'w', 32, 0,
|
|
/* 10868 */ 'e', 'v', 'm', 'w', 'l', 's', 's', 'i', 'a', 'n', 'w', 32, 0,
|
|
/* 10881 */ 'e', 'v', 'm', 'h', 'o', 's', 's', 'i', 'a', 'n', 'w', 32, 0,
|
|
/* 10894 */ 'e', 'v', 'm', 'h', 'e', 'u', 's', 'i', 'a', 'n', 'w', 32, 0,
|
|
/* 10907 */ 'e', 'v', 'm', 'w', 'l', 'u', 's', 'i', 'a', 'n', 'w', 32, 0,
|
|
/* 10920 */ 'e', 'v', 'm', 'h', 'o', 'u', 's', 'i', 'a', 'n', 'w', 32, 0,
|
|
/* 10933 */ 'v', 'm', 'r', 'g', 'o', 'w', 32, 0,
|
|
/* 10941 */ 'c', 'm', 'p', 'w', 32, 0,
|
|
/* 10947 */ 'x', 'x', 'b', 'r', 'w', 32, 0,
|
|
/* 10954 */ 'v', 's', 'r', 'w', 32, 0,
|
|
/* 10960 */ 'm', 'o', 'd', 's', 'w', 32, 0,
|
|
/* 10967 */ 'v', 'm', 'u', 'l', 'e', 's', 'w', 32, 0,
|
|
/* 10976 */ 'v', 'a', 'v', 'g', 's', 'w', 32, 0,
|
|
/* 10984 */ 'v', 'u', 'p', 'k', 'h', 's', 'w', 32, 0,
|
|
/* 10993 */ 'v', 's', 'p', 'l', 't', 'i', 's', 'w', 32, 0,
|
|
/* 11003 */ 'v', 'u', 'p', 'k', 'l', 's', 'w', 32, 0,
|
|
/* 11012 */ 'e', 'v', 'c', 'n', 't', 'l', 's', 'w', 32, 0,
|
|
/* 11022 */ 'v', 'm', 'i', 'n', 's', 'w', 32, 0,
|
|
/* 11030 */ 'v', 'm', 'u', 'l', 'o', 's', 'w', 32, 0,
|
|
/* 11039 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'w', 32, 0,
|
|
/* 11049 */ 'e', 'x', 't', 's', 'w', 32, 0,
|
|
/* 11056 */ 'v', 'm', 'a', 'x', 's', 'w', 32, 0,
|
|
/* 11064 */ 'v', 's', 'p', 'l', 't', 'w', 32, 0,
|
|
/* 11072 */ 'x', 'x', 's', 'p', 'l', 't', 'w', 32, 0,
|
|
/* 11081 */ 'v', 'p', 'o', 'p', 'c', 'n', 't', 'w', 32, 0,
|
|
/* 11091 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'w', 32, 0,
|
|
/* 11101 */ 'x', 'x', 'i', 'n', 's', 'e', 'r', 't', 'w', 32, 0,
|
|
/* 11112 */ 's', 't', 'w', 32, 0,
|
|
/* 11117 */ 'v', 's', 'u', 'b', 'c', 'u', 'w', 32, 0,
|
|
/* 11126 */ 'v', 'a', 'd', 'd', 'c', 'u', 'w', 32, 0,
|
|
/* 11135 */ 'm', 'o', 'd', 'u', 'w', 32, 0,
|
|
/* 11142 */ 'v', 'a', 'b', 's', 'd', 'u', 'w', 32, 0,
|
|
/* 11151 */ 'v', 'm', 'u', 'l', 'e', 'u', 'w', 32, 0,
|
|
/* 11160 */ 'v', 'a', 'v', 'g', 'u', 'w', 32, 0,
|
|
/* 11168 */ 'v', 'm', 'i', 'n', 'u', 'w', 32, 0,
|
|
/* 11176 */ 'v', 'm', 'u', 'l', 'o', 'u', 'w', 32, 0,
|
|
/* 11185 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'w', 32, 0,
|
|
/* 11195 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'u', 'w', 32, 0,
|
|
/* 11207 */ 'x', 'x', 'e', 'x', 't', 'r', 'a', 'c', 't', 'u', 'w', 32, 0,
|
|
/* 11220 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'w', 32, 0,
|
|
/* 11230 */ 'v', 'm', 'a', 'x', 'u', 'w', 32, 0,
|
|
/* 11238 */ 'd', 'i', 'v', 'w', 32, 0,
|
|
/* 11244 */ 'v', 'c', 'm', 'p', 'n', 'e', 'z', 'w', 32, 0,
|
|
/* 11254 */ 'v', 'c', 'l', 'z', 'w', 32, 0,
|
|
/* 11261 */ 'e', 'v', 'c', 'n', 't', 'l', 'z', 'w', 32, 0,
|
|
/* 11271 */ 'v', 'c', 't', 'z', 'w', 32, 0,
|
|
/* 11278 */ 'c', 'n', 't', 't', 'z', 'w', 32, 0,
|
|
/* 11286 */ 'l', 'x', 'v', 'd', '2', 'x', 32, 0,
|
|
/* 11294 */ 's', 't', 'x', 'v', 'd', '2', 'x', 32, 0,
|
|
/* 11303 */ 'l', 'x', 'v', 'w', '4', 'x', 32, 0,
|
|
/* 11311 */ 's', 't', 'x', 'v', 'w', '4', 'x', 32, 0,
|
|
/* 11320 */ 'l', 'x', 'v', 'b', '1', '6', 'x', 32, 0,
|
|
/* 11329 */ 's', 't', 'x', 'v', 'b', '1', '6', 'x', 32, 0,
|
|
/* 11339 */ 'l', 'x', 'v', 'h', '8', 'x', 32, 0,
|
|
/* 11347 */ 's', 't', 'x', 'v', 'h', '8', 'x', 32, 0,
|
|
/* 11356 */ 'l', 'h', 'a', 'x', 32, 0,
|
|
/* 11362 */ 't', 'l', 'b', 'i', 'v', 'a', 'x', 32, 0,
|
|
/* 11371 */ 'q', 'v', 'l', 'f', 'i', 'w', 'a', 'x', 32, 0,
|
|
/* 11381 */ 'l', 'x', 's', 'i', 'w', 'a', 'x', 32, 0,
|
|
/* 11390 */ 'l', 'w', 'a', 'x', 32, 0,
|
|
/* 11396 */ 'l', 'v', 'e', 'b', 'x', 32, 0,
|
|
/* 11403 */ 's', 't', 'v', 'e', 'b', 'x', 32, 0,
|
|
/* 11411 */ 's', 't', 'x', 's', 'i', 'b', 'x', 32, 0,
|
|
/* 11420 */ 's', 't', 'b', 'x', 32, 0,
|
|
/* 11426 */ 'q', 'v', 'l', 'f', 'c', 'd', 'x', 32, 0,
|
|
/* 11435 */ 'q', 'v', 's', 't', 'f', 'c', 'd', 'x', 32, 0,
|
|
/* 11445 */ 'e', 'v', 'l', 'd', 'd', 'x', 32, 0,
|
|
/* 11453 */ 'e', 'v', 's', 't', 'd', 'd', 'x', 32, 0,
|
|
/* 11462 */ 'q', 'v', 'l', 'f', 'd', 'x', 32, 0,
|
|
/* 11470 */ 'q', 'v', 's', 't', 'f', 'd', 'x', 32, 0,
|
|
/* 11479 */ 'q', 'v', 'l', 'p', 'c', 'l', 'd', 'x', 32, 0,
|
|
/* 11489 */ 'q', 'v', 'l', 'p', 'c', 'r', 'd', 'x', 32, 0,
|
|
/* 11499 */ 'l', 'x', 's', 'd', 'x', 32, 0,
|
|
/* 11506 */ 's', 't', 'x', 's', 'd', 'x', 32, 0,
|
|
/* 11514 */ 's', 't', 'd', 'x', 32, 0,
|
|
/* 11520 */ 'e', 'v', 'l', 'w', 'h', 'e', 'x', 32, 0,
|
|
/* 11529 */ 'e', 'v', 's', 't', 'w', 'h', 'e', 'x', 32, 0,
|
|
/* 11539 */ 'e', 'v', 's', 't', 'w', 'w', 'e', 'x', 32, 0,
|
|
/* 11549 */ 'e', 'v', 'l', 'd', 'h', 'x', 32, 0,
|
|
/* 11557 */ 'e', 'v', 's', 't', 'd', 'h', 'x', 32, 0,
|
|
/* 11566 */ 'l', 'v', 'e', 'h', 'x', 32, 0,
|
|
/* 11573 */ 's', 't', 'v', 'e', 'h', 'x', 32, 0,
|
|
/* 11581 */ 's', 't', 'x', 's', 'i', 'h', 'x', 32, 0,
|
|
/* 11590 */ 's', 't', 'h', 'x', 32, 0,
|
|
/* 11596 */ 's', 't', 'b', 'c', 'i', 'x', 32, 0,
|
|
/* 11604 */ 'l', 'd', 'c', 'i', 'x', 32, 0,
|
|
/* 11611 */ 's', 't', 'd', 'c', 'i', 'x', 32, 0,
|
|
/* 11619 */ 's', 't', 'h', 'c', 'i', 'x', 32, 0,
|
|
/* 11627 */ 's', 't', 'w', 'c', 'i', 'x', 32, 0,
|
|
/* 11635 */ 'l', 'b', 'z', 'c', 'i', 'x', 32, 0,
|
|
/* 11643 */ 'l', 'h', 'z', 'c', 'i', 'x', 32, 0,
|
|
/* 11651 */ 'l', 'w', 'z', 'c', 'i', 'x', 32, 0,
|
|
/* 11659 */ 'x', 's', 'r', 'q', 'p', 'i', 'x', 32, 0,
|
|
/* 11668 */ 'v', 'e', 'x', 't', 'u', 'b', 'l', 'x', 32, 0,
|
|
/* 11678 */ 'v', 'e', 'x', 't', 'u', 'h', 'l', 'x', 32, 0,
|
|
/* 11688 */ 'v', 'e', 'x', 't', 'u', 'w', 'l', 'x', 32, 0,
|
|
/* 11698 */ 'l', 'd', 'm', 'x', 32, 0,
|
|
/* 11704 */ 'v', 's', 'b', 'o', 'x', 32, 0,
|
|
/* 11711 */ 'e', 'v', 's', 't', 'w', 'h', 'o', 'x', 32, 0,
|
|
/* 11721 */ 'e', 'v', 's', 't', 'w', 'w', 'o', 'x', 32, 0,
|
|
/* 11731 */ 'l', 'b', 'e', 'p', 'x', 32, 0,
|
|
/* 11738 */ 's', 't', 'b', 'e', 'p', 'x', 32, 0,
|
|
/* 11746 */ 'l', 'f', 'd', 'e', 'p', 'x', 32, 0,
|
|
/* 11754 */ 's', 't', 'f', 'd', 'e', 'p', 'x', 32, 0,
|
|
/* 11763 */ 'l', 'h', 'e', 'p', 'x', 32, 0,
|
|
/* 11770 */ 's', 't', 'h', 'e', 'p', 'x', 32, 0,
|
|
/* 11778 */ 'l', 'w', 'e', 'p', 'x', 32, 0,
|
|
/* 11785 */ 's', 't', 'w', 'e', 'p', 'x', 32, 0,
|
|
/* 11793 */ 'v', 'u', 'p', 'k', 'h', 'p', 'x', 32, 0,
|
|
/* 11802 */ 'v', 'p', 'k', 'p', 'x', 32, 0,
|
|
/* 11809 */ 'v', 'u', 'p', 'k', 'l', 'p', 'x', 32, 0,
|
|
/* 11818 */ 'l', 'x', 's', 's', 'p', 'x', 32, 0,
|
|
/* 11826 */ 's', 't', 'x', 's', 's', 'p', 'x', 32, 0,
|
|
/* 11835 */ 'l', 'b', 'a', 'r', 'x', 32, 0,
|
|
/* 11842 */ 'l', 'd', 'a', 'r', 'x', 32, 0,
|
|
/* 11849 */ 'l', 'h', 'a', 'r', 'x', 32, 0,
|
|
/* 11856 */ 'l', 'w', 'a', 'r', 'x', 32, 0,
|
|
/* 11863 */ 'l', 'd', 'b', 'r', 'x', 32, 0,
|
|
/* 11870 */ 's', 't', 'd', 'b', 'r', 'x', 32, 0,
|
|
/* 11878 */ 'l', 'h', 'b', 'r', 'x', 32, 0,
|
|
/* 11885 */ 's', 't', 'h', 'b', 'r', 'x', 32, 0,
|
|
/* 11893 */ 'v', 'e', 'x', 't', 'u', 'b', 'r', 'x', 32, 0,
|
|
/* 11903 */ 'l', 'w', 'b', 'r', 'x', 32, 0,
|
|
/* 11910 */ 's', 't', 'w', 'b', 'r', 'x', 32, 0,
|
|
/* 11918 */ 'v', 'e', 'x', 't', 'u', 'h', 'r', 'x', 32, 0,
|
|
/* 11928 */ 'v', 'e', 'x', 't', 'u', 'w', 'r', 'x', 32, 0,
|
|
/* 11938 */ 'm', 'c', 'r', 'x', 'r', 'x', 32, 0,
|
|
/* 11946 */ 't', 'l', 'b', 's', 'x', 32, 0,
|
|
/* 11953 */ 'q', 'v', 'l', 'f', 'c', 's', 'x', 32, 0,
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/* 11962 */ 'q', 'v', 's', 't', 'f', 'c', 's', 'x', 32, 0,
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/* 11972 */ 'l', 'x', 'v', 'd', 's', 'x', 32, 0,
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/* 11980 */ 'v', 'c', 'f', 's', 'x', 32, 0,
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/* 11987 */ 'q', 'v', 'l', 'f', 's', 'x', 32, 0,
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/* 11995 */ 'q', 'v', 's', 't', 'f', 's', 'x', 32, 0,
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/* 12004 */ 'q', 'v', 'l', 'p', 'c', 'l', 's', 'x', 32, 0,
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/* 12014 */ 'e', 'v', 'l', 'w', 'h', 'o', 's', 'x', 32, 0,
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/* 12024 */ 'q', 'v', 'l', 'p', 'c', 'r', 's', 'x', 32, 0,
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/* 12034 */ 'l', 'x', 'v', 'w', 's', 'x', 32, 0,
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/* 12042 */ 'e', 'v', 'l', 'h', 'h', 'e', 's', 'p', 'l', 'a', 't', 'x', 32, 0,
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/* 12056 */ 'e', 'v', 'l', 'w', 'h', 's', 'p', 'l', 'a', 't', 'x', 32, 0,
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/* 12099 */ 'e', 'v', 'l', 'w', 'w', 's', 'p', 'l', 'a', 't', 'x', 32, 0,
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/* 12112 */ 'l', 'h', 'a', 'u', 'x', 32, 0,
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/* 12119 */ 'l', 'w', 'a', 'u', 'x', 32, 0,
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/* 12126 */ 's', 't', 'b', 'u', 'x', 32, 0,
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/* 12133 */ 'q', 'v', 'l', 'f', 'c', 'd', 'u', 'x', 32, 0,
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/* 12143 */ 'q', 'v', 's', 't', 'f', 'c', 'd', 'u', 'x', 32, 0,
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/* 12154 */ 'q', 'v', 'l', 'f', 'd', 'u', 'x', 32, 0,
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/* 12163 */ 'q', 'v', 's', 't', 'f', 'd', 'u', 'x', 32, 0,
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/* 12173 */ 'l', 'd', 'u', 'x', 32, 0,
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/* 12179 */ 's', 't', 'd', 'u', 'x', 32, 0,
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/* 12186 */ 'v', 'c', 'f', 'u', 'x', 32, 0,
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/* 12193 */ 's', 't', 'h', 'u', 'x', 32, 0,
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/* 12200 */ 'e', 'v', 'l', 'w', 'h', 'o', 'u', 'x', 32, 0,
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/* 12210 */ 'q', 'v', 'l', 'f', 'c', 's', 'u', 'x', 32, 0,
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/* 12220 */ 'q', 'v', 's', 't', 'f', 'c', 's', 'u', 'x', 32, 0,
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/* 12231 */ 'q', 'v', 'l', 'f', 's', 'u', 'x', 32, 0,
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/* 12240 */ 'q', 'v', 's', 't', 'f', 's', 'u', 'x', 32, 0,
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/* 12250 */ 's', 't', 'w', 'u', 'x', 32, 0,
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/* 12257 */ 'l', 'b', 'z', 'u', 'x', 32, 0,
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/* 12264 */ 'l', 'h', 'z', 'u', 'x', 32, 0,
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/* 12271 */ 'l', 'w', 'z', 'u', 'x', 32, 0,
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/* 12278 */ 'l', 'v', 'x', 32, 0,
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/* 12283 */ 's', 't', 'v', 'x', 32, 0,
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/* 12289 */ 'l', 'x', 'v', 'x', 32, 0,
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/* 12295 */ 's', 't', 'x', 'v', 'x', 32, 0,
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/* 12302 */ 'e', 'v', 'l', 'd', 'w', 'x', 32, 0,
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/* 12310 */ 'e', 'v', 's', 't', 'd', 'w', 'x', 32, 0,
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/* 12319 */ 'l', 'v', 'e', 'w', 'x', 32, 0,
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/* 12326 */ 's', 't', 'v', 'e', 'w', 'x', 32, 0,
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/* 12334 */ 'q', 'v', 's', 't', 'f', 'i', 'w', 'x', 32, 0,
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/* 12344 */ 's', 't', 'x', 's', 'i', 'w', 'x', 32, 0,
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/* 12353 */ 's', 't', 'w', 'x', 32, 0,
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/* 12359 */ 'l', 'x', 's', 'i', 'b', 'z', 'x', 32, 0,
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/* 12368 */ 'l', 'b', 'z', 'x', 32, 0,
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/* 12374 */ 'l', 'x', 's', 'i', 'h', 'z', 'x', 32, 0,
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/* 12383 */ 'l', 'h', 'z', 'x', 32, 0,
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/* 12389 */ 'q', 'v', 'l', 'f', 'i', 'w', 'z', 'x', 32, 0,
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/* 12399 */ 'l', 'x', 's', 'i', 'w', 'z', 'x', 32, 0,
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/* 12408 */ 'l', 'w', 'z', 'x', 32, 0,
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/* 12414 */ 'c', 'o', 'p', 'y', 32, 0,
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/* 12420 */ 'd', 'c', 'b', 'z', 32, 0,
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/* 12426 */ 'l', 'b', 'z', 32, 0,
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/* 12431 */ 'b', 'd', 'z', 32, 0,
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/* 12436 */ 'e', 'f', 'd', 'c', 't', 's', 'i', 'd', 'z', 32, 0,
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/* 12447 */ 'q', 'v', 'f', 'c', 't', 'i', 'd', 'z', 32, 0,
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/* 12457 */ 'e', 'f', 'd', 'c', 't', 'u', 'i', 'd', 'z', 32, 0,
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/* 12468 */ 'x', 's', 'c', 'v', 'q', 'p', 's', 'd', 'z', 32, 0,
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/* 12479 */ 'x', 's', 'c', 'v', 'q', 'p', 'u', 'd', 'z', 32, 0,
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/* 12490 */ 'l', 'h', 'z', 32, 0,
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/* 12495 */ 'v', 'r', 'f', 'i', 'z', 32, 0,
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/* 12502 */ 'x', 's', 'r', 'd', 'p', 'i', 'z', 32, 0,
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/* 12511 */ 'x', 'v', 'r', 'd', 'p', 'i', 'z', 32, 0,
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/* 12520 */ 'x', 'v', 'r', 's', 'p', 'i', 'z', 32, 0,
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/* 12529 */ 'q', 'v', 'f', 'r', 'i', 'z', 32, 0,
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/* 12537 */ 'e', 'f', 'd', 'c', 't', 's', 'i', 'z', 32, 0,
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/* 12547 */ 'e', 'f', 's', 'c', 't', 's', 'i', 'z', 32, 0,
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/* 12557 */ 'e', 'v', 'f', 's', 'c', 't', 's', 'i', 'z', 32, 0,
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/* 12568 */ 'e', 'f', 'd', 'c', 't', 'u', 'i', 'z', 32, 0,
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/* 12578 */ 'e', 'f', 's', 'c', 't', 'u', 'i', 'z', 32, 0,
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/* 12588 */ 'b', 'd', 'n', 'z', 32, 0,
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/* 12594 */ 'q', 'v', 'f', 'c', 't', 'i', 'd', 'u', 'z', 32, 0,
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/* 12605 */ 'q', 'v', 'f', 'c', 't', 'i', 'w', 'u', 'z', 32, 0,
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/* 12616 */ 'q', 'v', 'f', 'c', 't', 'i', 'w', 'z', 32, 0,
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/* 12626 */ 'l', 'w', 'z', 32, 0,
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/* 12631 */ 'm', 'f', 'v', 's', 'r', 'w', 'z', 32, 0,
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/* 12640 */ 'm', 't', 'v', 's', 'r', 'w', 'z', 32, 0,
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/* 12649 */ 'x', 's', 'c', 'v', 'q', 'p', 's', 'w', 'z', 32, 0,
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/* 12660 */ 'x', 's', 'c', 'v', 'q', 'p', 'u', 'w', 'z', 32, 0,
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/* 12671 */ 'b', 'd', 'z', 'l', 'r', 'l', '+', 0,
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/* 12679 */ 'b', 'd', 'n', 'z', 'l', 'r', 'l', '+', 0,
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/* 12688 */ 'b', 'd', 'z', 'l', 'r', '+', 0,
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/* 12695 */ 'b', 'd', 'n', 'z', 'l', 'r', '+', 0,
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/* 12703 */ 'e', 'v', 's', 'e', 'l', 32, 'c', 'r', 'D', ',', 0,
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/* 12714 */ 'b', 'd', 'z', 'l', 'r', 'l', '-', 0,
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/* 12722 */ 'b', 'd', 'n', 'z', 'l', 'r', 'l', '-', 0,
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/* 12731 */ 'b', 'd', 'z', 'l', 'r', '-', 0,
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/* 12738 */ 'b', 'd', 'n', 'z', 'l', 'r', '-', 0,
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/* 12894 */ 't', 'r', 'e', 'c', 'h', 'k', 'p', 't', '.', 0,
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/* 12904 */ 'o', 'r', 'i', 32, '1', ',', 32, '1', ',', 32, '0', 0,
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/* 12916 */ 'o', 'r', 'i', 32, '2', ',', 32, '2', ',', 32, '0', 0,
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/* 12928 */ '#', 'A', 'D', 'D', 'I', 'S', 'd', 't', 'p', 'r', 'e', 'l', 'H', 'A', '3', '2', 0,
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/* 13073 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '3', '2', 0,
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/* 13333 */ '#', 'D', 'F', 'L', 'O', 'A', 'D', 'f', '3', '2', 0,
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/* 13344 */ '#', 'X', 'F', 'L', 'O', 'A', 'D', 'f', '3', '2', 0,
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/* 13355 */ '#', 'D', 'F', 'S', 'T', 'O', 'R', 'E', 'f', '3', '2', 0,
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/* 13367 */ '#', 'X', 'F', 'S', 'T', 'O', 'R', 'E', 'f', '3', '2', 0,
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/* 13627 */ '#', 'E', 'H', '_', 'S', 'J', 'L', 'J', '_', 'S', 'E', 'T', 'J', 'M', 'P', '6', '4', 0,
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/* 13645 */ '#', 'D', 'F', 'L', 'O', 'A', 'D', 'f', '6', '4', 0,
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/* 13656 */ '#', 'X', 'F', 'L', 'O', 'A', 'D', 'f', '6', '4', 0,
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/* 13667 */ '#', 'D', 'F', 'S', 'T', 'O', 'R', 'E', 'f', '6', '4', 0,
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/* 13679 */ '#', 'X', 'F', 'S', 'T', 'O', 'R', 'E', 'f', '6', '4', 0,
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/* 13712 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'S', 'P', 'E', '4', 0,
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/* 13728 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'S', 'P', 'E', '4', 0,
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/* 13741 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', '4', 0,
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/* 13755 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'F', '4', 0,
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/* 13766 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', '4', 0,
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/* 13780 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'I', '4', 0,
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/* 13791 */ 'c', 'r', 'x', 'o', 'r', 32, '6', ',', 32, '6', ',', 32, '6', 0,
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/* 13805 */ 'c', 'r', 'e', 'q', 'v', 32, '6', ',', 32, '6', ',', 32, '6', 0,
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/* 13819 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', '1', '6', 0,
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/* 13834 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'F', '1', '6', 0,
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/* 14086 */ '#', 'C', 'F', 'E', 'N', 'C', 'E', '8', 0,
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|
|
/* 14154 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '8', 0,
|
|
/* 14174 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '8', 0,
|
|
/* 14195 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '8', 0,
|
|
/* 14215 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'I', 'N', '_', 'I', '8', 0,
|
|
/* 14236 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'I', 'N', '_', 'I', '8', 0,
|
|
/* 14256 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '8', 0,
|
|
/* 14276 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '8', 0,
|
|
/* 14295 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '8', 0,
|
|
/* 14314 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'I', '8', 0,
|
|
/* 14325 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'A', 'X', '_', 'I', '8', 0,
|
|
/* 14346 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'A', 'X', '_', 'I', '8', 0,
|
|
/* 14366 */ '#', 'M', 'o', 'v', 'e', 'P', 'C', 't', 'o', 'L', 'R', '8', 0,
|
|
/* 14379 */ '#', 'D', 'Y', 'N', 'A', 'R', 'E', 'A', 'O', 'F', 'F', 'S', 'E', 'T', '8', 0,
|
|
/* 14395 */ '#', 'A', 'N', 'D', 'I', 'o', '_', '1', '_', 'E', 'Q', '_', 'B', 'I', 'T', '8', 0,
|
|
/* 14412 */ '#', 'A', 'N', 'D', 'I', 'o', '_', '1', '_', 'G', 'T', '_', 'B', 'I', 'T', '8', 0,
|
|
/* 14429 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'i', '8', 0,
|
|
/* 14445 */ '#', 'A', 'D', 'D', 'I', 'S', 't', 'o', 'c', 'H', 'A', 0,
|
|
/* 14457 */ '#', 'A', 'D', 'D', 'I', 'S', 't', 'l', 's', 'g', 'd', 'H', 'A', 0,
|
|
/* 14471 */ '#', 'A', 'D', 'D', 'I', 'S', 't', 'l', 's', 'l', 'd', 'H', 'A', 0,
|
|
/* 14485 */ '#', 'A', 'D', 'D', 'I', 'S', 'g', 'o', 't', 'T', 'p', 'r', 'e', 'l', 'H', 'A', 0,
|
|
/* 14502 */ '#', 'A', 'D', 'D', 'I', 'S', 'd', 't', 'p', 'r', 'e', 'l', 'H', 'A', 0,
|
|
/* 14517 */ '#', 'R', 'e', 'a', 'd', 'T', 'B', 0,
|
|
/* 14525 */ '#', 'D', 'Y', 'N', 'A', 'L', 'L', 'O', 'C', 0,
|
|
/* 14535 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'B', 'R', 'C', 0,
|
|
/* 14551 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'Q', 'B', 'R', 'C', 0,
|
|
/* 14564 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'R', 'C', 0,
|
|
/* 14580 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'Q', 'F', 'R', 'C', 0,
|
|
/* 14593 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'V', 'S', 'F', 'R', 'C', 0,
|
|
/* 14610 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'V', 'S', 'F', 'R', 'C', 0,
|
|
/* 14624 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'V', 'R', 'R', 'C', 0,
|
|
/* 14640 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'V', 'R', 'R', 'C', 0,
|
|
/* 14653 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'S', 'R', 'C', 0,
|
|
/* 14669 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'Q', 'S', 'R', 'C', 0,
|
|
/* 14682 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'V', 'S', 'S', 'R', 'C', 0,
|
|
/* 14699 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'V', 'S', 'S', 'R', 'C', 0,
|
|
/* 14713 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'V', 'S', 'R', 'C', 0,
|
|
/* 14729 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'V', 'S', 'R', 'C', 0,
|
|
/* 14742 */ '#', 'S', 'P', 'I', 'L', 'L', 'T', 'O', 'V', 'S', 'R', '_', 'L', 'D', 0,
|
|
/* 14757 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
|
|
/* 14770 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
|
|
/* 14777 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'S', 'P', 'E', 0,
|
|
/* 14792 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'S', 'P', 'E', 0,
|
|
/* 14804 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
|
|
/* 14814 */ '#', 'R', 'E', 'S', 'T', 'O', 'R', 'E', '_', 'V', 'R', 'S', 'A', 'V', 'E', 0,
|
|
/* 14830 */ '#', 'S', 'P', 'I', 'L', 'L', '_', 'V', 'R', 'S', 'A', 'V', 'E', 0,
|
|
/* 14844 */ '#', 'L', 'D', 't', 'o', 'c', 'J', 'T', 'I', 0,
|
|
/* 14854 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0,
|
|
/* 14864 */ '#', 'L', 'D', 't', 'o', 'c', 'L', 0,
|
|
/* 14872 */ '#', 'A', 'D', 'D', 'I', 't', 'o', 'c', 'L', 0,
|
|
/* 14882 */ '#', 'A', 'D', 'D', 'I', 't', 'l', 's', 'g', 'd', 'L', 0,
|
|
/* 14894 */ '#', 'A', 'D', 'D', 'I', 't', 'l', 's', 'l', 'd', 'L', 0,
|
|
/* 14906 */ '#', 'L', 'D', 'g', 'o', 't', 'T', 'p', 'r', 'e', 'l', 'L', 0,
|
|
/* 14919 */ '#', 'A', 'D', 'D', 'I', 'd', 't', 'p', 'r', 'e', 'l', 'L', 0,
|
|
/* 14932 */ '#', 'U', 'p', 'd', 'a', 't', 'e', 'G', 'B', 'R', 0,
|
|
/* 14943 */ '#', 'R', 'E', 'S', 'T', 'O', 'R', 'E', '_', 'C', 'R', 0,
|
|
/* 14955 */ '#', 'S', 'P', 'I', 'L', 'L', '_', 'C', 'R', 0,
|
|
/* 14965 */ '#', 'A', 'D', 'D', 'I', 't', 'l', 's', 'g', 'd', 'L', 'A', 'D', 'D', 'R', 0,
|
|
/* 14981 */ '#', 'A', 'D', 'D', 'I', 't', 'l', 's', 'l', 'd', 'L', 'A', 'D', 'D', 'R', 0,
|
|
/* 14997 */ '#', 'G', 'E', 'T', 't', 'l', 's', 'l', 'd', 'A', 'D', 'D', 'R', 0,
|
|
/* 15011 */ '#', 'G', 'E', 'T', 't', 'l', 's', 'A', 'D', 'D', 'R', 0,
|
|
/* 15023 */ '#', 'M', 'o', 'v', 'e', 'P', 'C', 't', 'o', 'L', 'R', 0,
|
|
/* 15035 */ '#', 'M', 'o', 'v', 'e', 'G', 'O', 'T', 't', 'o', 'L', 'R', 0,
|
|
/* 15048 */ '#', 'T', 'C', 'H', 'E', 'C', 'K', '_', 'R', 'E', 'T', 0,
|
|
/* 15060 */ '#', 'D', 'Y', 'N', 'A', 'R', 'E', 'A', 'O', 'F', 'F', 'S', 'E', 'T', 0,
|
|
/* 15075 */ '#', 'R', 'E', 'S', 'T', 'O', 'R', 'E', '_', 'C', 'R', 'B', 'I', 'T', 0,
|
|
/* 15090 */ '#', 'S', 'P', 'I', 'L', 'L', '_', 'C', 'R', 'B', 'I', 'T', 0,
|
|
/* 15103 */ '#', 'A', 'N', 'D', 'I', 'o', '_', '1', '_', 'E', 'Q', '_', 'B', 'I', 'T', 0,
|
|
/* 15119 */ '#', 'A', 'N', 'D', 'I', 'o', '_', '1', '_', 'G', 'T', '_', 'B', 'I', 'T', 0,
|
|
/* 15135 */ '#', 'P', 'P', 'C', '3', '2', 'G', 'O', 'T', 0,
|
|
/* 15145 */ '#', 'P', 'P', 'C', '3', '2', 'P', 'I', 'C', 'G', 'O', 'T', 0,
|
|
/* 15158 */ '#', 'L', 'D', 't', 'o', 'c', 'C', 'P', 'T', 0,
|
|
/* 15168 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
|
|
/* 15183 */ '#', 'S', 'P', 'I', 'L', 'L', 'T', 'O', 'V', 'S', 'R', '_', 'S', 'T', 0,
|
|
/* 15198 */ '#', 'L', 'I', 'W', 'A', 'X', 0,
|
|
/* 15205 */ '#', 'S', 'P', 'I', 'L', 'L', 'T', 'O', 'V', 'S', 'R', '_', 'L', 'D', 'X', 0,
|
|
/* 15221 */ '#', 'S', 'P', 'I', 'L', 'L', 'T', 'O', 'V', 'S', 'R', '_', 'S', 'T', 'X', 0,
|
|
/* 15237 */ '#', 'S', 'T', 'I', 'W', 'X', 0,
|
|
/* 15244 */ '#', 'L', 'I', 'W', 'Z', 'X', 0,
|
|
/* 15251 */ 'b', 'c', 'a', 0,
|
|
/* 15255 */ 's', 'l', 'b', 'i', 'a', 0,
|
|
/* 15261 */ 't', 'l', 'b', 'i', 'a', 0,
|
|
/* 15267 */ 'b', 'c', 'l', 'a', 0,
|
|
/* 15272 */ 'c', 'l', 'r', 'b', 'h', 'r', 'b', 0,
|
|
/* 15280 */ 'b', 'c', 0,
|
|
/* 15283 */ 's', 'l', 'b', 's', 'y', 'n', 'c', 0,
|
|
/* 15291 */ 't', 'l', 'b', 's', 'y', 'n', 'c', 0,
|
|
/* 15299 */ 'm', 's', 'g', 's', 'y', 'n', 'c', 0,
|
|
/* 15307 */ 'i', 's', 'y', 'n', 'c', 0,
|
|
/* 15313 */ 'm', 's', 'y', 'n', 'c', 0,
|
|
/* 15319 */ '#', 'L', 'D', 't', 'o', 'c', 0,
|
|
/* 15326 */ '#', 'L', 'W', 'Z', 't', 'o', 'c', 0,
|
|
/* 15334 */ 'h', 'r', 'f', 'i', 'd', 0,
|
|
/* 15340 */ 't', 'l', 'b', 'r', 'e', 0,
|
|
/* 15346 */ 't', 'l', 'b', 'w', 'e', 0,
|
|
/* 15352 */ 'r', 'f', 'c', 'i', 0,
|
|
/* 15357 */ 'r', 'f', 'm', 'c', 'i', 0,
|
|
/* 15363 */ 'r', 'f', 'd', 'i', 0,
|
|
/* 15368 */ 'r', 'f', 'i', 0,
|
|
/* 15372 */ 'b', 'c', 'l', 0,
|
|
/* 15376 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0,
|
|
/* 15390 */ 'd', 's', 's', 'a', 'l', 'l', 0,
|
|
/* 15397 */ 'b', 'l', 'r', 'l', 0,
|
|
/* 15402 */ 'b', 'd', 'z', 'l', 'r', 'l', 0,
|
|
/* 15409 */ 'b', 'd', 'n', 'z', 'l', 'r', 'l', 0,
|
|
/* 15417 */ 'b', 'c', 't', 'r', 'l', 0,
|
|
/* 15423 */ 'a', 't', 't', 'n', 0,
|
|
/* 15428 */ 'e', 'i', 'e', 'i', 'o', 0,
|
|
/* 15434 */ 'n', 'a', 'p', 0,
|
|
/* 15438 */ 't', 'r', 'a', 'p', 0,
|
|
/* 15443 */ 'n', 'o', 'p', 0,
|
|
/* 15447 */ 's', 't', 'o', 'p', 0,
|
|
/* 15452 */ 'b', 'l', 'r', 0,
|
|
/* 15456 */ 'b', 'd', 'z', 'l', 'r', 0,
|
|
/* 15462 */ 'b', 'd', 'n', 'z', 'l', 'r', 0,
|
|
/* 15469 */ 'b', 'c', 't', 'r', 0,
|
|
/* 15474 */ 'c', 'p', '_', 'a', 'b', 'o', 'r', 't', 0,
|
|
};
|
|
#endif
|
|
|
|
static const uint32_t OpInfo0[] = {
|
|
0U, // PHI
|
|
0U, // INLINEASM
|
|
0U, // CFI_INSTRUCTION
|
|
0U, // EH_LABEL
|
|
0U, // GC_LABEL
|
|
0U, // ANNOTATION_LABEL
|
|
0U, // KILL
|
|
0U, // EXTRACT_SUBREG
|
|
0U, // INSERT_SUBREG
|
|
0U, // IMPLICIT_DEF
|
|
0U, // SUBREG_TO_REG
|
|
0U, // COPY_TO_REGCLASS
|
|
14805U, // DBG_VALUE
|
|
14855U, // DBG_LABEL
|
|
0U, // REG_SEQUENCE
|
|
0U, // COPY
|
|
14771U, // BUNDLE
|
|
15169U, // LIFETIME_START
|
|
14758U, // LIFETIME_END
|
|
0U, // STACKMAP
|
|
15377U, // FENTRY_CALL
|
|
0U, // PATCHPOINT
|
|
0U, // LOAD_STACK_GUARD
|
|
0U, // STATEPOINT
|
|
0U, // LOCAL_ESCAPE
|
|
0U, // FAULTING_OP
|
|
0U, // PATCHABLE_OP
|
|
12827U, // PATCHABLE_FUNCTION_ENTER
|
|
12747U, // PATCHABLE_RET
|
|
12873U, // PATCHABLE_FUNCTION_EXIT
|
|
12850U, // PATCHABLE_TAIL_CALL
|
|
12802U, // PATCHABLE_EVENT_CALL
|
|
12778U, // PATCHABLE_TYPED_EVENT_CALL
|
|
0U, // ICALL_BRANCH_FUNNEL
|
|
0U, // G_ADD
|
|
0U, // G_SUB
|
|
0U, // G_MUL
|
|
0U, // G_SDIV
|
|
0U, // G_UDIV
|
|
0U, // G_SREM
|
|
0U, // G_UREM
|
|
0U, // G_AND
|
|
0U, // G_OR
|
|
0U, // G_XOR
|
|
0U, // G_IMPLICIT_DEF
|
|
0U, // G_PHI
|
|
0U, // G_FRAME_INDEX
|
|
0U, // G_GLOBAL_VALUE
|
|
0U, // G_EXTRACT
|
|
0U, // G_UNMERGE_VALUES
|
|
0U, // G_INSERT
|
|
0U, // G_MERGE_VALUES
|
|
0U, // G_PTRTOINT
|
|
0U, // G_INTTOPTR
|
|
0U, // G_BITCAST
|
|
0U, // G_LOAD
|
|
0U, // G_SEXTLOAD
|
|
0U, // G_ZEXTLOAD
|
|
0U, // G_STORE
|
|
0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
|
|
0U, // G_ATOMIC_CMPXCHG
|
|
0U, // G_ATOMICRMW_XCHG
|
|
0U, // G_ATOMICRMW_ADD
|
|
0U, // G_ATOMICRMW_SUB
|
|
0U, // G_ATOMICRMW_AND
|
|
0U, // G_ATOMICRMW_NAND
|
|
0U, // G_ATOMICRMW_OR
|
|
0U, // G_ATOMICRMW_XOR
|
|
0U, // G_ATOMICRMW_MAX
|
|
0U, // G_ATOMICRMW_MIN
|
|
0U, // G_ATOMICRMW_UMAX
|
|
0U, // G_ATOMICRMW_UMIN
|
|
0U, // G_BRCOND
|
|
0U, // G_BRINDIRECT
|
|
0U, // G_INTRINSIC
|
|
0U, // G_INTRINSIC_W_SIDE_EFFECTS
|
|
0U, // G_ANYEXT
|
|
0U, // G_TRUNC
|
|
0U, // G_CONSTANT
|
|
0U, // G_FCONSTANT
|
|
0U, // G_VASTART
|
|
0U, // G_VAARG
|
|
0U, // G_SEXT
|
|
0U, // G_ZEXT
|
|
0U, // G_SHL
|
|
0U, // G_LSHR
|
|
0U, // G_ASHR
|
|
0U, // G_ICMP
|
|
0U, // G_FCMP
|
|
0U, // G_SELECT
|
|
0U, // G_UADDE
|
|
0U, // G_USUBE
|
|
0U, // G_SADDO
|
|
0U, // G_SSUBO
|
|
0U, // G_UMULO
|
|
0U, // G_SMULO
|
|
0U, // G_UMULH
|
|
0U, // G_SMULH
|
|
0U, // G_FADD
|
|
0U, // G_FSUB
|
|
0U, // G_FMUL
|
|
0U, // G_FMA
|
|
0U, // G_FDIV
|
|
0U, // G_FREM
|
|
0U, // G_FPOW
|
|
0U, // G_FEXP
|
|
0U, // G_FEXP2
|
|
0U, // G_FLOG
|
|
0U, // G_FLOG2
|
|
0U, // G_FNEG
|
|
0U, // G_FPEXT
|
|
0U, // G_FPTRUNC
|
|
0U, // G_FPTOSI
|
|
0U, // G_FPTOUI
|
|
0U, // G_SITOFP
|
|
0U, // G_UITOFP
|
|
0U, // G_FABS
|
|
0U, // G_GEP
|
|
0U, // G_PTR_MASK
|
|
0U, // G_BR
|
|
0U, // G_INSERT_VECTOR_ELT
|
|
0U, // G_EXTRACT_VECTOR_ELT
|
|
0U, // G_SHUFFLE_VECTOR
|
|
0U, // G_BSWAP
|
|
0U, // G_ADDRSPACE_CAST
|
|
0U, // G_BLOCK_ADDR
|
|
14087U, // CFENCE8
|
|
21042U, // CLRLSLDI
|
|
17211U, // CLRLSLDIo
|
|
21551U, // CLRLSLWI
|
|
17320U, // CLRLSLWIo
|
|
21077U, // CLRRDI
|
|
17238U, // CLRRDIo
|
|
21592U, // CLRRWI
|
|
17349U, // CLRRWIo
|
|
536897109U, // CP_COPY_FIRST
|
|
536899711U, // CP_COPYx
|
|
536897058U, // CP_PASTE_LAST
|
|
536891262U, // CP_PASTEx
|
|
562481U, // DCBFL
|
|
564336U, // DCBFLP
|
|
561067U, // DCBFx
|
|
553690475U, // DCBTCT
|
|
553689756U, // DCBTDS
|
|
553690483U, // DCBTSTCT
|
|
553689764U, // DCBTSTDS
|
|
566909U, // DCBTSTT
|
|
566881U, // DCBTSTx
|
|
566896U, // DCBTT
|
|
566623U, // DCBTx
|
|
13334U, // DFLOADf32
|
|
13646U, // DFLOADf64
|
|
13356U, // DFSTOREf32
|
|
13668U, // DFSTOREf64
|
|
21052U, // EXTLDI
|
|
17222U, // EXTLDIo
|
|
21577U, // EXTLWI
|
|
17340U, // EXTLWIo
|
|
21101U, // EXTRDI
|
|
17265U, // EXTRDIo
|
|
21616U, // EXTRWI
|
|
17376U, // EXTRWIo
|
|
21561U, // INSLWI
|
|
17331U, // INSLWIo
|
|
21085U, // INSRDI
|
|
17247U, // INSRDIo
|
|
21600U, // INSRWI
|
|
17358U, // INSRWIo
|
|
33573242U, // LAx
|
|
15199U, // LIWAX
|
|
15245U, // LIWZX
|
|
21205U, // RLWIMIbm
|
|
17303U, // RLWIMIobm
|
|
22102U, // RLWINMbm
|
|
17434U, // RLWINMobm
|
|
22111U, // RLWNMbm
|
|
17443U, // RLWNMobm
|
|
21093U, // ROTRDI
|
|
17256U, // ROTRDIo
|
|
21608U, // ROTRWI
|
|
17367U, // ROTRWIo
|
|
21046U, // SLDI
|
|
17215U, // SLDIo
|
|
21555U, // SLWI
|
|
17324U, // SLWIo
|
|
14743U, // SPILLTOVSR_LD
|
|
15206U, // SPILLTOVSR_LDX
|
|
15184U, // SPILLTOVSR_ST
|
|
15222U, // SPILLTOVSR_STX
|
|
21087U, // SRDI
|
|
17249U, // SRDIo
|
|
21602U, // SRWI
|
|
17360U, // SRWIo
|
|
15238U, // STIWX
|
|
20993U, // SUBI
|
|
19522U, // SUBIC
|
|
16795U, // SUBICo
|
|
25475U, // SUBIS
|
|
50357130U, // SUBPCIS
|
|
13345U, // XFLOADf32
|
|
13657U, // XFLOADf64
|
|
13368U, // XFSTOREf32
|
|
13680U, // XFSTOREf64
|
|
19705U, // ADD4
|
|
19705U, // ADD4TLS
|
|
16867U, // ADD4o
|
|
19705U, // ADD8
|
|
19705U, // ADD8TLS
|
|
19705U, // ADD8TLS_
|
|
16867U, // ADD8o
|
|
19484U, // ADDC
|
|
19484U, // ADDC8
|
|
16762U, // ADDC8o
|
|
16762U, // ADDCo
|
|
20235U, // ADDE
|
|
20235U, // ADDE8
|
|
17006U, // ADDE8o
|
|
17006U, // ADDEo
|
|
21028U, // ADDI
|
|
21028U, // ADDI8
|
|
19529U, // ADDIC
|
|
19529U, // ADDIC8
|
|
16803U, // ADDICo
|
|
25500U, // ADDIS
|
|
25500U, // ADDIS8
|
|
14503U, // ADDISdtprelHA
|
|
12929U, // ADDISdtprelHA32
|
|
14486U, // ADDISgotTprelHA
|
|
14458U, // ADDIStlsgdHA
|
|
14472U, // ADDIStlsldHA
|
|
14446U, // ADDIStocHA
|
|
14920U, // ADDIdtprelL
|
|
13218U, // ADDIdtprelL32
|
|
14883U, // ADDItlsgdL
|
|
13175U, // ADDItlsgdL32
|
|
14966U, // ADDItlsgdLADDR
|
|
13270U, // ADDItlsgdLADDR32
|
|
14895U, // ADDItlsldL
|
|
13189U, // ADDItlsldL32
|
|
14982U, // ADDItlsldLADDR
|
|
13288U, // ADDItlsldLADDR32
|
|
14873U, // ADDItocL
|
|
536891214U, // ADDME
|
|
536891214U, // ADDME8
|
|
536887941U, // ADDME8o
|
|
536887941U, // ADDMEo
|
|
536896403U, // ADDPCIS
|
|
536891292U, // ADDZE
|
|
536891292U, // ADDZE8
|
|
536887990U, // ADDZE8o
|
|
536887990U, // ADDZEo
|
|
51111U, // ADJCALLSTACKDOWN
|
|
51130U, // ADJCALLSTACKUP
|
|
19976U, // AND
|
|
19976U, // AND8
|
|
16929U, // AND8o
|
|
19493U, // ANDC
|
|
19493U, // ANDC8
|
|
16769U, // ANDC8o
|
|
16769U, // ANDCo
|
|
17833U, // ANDISo
|
|
17833U, // ANDISo8
|
|
17231U, // ANDIo
|
|
17231U, // ANDIo8
|
|
15104U, // ANDIo_1_EQ_BIT
|
|
14396U, // ANDIo_1_EQ_BIT8
|
|
15120U, // ANDIo_1_GT_BIT
|
|
14413U, // ANDIo_1_GT_BIT8
|
|
16929U, // ANDo
|
|
1141917528U, // ATOMIC_CMP_SWAP_I16
|
|
1141917506U, // ATOMIC_CMP_SWAP_I32
|
|
13504U, // ATOMIC_CMP_SWAP_I64
|
|
14257U, // ATOMIC_CMP_SWAP_I8
|
|
13868U, // ATOMIC_LOAD_ADD_I16
|
|
12967U, // ATOMIC_LOAD_ADD_I32
|
|
13401U, // ATOMIC_LOAD_ADD_I64
|
|
14155U, // ATOMIC_LOAD_ADD_I8
|
|
13911U, // ATOMIC_LOAD_AND_I16
|
|
13010U, // ATOMIC_LOAD_AND_I32
|
|
13692U, // ATOMIC_LOAD_AND_I64
|
|
14196U, // ATOMIC_LOAD_AND_I8
|
|
14055U, // ATOMIC_LOAD_MAX_I16
|
|
13154U, // ATOMIC_LOAD_MAX_I32
|
|
13588U, // ATOMIC_LOAD_MAX_I64
|
|
14347U, // ATOMIC_LOAD_MAX_I8
|
|
13954U, // ATOMIC_LOAD_MIN_I16
|
|
13053U, // ATOMIC_LOAD_MIN_I32
|
|
13466U, // ATOMIC_LOAD_MIN_I64
|
|
14237U, // ATOMIC_LOAD_MIN_I8
|
|
13889U, // ATOMIC_LOAD_NAND_I16
|
|
12988U, // ATOMIC_LOAD_NAND_I32
|
|
13422U, // ATOMIC_LOAD_NAND_I64
|
|
14175U, // ATOMIC_LOAD_NAND_I8
|
|
14013U, // ATOMIC_LOAD_OR_I16
|
|
13112U, // ATOMIC_LOAD_OR_I32
|
|
13546U, // ATOMIC_LOAD_OR_I64
|
|
14296U, // ATOMIC_LOAD_OR_I8
|
|
13847U, // ATOMIC_LOAD_SUB_I16
|
|
12946U, // ATOMIC_LOAD_SUB_I32
|
|
13380U, // ATOMIC_LOAD_SUB_I64
|
|
14121U, // ATOMIC_LOAD_SUB_I8
|
|
14033U, // ATOMIC_LOAD_UMAX_I16
|
|
13132U, // ATOMIC_LOAD_UMAX_I32
|
|
13566U, // ATOMIC_LOAD_UMAX_I64
|
|
14326U, // ATOMIC_LOAD_UMAX_I8
|
|
13932U, // ATOMIC_LOAD_UMIN_I16
|
|
13031U, // ATOMIC_LOAD_UMIN_I32
|
|
13444U, // ATOMIC_LOAD_UMIN_I64
|
|
14216U, // ATOMIC_LOAD_UMIN_I8
|
|
13992U, // ATOMIC_LOAD_XOR_I16
|
|
13091U, // ATOMIC_LOAD_XOR_I32
|
|
13525U, // ATOMIC_LOAD_XOR_I64
|
|
14277U, // ATOMIC_LOAD_XOR_I8
|
|
13975U, // ATOMIC_SWAP_I16
|
|
13074U, // ATOMIC_SWAP_I32
|
|
13487U, // ATOMIC_SWAP_I64
|
|
14430U, // ATOMIC_SWAP_I8
|
|
15424U, // ATTN
|
|
592514U, // B
|
|
608340U, // BA
|
|
83902568U, // BC
|
|
1686447U, // BCC
|
|
2210735U, // BCCA
|
|
2735023U, // BCCCTR
|
|
2735023U, // BCCCTR8
|
|
3259311U, // BCCCTRL
|
|
3259311U, // BCCCTRL8
|
|
3783599U, // BCCL
|
|
4307887U, // BCCLA
|
|
4832175U, // BCCLR
|
|
5356463U, // BCCLRL
|
|
5783706U, // BCCTR
|
|
5783706U, // BCCTR8
|
|
5783762U, // BCCTR8n
|
|
5783684U, // BCCTRL
|
|
5783684U, // BCCTRL8
|
|
5783742U, // BCCTRL8n
|
|
5783742U, // BCCTRLn
|
|
5783762U, // BCCTRn
|
|
17451U, // BCDCFNo
|
|
17654U, // BCDCFSQo
|
|
18172U, // BCDCFZo
|
|
17460U, // BCDCPSGNo
|
|
536888420U, // BCDCTNo
|
|
536888576U, // BCDCTSQo
|
|
18188U, // BCDCTZo
|
|
17480U, // BCDSETSGNo
|
|
17709U, // BCDSRo
|
|
17765U, // BCDSo
|
|
16819U, // BCDTRUNCo
|
|
17858U, // BCDUSo
|
|
16830U, // BCDUTRUNCo
|
|
83902576U, // BCL
|
|
5783696U, // BCLR
|
|
5783673U, // BCLRL
|
|
5783732U, // BCLRLn
|
|
5783753U, // BCLRn
|
|
589901U, // BCLalways
|
|
83902636U, // BCLn
|
|
15470U, // BCTR
|
|
15470U, // BCTR8
|
|
15418U, // BCTRL
|
|
15418U, // BCTRL8
|
|
114778U, // BCTRL8_LDinto_toc
|
|
83902629U, // BCn
|
|
602413U, // BDNZ
|
|
602413U, // BDNZ8
|
|
608887U, // BDNZA
|
|
606464U, // BDNZAm
|
|
606249U, // BDNZAp
|
|
595380U, // BDNZL
|
|
608651U, // BDNZLA
|
|
606448U, // BDNZLAm
|
|
606233U, // BDNZLAp
|
|
15463U, // BDNZLR
|
|
15463U, // BDNZLR8
|
|
15410U, // BDNZLRL
|
|
12723U, // BDNZLRLm
|
|
12680U, // BDNZLRLp
|
|
12739U, // BDNZLRm
|
|
12696U, // BDNZLRp
|
|
590095U, // BDNZLm
|
|
589880U, // BDNZLp
|
|
590109U, // BDNZm
|
|
589894U, // BDNZp
|
|
602256U, // BDZ
|
|
602256U, // BDZ8
|
|
608881U, // BDZA
|
|
606457U, // BDZAm
|
|
606242U, // BDZAp
|
|
595374U, // BDZL
|
|
608644U, // BDZLA
|
|
606440U, // BDZLAm
|
|
606225U, // BDZLAp
|
|
15457U, // BDZLR
|
|
15457U, // BDZLR8
|
|
15403U, // BDZLRL
|
|
12715U, // BDZLRLm
|
|
12672U, // BDZLRLp
|
|
12732U, // BDZLRm
|
|
12689U, // BDZLRp
|
|
590088U, // BDZLm
|
|
589873U, // BDZLp
|
|
590103U, // BDZm
|
|
589888U, // BDZp
|
|
595190U, // BL
|
|
595190U, // BL8
|
|
6362358U, // BL8_NOP
|
|
6427894U, // BL8_NOP_TLS
|
|
660726U, // BL8_TLS
|
|
660726U, // BL8_TLS_
|
|
608633U, // BLA
|
|
608633U, // BLA8
|
|
6375801U, // BLA8_NOP
|
|
15453U, // BLR
|
|
15453U, // BLR8
|
|
15398U, // BLRL
|
|
660726U, // BL_TLS
|
|
19956U, // BPERMD
|
|
19585U, // BRINC
|
|
15273U, // CLRBHRB
|
|
19160U, // CMPB
|
|
19160U, // CMPB8
|
|
20020U, // CMPD
|
|
21070U, // CMPDI
|
|
19166U, // CMPEQB
|
|
19927U, // CMPLD
|
|
21034U, // CMPLDI
|
|
27069U, // CMPLW
|
|
21535U, // CMPLWI
|
|
100682470U, // CMPRB
|
|
100682470U, // CMPRB8
|
|
27326U, // CMPW
|
|
21585U, // CMPWI
|
|
536891107U, // CNTLZD
|
|
536887900U, // CNTLZDo
|
|
536898560U, // CNTLZW
|
|
536898560U, // CNTLZW8
|
|
536889017U, // CNTLZW8o
|
|
536889017U, // CNTLZWo
|
|
536891122U, // CNTTZD
|
|
536887909U, // CNTTZDo
|
|
536898575U, // CNTTZW
|
|
536898575U, // CNTTZW8
|
|
536889026U, // CNTTZW8o
|
|
536889026U, // CNTTZWo
|
|
15475U, // CP_ABORT
|
|
28799U, // CP_COPY
|
|
28799U, // CP_COPY8
|
|
20350U, // CP_PASTE
|
|
20350U, // CP_PASTE8
|
|
17062U, // CP_PASTE8o
|
|
17062U, // CP_PASTEo
|
|
13806U, // CR6SET
|
|
13792U, // CR6UNSET
|
|
20006U, // CRAND
|
|
19499U, // CRANDC
|
|
26534U, // CREQV
|
|
19990U, // CRNAND
|
|
24864U, // CRNOR
|
|
24878U, // CROR
|
|
19606U, // CRORC
|
|
117467046U, // CRSET
|
|
117465420U, // CRUNSET
|
|
24908U, // CRXOR
|
|
1686447U, // CTRL_DEP
|
|
536893342U, // DARN
|
|
559186U, // DCBA
|
|
151467U, // DCBF
|
|
564087U, // DCBFEP
|
|
561653U, // DCBI
|
|
566857U, // DCBST
|
|
564120U, // DCBSTEP
|
|
157023U, // DCBT
|
|
170896U, // DCBTEP
|
|
157281U, // DCBTST
|
|
170913U, // DCBTSTEP
|
|
569477U, // DCBZ
|
|
564139U, // DCBZEP
|
|
562599U, // DCBZL
|
|
564103U, // DCBZLEP
|
|
536891911U, // DCCCI
|
|
20182U, // DIVD
|
|
20241U, // DIVDE
|
|
26334U, // DIVDEU
|
|
17936U, // DIVDEUo
|
|
17013U, // DIVDEo
|
|
26327U, // DIVDU
|
|
17928U, // DIVDUo
|
|
16981U, // DIVDo
|
|
27623U, // DIVW
|
|
20364U, // DIVWE
|
|
26342U, // DIVWEU
|
|
17945U, // DIVWEUo
|
|
17070U, // DIVWEo
|
|
26448U, // DIVWU
|
|
17972U, // DIVWUo
|
|
18087U, // DIVWo
|
|
713696U, // DSS
|
|
15391U, // DSSALL
|
|
1745036880U, // DST
|
|
1745036880U, // DST64
|
|
1745036905U, // DSTST
|
|
1745036905U, // DSTST64
|
|
1745036934U, // DSTSTT
|
|
1745036934U, // DSTSTT64
|
|
1745036919U, // DSTT
|
|
1745036919U, // DSTT64
|
|
14526U, // DYNALLOC
|
|
14076U, // DYNALLOC8
|
|
15061U, // DYNAREAOFFSET
|
|
14380U, // DYNAREAOFFSET8
|
|
536895901U, // EFDABS
|
|
19702U, // EFDADD
|
|
536896266U, // EFDCFS
|
|
536891387U, // EFDCFSF
|
|
536892298U, // EFDCFSI
|
|
536890788U, // EFDCFSID
|
|
536891489U, // EFDCFUF
|
|
536892375U, // EFDCFUI
|
|
536890807U, // EFDCFUID
|
|
24525U, // EFDCMPEQ
|
|
25981U, // EFDCMPGT
|
|
26059U, // EFDCMPLT
|
|
536891461U, // EFDCTSF
|
|
536892326U, // EFDCTSI
|
|
536899733U, // EFDCTSIDZ
|
|
536899834U, // EFDCTSIZ
|
|
536891517U, // EFDCTUF
|
|
536892403U, // EFDCTUI
|
|
536899754U, // EFDCTUIDZ
|
|
536899865U, // EFDCTUIZ
|
|
26482U, // EFDDIV
|
|
21859U, // EFDMUL
|
|
536895917U, // EFDNABS
|
|
536891543U, // EFDNEG
|
|
19374U, // EFDSUB
|
|
24575U, // EFDTSTEQ
|
|
26022U, // EFDTSTGT
|
|
26100U, // EFDTSTLT
|
|
536895954U, // EFSABS
|
|
19785U, // EFSADD
|
|
536890738U, // EFSCFD
|
|
536891396U, // EFSCFSF
|
|
536892307U, // EFSCFSI
|
|
536891498U, // EFSCFUF
|
|
536892384U, // EFSCFUI
|
|
24545U, // EFSCMPEQ
|
|
26001U, // EFSCMPGT
|
|
26079U, // EFSCMPLT
|
|
536891470U, // EFSCTSF
|
|
536892335U, // EFSCTSI
|
|
536899844U, // EFSCTSIZ
|
|
536891526U, // EFSCTUF
|
|
536892412U, // EFSCTUI
|
|
536899875U, // EFSCTUIZ
|
|
26496U, // EFSDIV
|
|
21875U, // EFSMUL
|
|
536895935U, // EFSNABS
|
|
536891559U, // EFSNEG
|
|
19409U, // EFSSUB
|
|
24585U, // EFSTSTEQ
|
|
26032U, // EFSTSTGT
|
|
26110U, // EFSTSTLT
|
|
13233U, // EH_SjLj_LongJmp32
|
|
13609U, // EH_SjLj_LongJmp64
|
|
13252U, // EH_SjLj_SetJmp32
|
|
13628U, // EH_SjLj_SetJmp64
|
|
589825U, // EH_SjLj_Setup
|
|
26529U, // EQV
|
|
26529U, // EQV8
|
|
17987U, // EQV8o
|
|
17987U, // EQVo
|
|
536895971U, // EVABS
|
|
16804243U, // EVADDIW
|
|
536897549U, // EVADDSMIAAW
|
|
536897681U, // EVADDSSIAAW
|
|
536897615U, // EVADDUMIAAW
|
|
536897747U, // EVADDUSIAAW
|
|
26929U, // EVADDW
|
|
20013U, // EVAND
|
|
19507U, // EVANDC
|
|
24566U, // EVCMPEQ
|
|
25591U, // EVCMPGTS
|
|
26394U, // EVCMPGTU
|
|
25601U, // EVCMPLTS
|
|
26404U, // EVCMPLTU
|
|
536898309U, // EVCNTLSW
|
|
536898558U, // EVCNTLZW
|
|
25763U, // EVDIVWS
|
|
26446U, // EVDIVWU
|
|
26541U, // EVEQV
|
|
536890171U, // EVEXTSB
|
|
536891736U, // EVEXTSH
|
|
536895962U, // EVFSABS
|
|
19793U, // EVFSADD
|
|
536891405U, // EVFSCFSF
|
|
536892316U, // EVFSCFSI
|
|
536891507U, // EVFSCFUF
|
|
536892393U, // EVFSCFUI
|
|
24555U, // EVFSCMPEQ
|
|
26011U, // EVFSCMPGT
|
|
26089U, // EVFSCMPLT
|
|
536891479U, // EVFSCTSF
|
|
536892344U, // EVFSCTSI
|
|
536899854U, // EVFSCTSIZ
|
|
536891479U, // EVFSCTUF
|
|
536892421U, // EVFSCTUI
|
|
536899854U, // EVFSCTUIZ
|
|
26504U, // EVFSDIV
|
|
21883U, // EVFSMUL
|
|
536895944U, // EVFSNABS
|
|
536891567U, // EVFSNEG
|
|
19417U, // EVFSSUB
|
|
24595U, // EVFSTSTEQ
|
|
26042U, // EVFSTSTGT
|
|
26120U, // EVFSTSTLT
|
|
33574234U, // EVLDD
|
|
604007606U, // EVLDDX
|
|
33575110U, // EVLDH
|
|
604007710U, // EVLDHX
|
|
33581369U, // EVLDW
|
|
604008463U, // EVLDWX
|
|
33580305U, // EVLHHESPLAT
|
|
604008203U, // EVLHHESPLATX
|
|
33580330U, // EVLHHOSSPLAT
|
|
604008230U, // EVLHHOSSPLATX
|
|
33580344U, // EVLHHOUSPLAT
|
|
604008245U, // EVLHHOUSPLATX
|
|
33574703U, // EVLWHE
|
|
604007681U, // EVLWHEX
|
|
33579987U, // EVLWHOS
|
|
604008175U, // EVLWHOSX
|
|
33580797U, // EVLWHOU
|
|
604008361U, // EVLWHOUX
|
|
33580318U, // EVLWHSPLAT
|
|
604008217U, // EVLWHSPLATX
|
|
33580358U, // EVLWWSPLAT
|
|
604008260U, // EVLWWSPLATX
|
|
21141U, // EVMERGEHI
|
|
22475U, // EVMERGEHILO
|
|
22464U, // EVMERGELO
|
|
21152U, // EVMERGELOHI
|
|
18392U, // EVMHEGSMFAA
|
|
22234U, // EVMHEGSMFAN
|
|
18440U, // EVMHEGSMIAA
|
|
22282U, // EVMHEGSMIAN
|
|
18477U, // EVMHEGUMIAA
|
|
22319U, // EVMHEGUMIAN
|
|
20407U, // EVMHESMF
|
|
18525U, // EVMHESMFA
|
|
26585U, // EVMHESMFAAW
|
|
27110U, // EVMHESMFANW
|
|
21213U, // EVMHESMI
|
|
18616U, // EVMHESMIA
|
|
26650U, // EVMHESMIAAW
|
|
27162U, // EVMHESMIANW
|
|
20510U, // EVMHESSF
|
|
18568U, // EVMHESSFA
|
|
26611U, // EVMHESSFAAW
|
|
27136U, // EVMHESSFANW
|
|
26782U, // EVMHESSIAAW
|
|
27240U, // EVMHESSIANW
|
|
21252U, // EVMHEUMI
|
|
18659U, // EVMHEUMIA
|
|
26716U, // EVMHEUMIAAW
|
|
27201U, // EVMHEUMIANW
|
|
26848U, // EVMHEUSIAAW
|
|
27279U, // EVMHEUSIANW
|
|
18405U, // EVMHOGSMFAA
|
|
22247U, // EVMHOGSMFAN
|
|
18453U, // EVMHOGSMIAA
|
|
22295U, // EVMHOGSMIAN
|
|
18490U, // EVMHOGUMIAA
|
|
22332U, // EVMHOGUMIAN
|
|
20427U, // EVMHOSMF
|
|
18547U, // EVMHOSMFA
|
|
26598U, // EVMHOSMFAAW
|
|
27123U, // EVMHOSMFANW
|
|
21233U, // EVMHOSMI
|
|
18638U, // EVMHOSMIA
|
|
26690U, // EVMHOSMIAAW
|
|
27188U, // EVMHOSMIANW
|
|
20530U, // EVMHOSSF
|
|
18590U, // EVMHOSSFA
|
|
26624U, // EVMHOSSFAAW
|
|
27149U, // EVMHOSSFANW
|
|
26822U, // EVMHOSSIAAW
|
|
27266U, // EVMHOSSIANW
|
|
21282U, // EVMHOUMI
|
|
18692U, // EVMHOUMIA
|
|
26756U, // EVMHOUMIAAW
|
|
27227U, // EVMHOUMIANW
|
|
26888U, // EVMHOUSIAAW
|
|
27305U, // EVMHOUSIANW
|
|
536889747U, // EVMRA
|
|
20417U, // EVMWHSMF
|
|
18536U, // EVMWHSMFA
|
|
21223U, // EVMWHSMI
|
|
18627U, // EVMWHSMIA
|
|
20520U, // EVMWHSSF
|
|
18579U, // EVMWHSSFA
|
|
21262U, // EVMWHUMI
|
|
18670U, // EVMWHUMIA
|
|
26677U, // EVMWLSMIAAW
|
|
27175U, // EVMWLSMIANW
|
|
26809U, // EVMWLSSIAAW
|
|
27253U, // EVMWLSSIANW
|
|
21272U, // EVMWLUMI
|
|
18681U, // EVMWLUMIA
|
|
26743U, // EVMWLUMIAAW
|
|
27214U, // EVMWLUMIANW
|
|
26875U, // EVMWLUSIAAW
|
|
27292U, // EVMWLUSIANW
|
|
20437U, // EVMWSMF
|
|
18558U, // EVMWSMFA
|
|
18418U, // EVMWSMFAA
|
|
22260U, // EVMWSMFAN
|
|
21243U, // EVMWSMI
|
|
18649U, // EVMWSMIA
|
|
18466U, // EVMWSMIAA
|
|
22308U, // EVMWSMIAN
|
|
20540U, // EVMWSSF
|
|
18601U, // EVMWSSFA
|
|
18429U, // EVMWSSFAA
|
|
22271U, // EVMWSSFAN
|
|
21292U, // EVMWUMI
|
|
18703U, // EVMWUMIA
|
|
18503U, // EVMWUMIAA
|
|
22345U, // EVMWUMIAN
|
|
19998U, // EVNAND
|
|
536891576U, // EVNEG
|
|
24871U, // EVNOR
|
|
24884U, // EVOR
|
|
19613U, // EVORC
|
|
27076U, // EVRLW
|
|
21543U, // EVRLWI
|
|
536897856U, // EVRNDW
|
|
2154328480U, // EVSEL
|
|
27083U, // EVSLW
|
|
21569U, // EVSLWI
|
|
151016074U, // EVSPLATFI
|
|
151016397U, // EVSPLATI
|
|
25519U, // EVSRWIS
|
|
26356U, // EVSRWIU
|
|
25691U, // EVSRWS
|
|
26432U, // EVSRWU
|
|
33574250U, // EVSTDD
|
|
604007614U, // EVSTDDX
|
|
33575117U, // EVSTDH
|
|
604007718U, // EVSTDHX
|
|
33581384U, // EVSTDW
|
|
604008471U, // EVSTDWX
|
|
33574711U, // EVSTWHE
|
|
604007690U, // EVSTWHEX
|
|
33576887U, // EVSTWHO
|
|
604007872U, // EVSTWHOX
|
|
33574803U, // EVSTWWE
|
|
604007700U, // EVSTWWEX
|
|
33577040U, // EVSTWWO
|
|
604007882U, // EVSTWWOX
|
|
536897575U, // EVSUBFSMIAAW
|
|
536897707U, // EVSUBFSSIAAW
|
|
536897641U, // EVSUBFUMIAAW
|
|
536897773U, // EVSUBFUSIAAW
|
|
26977U, // EVSUBFW
|
|
167799146U, // EVSUBIFW
|
|
24915U, // EVXOR
|
|
536890173U, // EXTSB
|
|
536890173U, // EXTSB8
|
|
536890173U, // EXTSB8_32_64
|
|
536887609U, // EXTSB8o
|
|
536887609U, // EXTSBo
|
|
536891738U, // EXTSH
|
|
536891738U, // EXTSH8
|
|
536891738U, // EXTSH8_32_64
|
|
536888050U, // EXTSH8o
|
|
536888050U, // EXTSHo
|
|
536898346U, // EXTSW
|
|
21179U, // EXTSWSLI
|
|
17283U, // EXTSWSLIo
|
|
536898346U, // EXTSW_32
|
|
536898346U, // EXTSW_32_64
|
|
536888969U, // EXTSW_32_64o
|
|
536888969U, // EXTSWo
|
|
15429U, // EnforceIEIO
|
|
536895911U, // FABSD
|
|
536888635U, // FABSDo
|
|
536895911U, // FABSS
|
|
536888635U, // FABSSo
|
|
19712U, // FADD
|
|
25154U, // FADDS
|
|
17772U, // FADDSo
|
|
16866U, // FADDo
|
|
0U, // FADDrtz
|
|
536890781U, // FCFID
|
|
536896148U, // FCFIDS
|
|
536888711U, // FCFIDSo
|
|
536897210U, // FCFIDU
|
|
536896533U, // FCFIDUS
|
|
536888778U, // FCFIDUSo
|
|
536888822U, // FCFIDUo
|
|
536887810U, // FCFIDo
|
|
26374U, // FCMPUD
|
|
26374U, // FCMPUS
|
|
22369U, // FCPSGND
|
|
17471U, // FCPSGNDo
|
|
22369U, // FCPSGNS
|
|
17471U, // FCPSGNSo
|
|
536890800U, // FCTID
|
|
536897220U, // FCTIDU
|
|
536899893U, // FCTIDUZ
|
|
536889109U, // FCTIDUZo
|
|
536888831U, // FCTIDUo
|
|
536899746U, // FCTIDZ
|
|
536889075U, // FCTIDZo
|
|
536887818U, // FCTIDo
|
|
536897950U, // FCTIW
|
|
536897336U, // FCTIWU
|
|
536899904U, // FCTIWUZ
|
|
536889119U, // FCTIWUZo
|
|
536888875U, // FCTIWUo
|
|
536899915U, // FCTIWZ
|
|
536889129U, // FCTIWZo
|
|
536888930U, // FCTIWo
|
|
26490U, // FDIV
|
|
25684U, // FDIVS
|
|
17876U, // FDIVSo
|
|
17980U, // FDIVo
|
|
19720U, // FMADD
|
|
25163U, // FMADDS
|
|
17780U, // FMADDSo
|
|
16873U, // FMADDo
|
|
536895725U, // FMR
|
|
536888603U, // FMRo
|
|
19392U, // FMSUB
|
|
25133U, // FMSUBS
|
|
17746U, // FMSUBSo
|
|
16723U, // FMSUBo
|
|
21869U, // FMUL
|
|
25538U, // FMULS
|
|
17841U, // FMULSo
|
|
17409U, // FMULo
|
|
536895928U, // FNABSD
|
|
536888642U, // FNABSDo
|
|
536895928U, // FNABSS
|
|
536888642U, // FNABSSo
|
|
536891553U, // FNEGD
|
|
536888022U, // FNEGDo
|
|
536891553U, // FNEGS
|
|
536888022U, // FNEGSo
|
|
19729U, // FNMADD
|
|
25173U, // FNMADDS
|
|
17789U, // FNMADDSo
|
|
16881U, // FNMADDo
|
|
19401U, // FNMSUB
|
|
25143U, // FNMSUBS
|
|
17755U, // FNMSUBSo
|
|
16731U, // FNMSUBo
|
|
536891238U, // FRE
|
|
536896248U, // FRES
|
|
536888720U, // FRESo
|
|
536887958U, // FREo
|
|
536893000U, // FRIMD
|
|
536888339U, // FRIMDo
|
|
536893000U, // FRIMS
|
|
536888339U, // FRIMSo
|
|
536893298U, // FRIND
|
|
536888413U, // FRINDo
|
|
536893298U, // FRINS
|
|
536888413U, // FRINSo
|
|
536894570U, // FRIPD
|
|
536888508U, // FRIPDo
|
|
536894570U, // FRIPS
|
|
536888508U, // FRIPSo
|
|
536899828U, // FRIZD
|
|
536889093U, // FRIZDo
|
|
536899828U, // FRIZS
|
|
536889093U, // FRIZSo
|
|
536895271U, // FRSP
|
|
536888539U, // FRSPo
|
|
536891253U, // FRSQRTE
|
|
536896256U, // FRSQRTES
|
|
536888727U, // FRSQRTESo
|
|
536887964U, // FRSQRTEo
|
|
21784U, // FSELD
|
|
17402U, // FSELDo
|
|
21784U, // FSELS
|
|
17402U, // FSELSo
|
|
536897043U, // FSQRT
|
|
536896523U, // FSQRTS
|
|
536888761U, // FSQRTSo
|
|
536888805U, // FSQRTo
|
|
19384U, // FSUB
|
|
25124U, // FSUBS
|
|
17738U, // FSUBSo
|
|
16716U, // FSUBo
|
|
26513U, // FTDIV
|
|
536897050U, // FTSQRT
|
|
15012U, // GETtlsADDR
|
|
13321U, // GETtlsADDR32
|
|
14998U, // GETtlsldADDR
|
|
13306U, // GETtlsldADDR32
|
|
15335U, // HRFID
|
|
561659U, // ICBI
|
|
564095U, // ICBIEP
|
|
216186U, // ICBLC
|
|
214254U, // ICBLQ
|
|
222565U, // ICBT
|
|
222136U, // ICBTLS
|
|
536891918U, // ICCCI
|
|
21790U, // ISEL
|
|
21790U, // ISEL8
|
|
15308U, // ISYNC
|
|
184568186U, // LA
|
|
604007996U, // LBARX
|
|
2751491644U, // LBARXL
|
|
604007892U, // LBEPX
|
|
33583243U, // LBZ
|
|
33583243U, // LBZ8
|
|
28020U, // LBZCIX
|
|
201353047U, // LBZU
|
|
201353047U, // LBZU8
|
|
218132450U, // LBZUX
|
|
218132450U, // LBZUX8
|
|
604008529U, // LBZX
|
|
604008529U, // LBZX8
|
|
28753U, // LBZXTLS
|
|
28753U, // LBZXTLS_
|
|
28753U, // LBZXTLS_32
|
|
33574340U, // LD
|
|
604008003U, // LDARX
|
|
2751491651U, // LDARXL
|
|
25860U, // LDAT
|
|
604008024U, // LDBRX
|
|
27989U, // LDCIX
|
|
604007859U, // LDMX
|
|
201352908U, // LDU
|
|
218132366U, // LDUX
|
|
604007645U, // LDX
|
|
27869U, // LDXTLS
|
|
27869U, // LDXTLS_
|
|
14907U, // LDgotTprelL
|
|
13203U, // LDgotTprelL32
|
|
15320U, // LDtoc
|
|
15159U, // LDtocBA
|
|
15159U, // LDtocCPT
|
|
14845U, // LDtocJTI
|
|
14865U, // LDtocL
|
|
33574266U, // LFD
|
|
604007907U, // LFDEPX
|
|
201352858U, // LFDU
|
|
218132349U, // LFDUX
|
|
604007625U, // LFDX
|
|
604007534U, // LFIWAX
|
|
604008552U, // LFIWZX
|
|
33579800U, // LFS
|
|
201352973U, // LFSU
|
|
218132426U, // LFSUX
|
|
604008150U, // LFSX
|
|
33573043U, // LHA
|
|
33573043U, // LHA8
|
|
604008010U, // LHARX
|
|
2751491658U, // LHARXL
|
|
201352846U, // LHAU
|
|
201352846U, // LHAU8
|
|
218132305U, // LHAUX
|
|
218132305U, // LHAUX8
|
|
604007517U, // LHAX
|
|
604007517U, // LHAX8
|
|
604008039U, // LHBRX
|
|
604008039U, // LHBRX8
|
|
604007924U, // LHEPX
|
|
33583307U, // LHZ
|
|
33583307U, // LHZ8
|
|
28028U, // LHZCIX
|
|
201353053U, // LHZU
|
|
201353053U, // LHZU8
|
|
218132457U, // LHZUX
|
|
218132457U, // LHZUX8
|
|
604008544U, // LHZX
|
|
604008544U, // LHZX8
|
|
28768U, // LHZXTLS
|
|
28768U, // LHZXTLS_
|
|
28768U, // LHZXTLS_32
|
|
50352816U, // LI
|
|
50352816U, // LI8
|
|
50357155U, // LIS
|
|
50357155U, // LIS8
|
|
33581522U, // LMW
|
|
21624U, // LSWI
|
|
604007557U, // LVEBX
|
|
604007727U, // LVEHX
|
|
604008480U, // LVEWX
|
|
604001629U, // LVSL
|
|
604004738U, // LVSR
|
|
604008439U, // LVX
|
|
604001690U, // LVXL
|
|
33573274U, // LWA
|
|
604008017U, // LWARX
|
|
2751491665U, // LWARXL
|
|
25938U, // LWAT
|
|
218132312U, // LWAUX
|
|
604007551U, // LWAX
|
|
604007551U, // LWAX_32
|
|
33573274U, // LWA_32
|
|
604008064U, // LWBRX
|
|
604008064U, // LWBRX8
|
|
604007939U, // LWEPX
|
|
33583443U, // LWZ
|
|
33583443U, // LWZ8
|
|
28036U, // LWZCIX
|
|
201353059U, // LWZU
|
|
201353059U, // LWZU8
|
|
218132464U, // LWZUX
|
|
218132464U, // LWZUX8
|
|
604008569U, // LWZX
|
|
604008569U, // LWZX8
|
|
28793U, // LWZXTLS
|
|
28793U, // LWZXTLS_
|
|
28793U, // LWZXTLS_32
|
|
15327U, // LWZtoc
|
|
33574522U, // LXSD
|
|
604007660U, // LXSDX
|
|
604008520U, // LXSIBZX
|
|
604008535U, // LXSIHZX
|
|
604007542U, // LXSIWAX
|
|
604008560U, // LXSIWZX
|
|
33578823U, // LXSSP
|
|
604007979U, // LXSSPX
|
|
33580986U, // LXV
|
|
604007481U, // LXVB16X
|
|
604007447U, // LXVD2X
|
|
604008133U, // LXVDSX
|
|
604007500U, // LXVH8X
|
|
21901U, // LXVL
|
|
21816U, // LXVLL
|
|
604007464U, // LXVW4X
|
|
604008195U, // LXVWSX
|
|
604008450U, // LXVX
|
|
19852U, // MADDHD
|
|
26279U, // MADDHDU
|
|
19912U, // MADDLD
|
|
712845U, // MBAR
|
|
536891358U, // MCRF
|
|
536896285U, // MCRFS
|
|
552611U, // MCRXRX
|
|
234901242U, // MFBHRBE
|
|
549032U, // MFCR
|
|
549032U, // MFCR8
|
|
549263U, // MFCTR
|
|
549263U, // MFCTR8
|
|
536895635U, // MFDCR
|
|
549650U, // MFFS
|
|
536893357U, // MFFSCDRN
|
|
251679569U, // MFFSCDRNI
|
|
544515U, // MFFSCE
|
|
536893348U, // MFFSCRN
|
|
268456775U, // MFFSCRNI
|
|
546134U, // MFFSL
|
|
542114U, // MFFSo
|
|
549087U, // MFLR
|
|
549087U, // MFLR8
|
|
549230U, // MFMSR
|
|
285233124U, // MFOCRF
|
|
285233124U, // MFOCRF8
|
|
536895730U, // MFPMR
|
|
536895834U, // MFSPR
|
|
536895834U, // MFSPR8
|
|
302014824U, // MFSR
|
|
536893304U, // MFSRIN
|
|
536890194U, // MFTB
|
|
7364954U, // MFTB8
|
|
536890953U, // MFVRD
|
|
7889242U, // MFVRSAVE
|
|
7889242U, // MFVRSAVEv
|
|
549046U, // MFVSCR
|
|
536890953U, // MFVSRD
|
|
536890846U, // MFVSRLD
|
|
536899928U, // MFVSRWZ
|
|
20057U, // MODSD
|
|
27345U, // MODSW
|
|
20139U, // MODUD
|
|
27520U, // MODUW
|
|
15300U, // MSGSYNC
|
|
15314U, // MSYNC
|
|
536891380U, // MTCRF
|
|
536891380U, // MTCRF8
|
|
549270U, // MTCTR
|
|
549270U, // MTCTR8
|
|
549270U, // MTCTR8loop
|
|
549270U, // MTCTRloop
|
|
654516385U, // MTDCR
|
|
706354U, // MTFSB0
|
|
706362U, // MTFSB1
|
|
20503U, // MTFSF
|
|
21122U, // MTFSFI
|
|
17274U, // MTFSFIo
|
|
536891415U, // MTFSFb
|
|
17102U, // MTFSFo
|
|
549093U, // MTLR
|
|
549093U, // MTLR8
|
|
536895861U, // MTMSR
|
|
536890945U, // MTMSRD
|
|
233452U, // MTOCRF
|
|
233452U, // MTOCRF8
|
|
536895737U, // MTPMR
|
|
536895841U, // MTSPR
|
|
536895841U, // MTSPR8
|
|
254332U, // MTSR
|
|
536893312U, // MTSRIN
|
|
540892U, // MTVRSAVE
|
|
721116U, // MTVRSAVEv
|
|
549054U, // MTVSCR
|
|
536890961U, // MTVSRD
|
|
19809U, // MTVSRDD
|
|
536889759U, // MTVSRWA
|
|
536896611U, // MTVSRWS
|
|
536899937U, // MTVSRWZ
|
|
19860U, // MULHD
|
|
26288U, // MULHDU
|
|
17901U, // MULHDUo
|
|
16890U, // MULHDo
|
|
27020U, // MULHW
|
|
26414U, // MULHWU
|
|
17954U, // MULHWUo
|
|
18010U, // MULHWo
|
|
19920U, // MULLD
|
|
16914U, // MULLDo
|
|
21172U, // MULLI
|
|
21172U, // MULLI8
|
|
27062U, // MULLW
|
|
18026U, // MULLWo
|
|
15036U, // MoveGOTtoLR
|
|
15024U, // MovePCtoLR
|
|
14367U, // MovePCtoLR8
|
|
19984U, // NAND
|
|
19984U, // NAND8
|
|
16928U, // NAND8o
|
|
16928U, // NANDo
|
|
15435U, // NAP
|
|
536891546U, // NEG
|
|
536891546U, // NEG8
|
|
536888023U, // NEG8o
|
|
536888023U, // NEGo
|
|
15444U, // NOP
|
|
12905U, // NOP_GT_PWR6
|
|
12917U, // NOP_GT_PWR7
|
|
24859U, // NOR
|
|
24859U, // NOR8
|
|
17697U, // NOR8o
|
|
17697U, // NORo
|
|
24852U, // OR
|
|
24852U, // OR8
|
|
17698U, // OR8o
|
|
19601U, // ORC
|
|
19601U, // ORC8
|
|
16842U, // ORC8o
|
|
16842U, // ORCo
|
|
21381U, // ORI
|
|
21381U, // ORI8
|
|
25513U, // ORIS
|
|
25513U, // ORIS8
|
|
17698U, // ORo
|
|
536890209U, // POPCNTB
|
|
536891027U, // POPCNTD
|
|
536898379U, // POPCNTW
|
|
15136U, // PPC32GOT
|
|
15146U, // PPC32PICGOT
|
|
21309U, // QVALIGNI
|
|
21309U, // QVALIGNIb
|
|
21309U, // QVALIGNIs
|
|
21442U, // QVESPLATI
|
|
21442U, // QVESPLATIb
|
|
21442U, // QVESPLATIs
|
|
536895909U, // QVFABS
|
|
536895909U, // QVFABSs
|
|
19710U, // QVFADD
|
|
25152U, // QVFADDS
|
|
25152U, // QVFADDSs
|
|
536890779U, // QVFCFID
|
|
536896146U, // QVFCFIDS
|
|
536897208U, // QVFCFIDU
|
|
536896531U, // QVFCFIDUS
|
|
536890779U, // QVFCFIDb
|
|
24535U, // QVFCMPEQ
|
|
24535U, // QVFCMPEQb
|
|
24535U, // QVFCMPEQbs
|
|
25991U, // QVFCMPGT
|
|
25991U, // QVFCMPGTb
|
|
25991U, // QVFCMPGTbs
|
|
26069U, // QVFCMPLT
|
|
26069U, // QVFCMPLTb
|
|
26069U, // QVFCMPLTbs
|
|
22367U, // QVFCPSGN
|
|
22367U, // QVFCPSGNs
|
|
536890798U, // QVFCTID
|
|
536897218U, // QVFCTIDU
|
|
536899891U, // QVFCTIDUZ
|
|
536899744U, // QVFCTIDZ
|
|
536890798U, // QVFCTIDb
|
|
536897948U, // QVFCTIW
|
|
536897334U, // QVFCTIWU
|
|
536899902U, // QVFCTIWUZ
|
|
536899913U, // QVFCTIWZ
|
|
21738U, // QVFLOGICAL
|
|
21738U, // QVFLOGICALb
|
|
21738U, // QVFLOGICALs
|
|
19718U, // QVFMADD
|
|
25161U, // QVFMADDS
|
|
25161U, // QVFMADDSs
|
|
536895723U, // QVFMR
|
|
536895723U, // QVFMRb
|
|
536895723U, // QVFMRs
|
|
19390U, // QVFMSUB
|
|
25131U, // QVFMSUBS
|
|
25131U, // QVFMSUBSs
|
|
21867U, // QVFMUL
|
|
25536U, // QVFMULS
|
|
25536U, // QVFMULSs
|
|
536895926U, // QVFNABS
|
|
536895926U, // QVFNABSs
|
|
536891551U, // QVFNEG
|
|
536891551U, // QVFNEGs
|
|
19727U, // QVFNMADD
|
|
25171U, // QVFNMADDS
|
|
25171U, // QVFNMADDSs
|
|
19399U, // QVFNMSUB
|
|
25141U, // QVFNMSUBS
|
|
25141U, // QVFNMSUBSs
|
|
22156U, // QVFPERM
|
|
22156U, // QVFPERMs
|
|
536891236U, // QVFRE
|
|
536896246U, // QVFRES
|
|
536896246U, // QVFRESs
|
|
536892998U, // QVFRIM
|
|
536892998U, // QVFRIMs
|
|
536893296U, // QVFRIN
|
|
536893296U, // QVFRINs
|
|
536894568U, // QVFRIP
|
|
536894568U, // QVFRIPs
|
|
536899826U, // QVFRIZ
|
|
536899826U, // QVFRIZs
|
|
536895269U, // QVFRSP
|
|
536895269U, // QVFRSPs
|
|
536891251U, // QVFRSQRTE
|
|
536896254U, // QVFRSQRTES
|
|
536896254U, // QVFRSQRTESs
|
|
21782U, // QVFSEL
|
|
21782U, // QVFSELb
|
|
21782U, // QVFSELbb
|
|
21782U, // QVFSELbs
|
|
19382U, // QVFSUB
|
|
25122U, // QVFSUBS
|
|
25122U, // QVFSUBSs
|
|
22356U, // QVFTSTNAN
|
|
22356U, // QVFTSTNANb
|
|
22356U, // QVFTSTNANbs
|
|
19764U, // QVFXMADD
|
|
25211U, // QVFXMADDS
|
|
21892U, // QVFXMUL
|
|
25545U, // QVFXMULS
|
|
19737U, // QVFXXCPNMADD
|
|
25182U, // QVFXXCPNMADDS
|
|
19774U, // QVFXXMADD
|
|
25222U, // QVFXXMADDS
|
|
19751U, // QVFXXNPMADD
|
|
25197U, // QVFXXNPMADDS
|
|
318788117U, // QVGPCI
|
|
604008294U, // QVLFCDUX
|
|
603998723U, // QVLFCDUXA
|
|
604007587U, // QVLFCDX
|
|
603998643U, // QVLFCDXA
|
|
604008371U, // QVLFCSUX
|
|
603998767U, // QVLFCSUXA
|
|
604008114U, // QVLFCSX
|
|
603998683U, // QVLFCSXA
|
|
604008114U, // QVLFCSXs
|
|
218132347U, // QVLFDUX
|
|
603998746U, // QVLFDUXA
|
|
604007623U, // QVLFDX
|
|
603998664U, // QVLFDXA
|
|
604007623U, // QVLFDXb
|
|
604007532U, // QVLFIWAX
|
|
603998632U, // QVLFIWAXA
|
|
604008550U, // QVLFIWZX
|
|
603998822U, // QVLFIWZXA
|
|
218132424U, // QVLFSUX
|
|
603998790U, // QVLFSUXA
|
|
604008148U, // QVLFSX
|
|
603998704U, // QVLFSXA
|
|
604008148U, // QVLFSXb
|
|
604008148U, // QVLFSXs
|
|
604007640U, // QVLPCLDX
|
|
604008165U, // QVLPCLSX
|
|
8416997U, // QVLPCLSXint
|
|
604007650U, // QVLPCRDX
|
|
604008185U, // QVLPCRSX
|
|
604008304U, // QVSTFCDUX
|
|
603998734U, // QVSTFCDUXA
|
|
604001460U, // QVSTFCDUXI
|
|
603998535U, // QVSTFCDUXIA
|
|
604007596U, // QVSTFCDX
|
|
603998653U, // QVSTFCDXA
|
|
604001418U, // QVSTFCDXI
|
|
603998489U, // QVSTFCDXIA
|
|
604008381U, // QVSTFCSUX
|
|
603998778U, // QVSTFCSUXA
|
|
604001483U, // QVSTFCSUXI
|
|
603998560U, // QVSTFCSUXIA
|
|
604008123U, // QVSTFCSX
|
|
603998693U, // QVSTFCSXA
|
|
604001439U, // QVSTFCSXI
|
|
603998512U, // QVSTFCSXIA
|
|
604008123U, // QVSTFCSXs
|
|
218312580U, // QVSTFDUX
|
|
603998756U, // QVSTFDUXA
|
|
604001472U, // QVSTFDUXI
|
|
603998548U, // QVSTFDUXIA
|
|
604007631U, // QVSTFDX
|
|
603998673U, // QVSTFDXA
|
|
604001429U, // QVSTFDXI
|
|
603998501U, // QVSTFDXIA
|
|
604007631U, // QVSTFDXb
|
|
604008495U, // QVSTFIWX
|
|
603998811U, // QVSTFIWXA
|
|
218312657U, // QVSTFSUX
|
|
603998800U, // QVSTFSUXA
|
|
604001495U, // QVSTFSUXI
|
|
603998573U, // QVSTFSUXIA
|
|
218312657U, // QVSTFSUXs
|
|
604008156U, // QVSTFSX
|
|
603998713U, // QVSTFSXA
|
|
604001450U, // QVSTFSXI
|
|
603998524U, // QVSTFSXIA
|
|
604008156U, // QVSTFSXs
|
|
14944U, // RESTORE_CR
|
|
15076U, // RESTORE_CRBIT
|
|
14815U, // RESTORE_VRSAVE
|
|
15353U, // RFCI
|
|
15364U, // RFDI
|
|
264837U, // RFEBB
|
|
15369U, // RFI
|
|
15336U, // RFID
|
|
15358U, // RFMCI
|
|
21759U, // RLDCL
|
|
17385U, // RLDCLo
|
|
24730U, // RLDCR
|
|
17674U, // RLDCRo
|
|
19536U, // RLDIC
|
|
21766U, // RLDICL
|
|
21766U, // RLDICL_32
|
|
21766U, // RLDICL_32_64
|
|
17393U, // RLDICL_32o
|
|
17393U, // RLDICLo
|
|
24750U, // RLDICR
|
|
24750U, // RLDICR_32
|
|
17682U, // RLDICRo
|
|
16811U, // RLDICo
|
|
3355464397U, // RLDIMI
|
|
3355460494U, // RLDIMIo
|
|
3892335317U, // RLWIMI
|
|
3892335317U, // RLWIMI8
|
|
3892331415U, // RLWIMI8o
|
|
3892331415U, // RLWIMIo
|
|
22102U, // RLWINM
|
|
22102U, // RLWINM8
|
|
17434U, // RLWINM8o
|
|
17434U, // RLWINMo
|
|
22111U, // RLWNM
|
|
22111U, // RLWNM8
|
|
17443U, // RLWNM8o
|
|
17443U, // RLWNMo
|
|
14518U, // ReadTB
|
|
543908U, // SC
|
|
13820U, // SELECT_CC_F16
|
|
13742U, // SELECT_CC_F4
|
|
14096U, // SELECT_CC_F8
|
|
13767U, // SELECT_CC_I4
|
|
14141U, // SELECT_CC_I8
|
|
14536U, // SELECT_CC_QBRC
|
|
14565U, // SELECT_CC_QFRC
|
|
14654U, // SELECT_CC_QSRC
|
|
14778U, // SELECT_CC_SPE
|
|
13713U, // SELECT_CC_SPE4
|
|
14625U, // SELECT_CC_VRRC
|
|
14594U, // SELECT_CC_VSFRC
|
|
14714U, // SELECT_CC_VSRC
|
|
14683U, // SELECT_CC_VSSRC
|
|
13835U, // SELECT_F16
|
|
13756U, // SELECT_F4
|
|
14110U, // SELECT_F8
|
|
13781U, // SELECT_I4
|
|
14315U, // SELECT_I8
|
|
14552U, // SELECT_QBRC
|
|
14581U, // SELECT_QFRC
|
|
14670U, // SELECT_QSRC
|
|
14793U, // SELECT_SPE
|
|
13729U, // SELECT_SPE4
|
|
14641U, // SELECT_VRRC
|
|
14611U, // SELECT_VSFRC
|
|
14730U, // SELECT_VSRC
|
|
14700U, // SELECT_VSSRC
|
|
536890188U, // SETB
|
|
15256U, // SLBIA
|
|
544576U, // SLBIE
|
|
536891535U, // SLBIEG
|
|
536891160U, // SLBMFEE
|
|
536897385U, // SLBMFEV
|
|
536891243U, // SLBMTE
|
|
15284U, // SLBSYNC
|
|
19950U, // SLD
|
|
16922U, // SLDo
|
|
27085U, // SLW
|
|
27085U, // SLW8
|
|
18034U, // SLW8o
|
|
18034U, // SLWo
|
|
33583443U, // SPELWZ
|
|
604008569U, // SPELWZX
|
|
33581929U, // SPESTW
|
|
604008514U, // SPESTWX
|
|
14956U, // SPILL_CR
|
|
15091U, // SPILL_CRBIT
|
|
14831U, // SPILL_VRSAVE
|
|
19680U, // SRAD
|
|
21021U, // SRADI
|
|
21021U, // SRADI_32
|
|
17203U, // SRADIo
|
|
16859U, // SRADo
|
|
26914U, // SRAW
|
|
21519U, // SRAWI
|
|
17312U, // SRAWIo
|
|
17993U, // SRAWo
|
|
20036U, // SRD
|
|
16942U, // SRDo
|
|
27340U, // SRW
|
|
27340U, // SRW8
|
|
18040U, // SRW8o
|
|
18040U, // SRWo
|
|
33573748U, // STB
|
|
33573748U, // STB8
|
|
27981U, // STBCIX
|
|
603997899U, // STBCX
|
|
604007899U, // STBEPX
|
|
201533076U, // STBU
|
|
201533076U, // STBU8
|
|
218312543U, // STBUX
|
|
218312543U, // STBUX8
|
|
604007581U, // STBX
|
|
604007581U, // STBX8
|
|
27805U, // STBXTLS
|
|
27805U, // STBXTLS_
|
|
27805U, // STBXTLS_32
|
|
33574566U, // STD
|
|
25866U, // STDAT
|
|
604008031U, // STDBRX
|
|
27996U, // STDCIX
|
|
603997907U, // STDCX
|
|
201533137U, // STDU
|
|
218312596U, // STDUX
|
|
604007675U, // STDX
|
|
27899U, // STDXTLS
|
|
27899U, // STDXTLS_
|
|
33574271U, // STFD
|
|
604007915U, // STFDEPX
|
|
201533088U, // STFDU
|
|
218312582U, // STFDUX
|
|
604007633U, // STFDX
|
|
604008497U, // STFIWX
|
|
33579812U, // STFS
|
|
201533203U, // STFSU
|
|
218312659U, // STFSUX
|
|
604008158U, // STFSX
|
|
33575301U, // STH
|
|
33575301U, // STH8
|
|
604008046U, // STHBRX
|
|
28004U, // STHCIX
|
|
603997915U, // STHCX
|
|
604007931U, // STHEPX
|
|
201533166U, // STHU
|
|
201533166U, // STHU8
|
|
218312610U, // STHUX
|
|
218312610U, // STHUX8
|
|
604007751U, // STHX
|
|
604007751U, // STHX8
|
|
27975U, // STHXTLS
|
|
27975U, // STHXTLS_
|
|
27975U, // STHXTLS_32
|
|
33581527U, // STMW
|
|
15448U, // STOP
|
|
21630U, // STSWI
|
|
604007564U, // STVEBX
|
|
604007734U, // STVEHX
|
|
604008487U, // STVEWX
|
|
604008444U, // STVX
|
|
604001696U, // STVXL
|
|
33581929U, // STW
|
|
33581929U, // STW8
|
|
25944U, // STWAT
|
|
604008071U, // STWBRX
|
|
28012U, // STWCIX
|
|
603997923U, // STWCX
|
|
604007946U, // STWEPX
|
|
201533256U, // STWU
|
|
201533256U, // STWU8
|
|
218312667U, // STWUX
|
|
218312667U, // STWUX8
|
|
604008514U, // STWX
|
|
604008514U, // STWX8
|
|
28738U, // STWXTLS
|
|
28738U, // STWXTLS_
|
|
28738U, // STWXTLS_32
|
|
33574528U, // STXSD
|
|
604007667U, // STXSDX
|
|
604007572U, // STXSIBX
|
|
604007572U, // STXSIBXv
|
|
604007742U, // STXSIHX
|
|
604007742U, // STXSIHXv
|
|
604008505U, // STXSIWX
|
|
33578830U, // STXSSP
|
|
604007987U, // STXSSPX
|
|
33580991U, // STXV
|
|
604007490U, // STXVB16X
|
|
604007455U, // STXVD2X
|
|
604007508U, // STXVH8X
|
|
21907U, // STXVL
|
|
21823U, // STXVLL
|
|
604007472U, // STXVW4X
|
|
604008456U, // STXVX
|
|
20401U, // SUBF
|
|
20401U, // SUBF8
|
|
17095U, // SUBF8o
|
|
19515U, // SUBFC
|
|
19515U, // SUBFC8
|
|
16787U, // SUBFC8o
|
|
16787U, // SUBFCo
|
|
20264U, // SUBFE
|
|
20264U, // SUBFE8
|
|
17021U, // SUBFE8o
|
|
17021U, // SUBFEo
|
|
19543U, // SUBFIC
|
|
19543U, // SUBFIC8
|
|
536891221U, // SUBFME
|
|
536891221U, // SUBFME8
|
|
536887949U, // SUBFME8o
|
|
536887949U, // SUBFMEo
|
|
536891299U, // SUBFZE
|
|
536891299U, // SUBFZE8
|
|
536887998U, // SUBFZE8o
|
|
536887998U, // SUBFZEo
|
|
17095U, // SUBFo
|
|
543880U, // SYNC
|
|
722396U, // TABORT
|
|
9191816U, // TABORTDC
|
|
9716507U, // TABORTDCI
|
|
9191888U, // TABORTWC
|
|
9716519U, // TABORTWCI
|
|
592514U, // TAILB
|
|
592514U, // TAILB8
|
|
608340U, // TAILBA
|
|
608340U, // TAILBA8
|
|
15470U, // TAILBCTR
|
|
15470U, // TAILBCTR8
|
|
263252U, // TBEGIN
|
|
546018U, // TCHECK
|
|
15049U, // TCHECK_RET
|
|
538003403U, // TCRETURNai
|
|
538003310U, // TCRETURNai8
|
|
537988294U, // TCRETURNdi
|
|
537986940U, // TCRETURNdi8
|
|
537944192U, // TCRETURNri
|
|
537937802U, // TCRETURNri8
|
|
183950U, // TD
|
|
184949U, // TDI
|
|
819751U, // TEND
|
|
15262U, // TLBIA
|
|
661327687U, // TLBIE
|
|
546062U, // TLBIEL
|
|
536898659U, // TLBIVAX
|
|
544193U, // TLBLD
|
|
545453U, // TLBLI
|
|
15341U, // TLBRE
|
|
20317U, // TLBRE2
|
|
536899243U, // TLBSX
|
|
28331U, // TLBSX2
|
|
18155U, // TLBSX2D
|
|
15292U, // TLBSYNC
|
|
15347U, // TLBWE
|
|
20357U, // TLBWE2
|
|
15439U, // TRAP
|
|
12895U, // TRECHKPT
|
|
721928U, // TRECLAIM
|
|
820533U, // TSR
|
|
191293U, // TW
|
|
185477U, // TWI
|
|
536889240U, // UPDATE_VRSAVE
|
|
14933U, // UpdateGBR
|
|
19321U, // VABSDUB
|
|
20874U, // VABSDUH
|
|
27527U, // VABSDUW
|
|
24652U, // VADDCUQ
|
|
27511U, // VADDCUW
|
|
24683U, // VADDECUQ
|
|
22146U, // VADDEUQM
|
|
23511U, // VADDFP
|
|
25085U, // VADDSBS
|
|
25428U, // VADDSHS
|
|
25727U, // VADDSWS
|
|
21966U, // VADDUBM
|
|
25113U, // VADDUBS
|
|
21994U, // VADDUDM
|
|
22033U, // VADDUHM
|
|
25456U, // VADDUHS
|
|
22127U, // VADDUQM
|
|
22216U, // VADDUWM
|
|
25754U, // VADDUWS
|
|
20014U, // VAND
|
|
19508U, // VANDC
|
|
19196U, // VAVGSB
|
|
20761U, // VAVGSH
|
|
27361U, // VAVGSW
|
|
19339U, // VAVGUB
|
|
20892U, // VAVGUH
|
|
27545U, // VAVGUW
|
|
19955U, // VBPERMD
|
|
24606U, // VBPERMQ
|
|
134246093U, // VCFSX
|
|
536899277U, // VCFSX_0
|
|
134246299U, // VCFUX
|
|
536899483U, // VCFUX_0
|
|
24784U, // VCIPHER
|
|
26172U, // VCIPHERLAST
|
|
536890378U, // VCLZB
|
|
536891100U, // VCLZD
|
|
536891879U, // VCLZH
|
|
536889996U, // VCLZLSBB
|
|
536898551U, // VCLZW
|
|
23475U, // VCMPBFP
|
|
17553U, // VCMPBFPo
|
|
23574U, // VCMPEQFP
|
|
17574U, // VCMPEQFPo
|
|
19364U, // VCMPEQUB
|
|
16705U, // VCMPEQUBo
|
|
20154U, // VCMPEQUD
|
|
16959U, // VCMPEQUDo
|
|
20917U, // VCMPEQUH
|
|
17146U, // VCMPEQUHo
|
|
27570U, // VCMPEQUW
|
|
18065U, // VCMPEQUWo
|
|
23528U, // VCMPGEFP
|
|
17563U, // VCMPGEFPo
|
|
23584U, // VCMPGTFP
|
|
17585U, // VCMPGTFPo
|
|
19249U, // VCMPGTSB
|
|
16686U, // VCMPGTSBo
|
|
20072U, // VCMPGTSD
|
|
16948U, // VCMPGTSDo
|
|
20814U, // VCMPGTSH
|
|
17127U, // VCMPGTSHo
|
|
27424U, // VCMPGTSW
|
|
18046U, // VCMPGTSWo
|
|
19438U, // VCMPGTUB
|
|
16740U, // VCMPGTUBo
|
|
20164U, // VCMPGTUD
|
|
16970U, // VCMPGTUDo
|
|
20939U, // VCMPGTUH
|
|
17157U, // VCMPGTUHo
|
|
27605U, // VCMPGTUW
|
|
18076U, // VCMPGTUWo
|
|
19104U, // VCMPNEB
|
|
16676U, // VCMPNEBo
|
|
20693U, // VCMPNEH
|
|
17117U, // VCMPNEHo
|
|
26968U, // VCMPNEW
|
|
18000U, // VCMPNEWo
|
|
19456U, // VCMPNEZB
|
|
16751U, // VCMPNEZBo
|
|
20957U, // VCMPNEZH
|
|
17168U, // VCMPNEZHo
|
|
27629U, // VCMPNEZW
|
|
18094U, // VCMPNEZWo
|
|
134243572U, // VCTSXS
|
|
536896756U, // VCTSXS_0
|
|
134243580U, // VCTUXS
|
|
536896764U, // VCTUXS_0
|
|
536890385U, // VCTZB
|
|
536891115U, // VCTZD
|
|
536891886U, // VCTZH
|
|
536890006U, // VCTZLSBB
|
|
536898568U, // VCTZW
|
|
26542U, // VEQV
|
|
536894457U, // VEXPTEFP
|
|
1207979655U, // VEXTRACTD
|
|
1207978978U, // VEXTRACTUB
|
|
1207980479U, // VEXTRACTUH
|
|
1207987132U, // VEXTRACTUW
|
|
536890536U, // VEXTSB2D
|
|
536890536U, // VEXTSB2Ds
|
|
536897477U, // VEXTSB2W
|
|
536897477U, // VEXTSB2Ws
|
|
536890546U, // VEXTSH2D
|
|
536890546U, // VEXTSH2Ds
|
|
536897487U, // VEXTSH2W
|
|
536897487U, // VEXTSH2Ws
|
|
536890556U, // VEXTSW2D
|
|
536890556U, // VEXTSW2Ds
|
|
28053U, // VEXTUBLX
|
|
28278U, // VEXTUBRX
|
|
28063U, // VEXTUHLX
|
|
28303U, // VEXTUHRX
|
|
28073U, // VEXTUWLX
|
|
28313U, // VEXTUWRX
|
|
536890598U, // VGBBD
|
|
335563626U, // VINSERTB
|
|
1207979676U, // VINSERTD
|
|
335565179U, // VINSERTH
|
|
1207987028U, // VINSERTW
|
|
536894431U, // VLOGEFP
|
|
23502U, // VMADDFP
|
|
23594U, // VMAXFP
|
|
19268U, // VMAXSB
|
|
20082U, // VMAXSD
|
|
20833U, // VMAXSH
|
|
27441U, // VMAXSW
|
|
19448U, // VMAXUB
|
|
20174U, // VMAXUD
|
|
20949U, // VMAXUH
|
|
27615U, // VMAXUW
|
|
25405U, // VMHADDSHS
|
|
25416U, // VMHRADDSHS
|
|
23566U, // VMINFP
|
|
19232U, // VMINSB
|
|
20064U, // VMINSD
|
|
20797U, // VMINSH
|
|
27407U, // VMINSW
|
|
19347U, // VMINUB
|
|
20146U, // VMINUD
|
|
20900U, // VMINUH
|
|
27553U, // VMINUW
|
|
22022U, // VMLADDUHM
|
|
26960U, // VMRGEW
|
|
19113U, // VMRGHB
|
|
20702U, // VMRGHH
|
|
27003U, // VMRGHW
|
|
19131U, // VMRGLB
|
|
20710U, // VMRGLH
|
|
27045U, // VMRGLW
|
|
27318U, // VMRGOW
|
|
21947U, // VMSUMMBM
|
|
22003U, // VMSUMSHM
|
|
25437U, // VMSUMSHS
|
|
21975U, // VMSUMUBM
|
|
22042U, // VMSUMUHM
|
|
25465U, // VMSUMUHS
|
|
536895544U, // VMUL10CUQ
|
|
24661U, // VMUL10ECUQ
|
|
24693U, // VMUL10EUQ
|
|
536895534U, // VMUL10UQ
|
|
19187U, // VMULESB
|
|
20752U, // VMULESH
|
|
27352U, // VMULESW
|
|
19330U, // VMULEUB
|
|
20883U, // VMULEUH
|
|
27536U, // VMULEUW
|
|
19240U, // VMULOSB
|
|
20805U, // VMULOSH
|
|
27415U, // VMULOSW
|
|
19355U, // VMULOUB
|
|
20908U, // VMULOUH
|
|
27561U, // VMULOUW
|
|
22225U, // VMULUWM
|
|
19999U, // VNAND
|
|
24774U, // VNCIPHER
|
|
26158U, // VNCIPHERLAST
|
|
536890757U, // VNEGD
|
|
536897908U, // VNEGW
|
|
23484U, // VNMSUBFP
|
|
24872U, // VNOR
|
|
24885U, // VOR
|
|
19614U, // VORC
|
|
22165U, // VPERM
|
|
24832U, // VPERMR
|
|
24898U, // VPERMXOR
|
|
28187U, // VPKPX
|
|
25564U, // VPKSDSS
|
|
25630U, // VPKSDUS
|
|
25573U, // VPKSHSS
|
|
25648U, // VPKSHUS
|
|
25582U, // VPKSWSS
|
|
25666U, // VPKSWUS
|
|
22180U, // VPKUDUM
|
|
25639U, // VPKUDUS
|
|
22189U, // VPKUHUM
|
|
25657U, // VPKUHUS
|
|
22198U, // VPKUWUM
|
|
25675U, // VPKUWUS
|
|
19151U, // VPMSUMB
|
|
19964U, // VPMSUMD
|
|
20730U, // VPMSUMH
|
|
27101U, // VPMSUMW
|
|
536890208U, // VPOPCNTB
|
|
536891026U, // VPOPCNTD
|
|
536891761U, // VPOPCNTH
|
|
536898378U, // VPOPCNTW
|
|
536890605U, // VPRTYBD
|
|
536895428U, // VPRTYBQ
|
|
536897832U, // VPRTYBW
|
|
536894450U, // VREFP
|
|
536892964U, // VRFIM
|
|
536893289U, // VRFIN
|
|
536894534U, // VRFIP
|
|
536899792U, // VRFIZ
|
|
19139U, // VRLB
|
|
19943U, // VRLD
|
|
21189U, // VRLDMI
|
|
22094U, // VRLDNM
|
|
20718U, // VRLH
|
|
27077U, // VRLW
|
|
21301U, // VRLWMI
|
|
22110U, // VRLWNM
|
|
536894467U, // VRSQRTEFP
|
|
536899001U, // VSBOX
|
|
21796U, // VSEL
|
|
19667U, // VSHASIGMAD
|
|
26901U, // VSHASIGMAW
|
|
21854U, // VSL
|
|
19145U, // VSLB
|
|
19949U, // VSLD
|
|
21340U, // VSLDOI
|
|
20724U, // VSLH
|
|
22488U, // VSLO
|
|
26520U, // VSLV
|
|
27084U, // VSLW
|
|
134237016U, // VSPLTB
|
|
134237016U, // VSPLTBs
|
|
134238569U, // VSPLTH
|
|
134238569U, // VSPLTHs
|
|
151014157U, // VSPLTISB
|
|
151015722U, // VSPLTISH
|
|
151022322U, // VSPLTISW
|
|
134245177U, // VSPLTW
|
|
24963U, // VSR
|
|
19070U, // VSRAB
|
|
19679U, // VSRAD
|
|
20671U, // VSRAH
|
|
26913U, // VSRAW
|
|
19181U, // VSRB
|
|
20043U, // VSRD
|
|
20746U, // VSRH
|
|
22602U, // VSRO
|
|
26548U, // VSRV
|
|
27339U, // VSRW
|
|
24643U, // VSUBCUQ
|
|
27502U, // VSUBCUW
|
|
24673U, // VSUBECUQ
|
|
22136U, // VSUBEUQM
|
|
23494U, // VSUBFP
|
|
25076U, // VSUBSBS
|
|
25396U, // VSUBSHS
|
|
25718U, // VSUBSWS
|
|
21957U, // VSUBUBM
|
|
25104U, // VSUBUBS
|
|
21985U, // VSUBUDM
|
|
22013U, // VSUBUHM
|
|
25447U, // VSUBUHS
|
|
22118U, // VSUBUQM
|
|
22207U, // VSUBUWM
|
|
25745U, // VSUBUWS
|
|
25708U, // VSUM2SWS
|
|
25066U, // VSUM4SBS
|
|
25386U, // VSUM4SHS
|
|
25094U, // VSUM4UBS
|
|
25736U, // VSUMSWS
|
|
536899090U, // VUPKHPX
|
|
536890116U, // VUPKHSB
|
|
536891681U, // VUPKHSH
|
|
536898281U, // VUPKHSW
|
|
536899106U, // VUPKLPX
|
|
536890135U, // VUPKLSB
|
|
536891700U, // VUPKLSH
|
|
536898300U, // VUPKLSW
|
|
24916U, // VXOR
|
|
117465428U, // V_SET0
|
|
117465428U, // V_SET0B
|
|
117465428U, // V_SET0H
|
|
9988850U, // V_SETALLONES
|
|
9988850U, // V_SETALLONESB
|
|
9988850U, // V_SETALLONESH
|
|
550341U, // WAIT
|
|
544545U, // WRTEE
|
|
545402U, // WRTEEI
|
|
24893U, // XOR
|
|
24893U, // XOR8
|
|
17703U, // XOR8o
|
|
21380U, // XORI
|
|
21380U, // XORI8
|
|
25512U, // XORIS
|
|
25512U, // XORIS8
|
|
17703U, // XORo
|
|
536894157U, // XSABSDP
|
|
536894776U, // XSABSQP
|
|
22769U, // XSADDDP
|
|
23734U, // XSADDQP
|
|
22561U, // XSADDQPO
|
|
24034U, // XSADDSP
|
|
23203U, // XSCMPEQDP
|
|
23171U, // XSCMPEXPDP
|
|
23832U, // XSCMPEXPQP
|
|
22831U, // XSCMPGEDP
|
|
23263U, // XSCMPGTDP
|
|
23101U, // XSCMPODP
|
|
23802U, // XSCMPOQP
|
|
23327U, // XSCMPUDP
|
|
23883U, // XSCMPUQP
|
|
23061U, // XSCPSGNDP
|
|
23791U, // XSCPSGNQP
|
|
536894514U, // XSCVDPHP
|
|
536894724U, // XSCVDPQP
|
|
536895208U, // XSCVDPSP
|
|
536893331U, // XSCVDPSPN
|
|
536896174U, // XSCVDPSXDS
|
|
536896174U, // XSCVDPSXDSs
|
|
536896684U, // XSCVDPSXWS
|
|
536896684U, // XSCVDPSXWSs
|
|
536896210U, // XSCVDPUXDS
|
|
536896210U, // XSCVDPUXDSs
|
|
536896720U, // XSCVDPUXWS
|
|
536896720U, // XSCVDPUXWSs
|
|
536894023U, // XSCVHPDP
|
|
536894033U, // XSCVQPDP
|
|
536893406U, // XSCVQPDPO
|
|
536899765U, // XSCVQPSDZ
|
|
536899946U, // XSCVQPSWZ
|
|
536899776U, // XSCVQPUDZ
|
|
536899957U, // XSCVQPUWZ
|
|
536894655U, // XSCVSDQP
|
|
536894043U, // XSCVSPDP
|
|
536893320U, // XSCVSPDPN
|
|
536893699U, // XSCVSXDDP
|
|
536894964U, // XSCVSXDSP
|
|
536894665U, // XSCVUDQP
|
|
536893721U, // XSCVUXDDP
|
|
536894986U, // XSCVUXDSP
|
|
23337U, // XSDIVDP
|
|
23893U, // XSDIVQP
|
|
22592U, // XSDIVQPO
|
|
24448U, // XSDIVSP
|
|
23151U, // XSIEXPDP
|
|
23822U, // XSIEXPQP
|
|
1744853151U, // XSMADDADP
|
|
1744854436U, // XSMADDASP
|
|
1744853503U, // XSMADDMDP
|
|
1744854718U, // XSMADDMSP
|
|
1744854188U, // XSMADDQP
|
|
1744853014U, // XSMADDQPO
|
|
22759U, // XSMAXCDP
|
|
23397U, // XSMAXDP
|
|
22941U, // XSMAXJDP
|
|
22749U, // XSMINCDP
|
|
23083U, // XSMINDP
|
|
22931U, // XSMINJDP
|
|
1744853105U, // XSMSUBADP
|
|
1744854390U, // XSMSUBASP
|
|
1744853457U, // XSMSUBMDP
|
|
1744854672U, // XSMSUBMSP
|
|
1744854147U, // XSMSUBQP
|
|
1744852981U, // XSMSUBQPO
|
|
22951U, // XSMULDP
|
|
23782U, // XSMULQP
|
|
22571U, // XSMULQPO
|
|
24166U, // XSMULSP
|
|
536894137U, // XSNABSDP
|
|
536894766U, // XSNABSQP
|
|
536893805U, // XSNEGDP
|
|
536894675U, // XSNEGQP
|
|
1744853127U, // XSNMADDADP
|
|
1744854412U, // XSNMADDASP
|
|
1744853479U, // XSNMADDMDP
|
|
1744854694U, // XSNMADDMSP
|
|
1744854177U, // XSNMADDQP
|
|
1744853002U, // XSNMADDQPO
|
|
1744853081U, // XSNMSUBADP
|
|
1744854366U, // XSNMSUBASP
|
|
1744853433U, // XSNMSUBMDP
|
|
1744854648U, // XSNMSUBMSP
|
|
1744854136U, // XSNMSUBQP
|
|
1744852969U, // XSNMSUBQPO
|
|
536892260U, // XSRDPI
|
|
536890463U, // XSRDPIC
|
|
536892971U, // XSRDPIM
|
|
536894541U, // XSRDPIP
|
|
536899799U, // XSRDPIZ
|
|
536893765U, // XSREDP
|
|
536895019U, // XSRESP
|
|
117740404U, // XSRQPI
|
|
117747084U, // XSRQPIX
|
|
117743547U, // XSRQPXP
|
|
536895277U, // XSRSP
|
|
536893781U, // XSRSQRTEDP
|
|
536895035U, // XSRSQRTESP
|
|
536894197U, // XSSQRTDP
|
|
536894785U, // XSSQRTQP
|
|
536893493U, // XSSQRTQPO
|
|
536895329U, // XSSQRTSP
|
|
22709U, // XSSUBDP
|
|
23693U, // XSSUBQP
|
|
22528U, // XSSUBQPO
|
|
23994U, // XSSUBSP
|
|
23346U, // XSTDIVDP
|
|
536894207U, // XSTSQRTDP
|
|
2281724103U, // XSTSTDCDP
|
|
2281725078U, // XSTSTDCQP
|
|
2281725388U, // XSTSTDCSP
|
|
536894095U, // XSXEXPDP
|
|
536894756U, // XSXEXPQP
|
|
536893823U, // XSXSIGDP
|
|
536894684U, // XSXSIGQP
|
|
536894166U, // XVABSDP
|
|
536895294U, // XVABSSP
|
|
22778U, // XVADDDP
|
|
24043U, // XVADDSP
|
|
23214U, // XVCMPEQDP
|
|
17529U, // XVCMPEQDPo
|
|
24346U, // XVCMPEQSP
|
|
17615U, // XVCMPEQSPo
|
|
22842U, // XVCMPGEDP
|
|
17517U, // XVCMPGEDPo
|
|
24096U, // XVCMPGESP
|
|
17603U, // XVCMPGESPo
|
|
23274U, // XVCMPGTDP
|
|
17541U, // XVCMPGTDPo
|
|
24406U, // XVCMPGTSP
|
|
17634U, // XVCMPGTSPo
|
|
23072U, // XVCPSGNDP
|
|
24276U, // XVCPSGNSP
|
|
536895218U, // XVCVDPSP
|
|
536896186U, // XVCVDPSXDS
|
|
536896696U, // XVCVDPSXWS
|
|
536896222U, // XVCVDPUXDS
|
|
536896732U, // XVCVDPUXWS
|
|
536895228U, // XVCVHPSP
|
|
536894053U, // XVCVSPDP
|
|
536894524U, // XVCVSPHP
|
|
536896198U, // XVCVSPSXDS
|
|
536896708U, // XVCVSPSXWS
|
|
536896234U, // XVCVSPUXDS
|
|
536896744U, // XVCVSPUXWS
|
|
536893710U, // XVCVSXDDP
|
|
536894975U, // XVCVSXDSP
|
|
536894287U, // XVCVSXWDP
|
|
536895388U, // XVCVSXWSP
|
|
536893732U, // XVCVUXDDP
|
|
536894997U, // XVCVUXDSP
|
|
536894298U, // XVCVUXWDP
|
|
536895399U, // XVCVUXWSP
|
|
23366U, // XVDIVDP
|
|
24467U, // XVDIVSP
|
|
23161U, // XVIEXPDP
|
|
24326U, // XVIEXPSP
|
|
1744853162U, // XVMADDADP
|
|
1744854447U, // XVMADDASP
|
|
1744853514U, // XVMADDMDP
|
|
1744854729U, // XVMADDMSP
|
|
23406U, // XVMAXDP
|
|
24498U, // XVMAXSP
|
|
23092U, // XVMINDP
|
|
24287U, // XVMINSP
|
|
1744853116U, // XVMSUBADP
|
|
1744854401U, // XVMSUBASP
|
|
1744853468U, // XVMSUBMDP
|
|
1744854683U, // XVMSUBMSP
|
|
22960U, // XVMULDP
|
|
24175U, // XVMULSP
|
|
536894147U, // XVNABSDP
|
|
536895284U, // XVNABSSP
|
|
536893814U, // XVNEGDP
|
|
536895059U, // XVNEGSP
|
|
1744853139U, // XVNMADDADP
|
|
1744854424U, // XVNMADDASP
|
|
1744853491U, // XVNMADDMDP
|
|
1744854706U, // XVNMADDMSP
|
|
1744853093U, // XVNMSUBADP
|
|
1744854378U, // XVNMSUBASP
|
|
1744853445U, // XVNMSUBMDP
|
|
1744854660U, // XVNMSUBMSP
|
|
536892268U, // XVRDPI
|
|
536890472U, // XVRDPIC
|
|
536892980U, // XVRDPIM
|
|
536894550U, // XVRDPIP
|
|
536899808U, // XVRDPIZ
|
|
536893773U, // XVREDP
|
|
536895027U, // XVRESP
|
|
536892284U, // XVRSPI
|
|
536890481U, // XVRSPIC
|
|
536892989U, // XVRSPIM
|
|
536894559U, // XVRSPIP
|
|
536899817U, // XVRSPIZ
|
|
536893793U, // XVRSQRTEDP
|
|
536895047U, // XVRSQRTESP
|
|
536894229U, // XVSQRTDP
|
|
536895350U, // XVSQRTSP
|
|
22718U, // XVSUBDP
|
|
24003U, // XVSUBSP
|
|
23356U, // XVTDIVDP
|
|
24457U, // XVTDIVSP
|
|
536894218U, // XVTSQRTDP
|
|
536895339U, // XVTSQRTSP
|
|
2281724114U, // XVTSTDCDP
|
|
2281725399U, // XVTSTDCSP
|
|
536894105U, // XVXEXPDP
|
|
536895248U, // XVXEXPSP
|
|
536893833U, // XVXSIGDP
|
|
536895068U, // XVXSIGSP
|
|
536890938U, // XXBRD
|
|
536891651U, // XXBRH
|
|
536895527U, // XXBRQ
|
|
536898244U, // XXBRW
|
|
27592U, // XXEXTRACTUW
|
|
2818599774U, // XXINSERTW
|
|
19973U, // XXLAND
|
|
19490U, // XXLANDC
|
|
26526U, // XXLEQV
|
|
19981U, // XXLNAND
|
|
24856U, // XXLNOR
|
|
24849U, // XXLOR
|
|
19598U, // XXLORC
|
|
24849U, // XXLORf
|
|
24890U, // XXLXOR
|
|
117465402U, // XXLXORdpz
|
|
117465402U, // XXLXORspz
|
|
117465402U, // XXLXORz
|
|
27011U, // XXMRGHW
|
|
27053U, // XXMRGLW
|
|
22172U, // XXPERM
|
|
21060U, // XXPERMDI
|
|
21060U, // XXPERMDIs
|
|
24840U, // XXPERMR
|
|
21802U, // XXSEL
|
|
21526U, // XXSLDWI
|
|
21526U, // XXSLDWIs
|
|
352340657U, // XXSPLTIB
|
|
27457U, // XXSPLTW
|
|
27457U, // XXSPLTWs
|
|
183320U, // gBC
|
|
182360U, // gBCA
|
|
10812308U, // gBCAat
|
|
188808U, // gBCCTR
|
|
185678U, // gBCCTRL
|
|
185594U, // gBCL
|
|
182654U, // gBCLA
|
|
10812324U, // gBCLAat
|
|
188633U, // gBCLR
|
|
185671U, // gBCLRL
|
|
11336717U, // gBCLat
|
|
11336625U, // gBCat
|
|
};
|
|
|
|
static const uint16_t OpInfo1[] = {
|
|
0U, // PHI
|
|
0U, // INLINEASM
|
|
0U, // CFI_INSTRUCTION
|
|
0U, // EH_LABEL
|
|
0U, // GC_LABEL
|
|
0U, // ANNOTATION_LABEL
|
|
0U, // KILL
|
|
0U, // EXTRACT_SUBREG
|
|
0U, // INSERT_SUBREG
|
|
0U, // IMPLICIT_DEF
|
|
0U, // SUBREG_TO_REG
|
|
0U, // COPY_TO_REGCLASS
|
|
0U, // DBG_VALUE
|
|
0U, // DBG_LABEL
|
|
0U, // REG_SEQUENCE
|
|
0U, // COPY
|
|
0U, // BUNDLE
|
|
0U, // LIFETIME_START
|
|
0U, // LIFETIME_END
|
|
0U, // STACKMAP
|
|
0U, // FENTRY_CALL
|
|
0U, // PATCHPOINT
|
|
0U, // LOAD_STACK_GUARD
|
|
0U, // STATEPOINT
|
|
0U, // LOCAL_ESCAPE
|
|
0U, // FAULTING_OP
|
|
0U, // PATCHABLE_OP
|
|
0U, // PATCHABLE_FUNCTION_ENTER
|
|
0U, // PATCHABLE_RET
|
|
0U, // PATCHABLE_FUNCTION_EXIT
|
|
0U, // PATCHABLE_TAIL_CALL
|
|
0U, // PATCHABLE_EVENT_CALL
|
|
0U, // PATCHABLE_TYPED_EVENT_CALL
|
|
0U, // ICALL_BRANCH_FUNNEL
|
|
0U, // G_ADD
|
|
0U, // G_SUB
|
|
0U, // G_MUL
|
|
0U, // G_SDIV
|
|
0U, // G_UDIV
|
|
0U, // G_SREM
|
|
0U, // G_UREM
|
|
0U, // G_AND
|
|
0U, // G_OR
|
|
0U, // G_XOR
|
|
0U, // G_IMPLICIT_DEF
|
|
0U, // G_PHI
|
|
0U, // G_FRAME_INDEX
|
|
0U, // G_GLOBAL_VALUE
|
|
0U, // G_EXTRACT
|
|
0U, // G_UNMERGE_VALUES
|
|
0U, // G_INSERT
|
|
0U, // G_MERGE_VALUES
|
|
0U, // G_PTRTOINT
|
|
0U, // G_INTTOPTR
|
|
0U, // G_BITCAST
|
|
0U, // G_LOAD
|
|
0U, // G_SEXTLOAD
|
|
0U, // G_ZEXTLOAD
|
|
0U, // G_STORE
|
|
0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
|
|
0U, // G_ATOMIC_CMPXCHG
|
|
0U, // G_ATOMICRMW_XCHG
|
|
0U, // G_ATOMICRMW_ADD
|
|
0U, // G_ATOMICRMW_SUB
|
|
0U, // G_ATOMICRMW_AND
|
|
0U, // G_ATOMICRMW_NAND
|
|
0U, // G_ATOMICRMW_OR
|
|
0U, // G_ATOMICRMW_XOR
|
|
0U, // G_ATOMICRMW_MAX
|
|
0U, // G_ATOMICRMW_MIN
|
|
0U, // G_ATOMICRMW_UMAX
|
|
0U, // G_ATOMICRMW_UMIN
|
|
0U, // G_BRCOND
|
|
0U, // G_BRINDIRECT
|
|
0U, // G_INTRINSIC
|
|
0U, // G_INTRINSIC_W_SIDE_EFFECTS
|
|
0U, // G_ANYEXT
|
|
0U, // G_TRUNC
|
|
0U, // G_CONSTANT
|
|
0U, // G_FCONSTANT
|
|
0U, // G_VASTART
|
|
0U, // G_VAARG
|
|
0U, // G_SEXT
|
|
0U, // G_ZEXT
|
|
0U, // G_SHL
|
|
0U, // G_LSHR
|
|
0U, // G_ASHR
|
|
0U, // G_ICMP
|
|
0U, // G_FCMP
|
|
0U, // G_SELECT
|
|
0U, // G_UADDE
|
|
0U, // G_USUBE
|
|
0U, // G_SADDO
|
|
0U, // G_SSUBO
|
|
0U, // G_UMULO
|
|
0U, // G_SMULO
|
|
0U, // G_UMULH
|
|
0U, // G_SMULH
|
|
0U, // G_FADD
|
|
0U, // G_FSUB
|
|
0U, // G_FMUL
|
|
0U, // G_FMA
|
|
0U, // G_FDIV
|
|
0U, // G_FREM
|
|
0U, // G_FPOW
|
|
0U, // G_FEXP
|
|
0U, // G_FEXP2
|
|
0U, // G_FLOG
|
|
0U, // G_FLOG2
|
|
0U, // G_FNEG
|
|
0U, // G_FPEXT
|
|
0U, // G_FPTRUNC
|
|
0U, // G_FPTOSI
|
|
0U, // G_FPTOUI
|
|
0U, // G_SITOFP
|
|
0U, // G_UITOFP
|
|
0U, // G_FABS
|
|
0U, // G_GEP
|
|
0U, // G_PTR_MASK
|
|
0U, // G_BR
|
|
0U, // G_INSERT_VECTOR_ELT
|
|
0U, // G_EXTRACT_VECTOR_ELT
|
|
0U, // G_SHUFFLE_VECTOR
|
|
0U, // G_BSWAP
|
|
0U, // G_ADDRSPACE_CAST
|
|
0U, // G_BLOCK_ADDR
|
|
0U, // CFENCE8
|
|
0U, // CLRLSLDI
|
|
0U, // CLRLSLDIo
|
|
66U, // CLRLSLWI
|
|
66U, // CLRLSLWIo
|
|
32U, // CLRRDI
|
|
32U, // CLRRDIo
|
|
34U, // CLRRWI
|
|
34U, // CLRRWIo
|
|
0U, // CP_COPY_FIRST
|
|
0U, // CP_COPYx
|
|
0U, // CP_PASTE_LAST
|
|
0U, // CP_PASTEx
|
|
0U, // DCBFL
|
|
0U, // DCBFLP
|
|
0U, // DCBFx
|
|
0U, // DCBTCT
|
|
0U, // DCBTDS
|
|
0U, // DCBTSTCT
|
|
0U, // DCBTSTDS
|
|
0U, // DCBTSTT
|
|
0U, // DCBTSTx
|
|
0U, // DCBTT
|
|
0U, // DCBTx
|
|
0U, // DFLOADf32
|
|
0U, // DFLOADf64
|
|
0U, // DFSTOREf32
|
|
0U, // DFSTOREf64
|
|
0U, // EXTLDI
|
|
0U, // EXTLDIo
|
|
66U, // EXTLWI
|
|
66U, // EXTLWIo
|
|
0U, // EXTRDI
|
|
0U, // EXTRDIo
|
|
66U, // EXTRWI
|
|
66U, // EXTRWIo
|
|
66U, // INSLWI
|
|
66U, // INSLWIo
|
|
0U, // INSRDI
|
|
0U, // INSRDIo
|
|
66U, // INSRWI
|
|
66U, // INSRWIo
|
|
0U, // LAx
|
|
0U, // LIWAX
|
|
0U, // LIWZX
|
|
130U, // RLWIMIbm
|
|
130U, // RLWIMIobm
|
|
130U, // RLWINMbm
|
|
130U, // RLWINMobm
|
|
130U, // RLWNMbm
|
|
130U, // RLWNMobm
|
|
32U, // ROTRDI
|
|
32U, // ROTRDIo
|
|
34U, // ROTRWI
|
|
34U, // ROTRWIo
|
|
32U, // SLDI
|
|
32U, // SLDIo
|
|
34U, // SLWI
|
|
34U, // SLWIo
|
|
0U, // SPILLTOVSR_LD
|
|
0U, // SPILLTOVSR_LDX
|
|
0U, // SPILLTOVSR_ST
|
|
0U, // SPILLTOVSR_STX
|
|
32U, // SRDI
|
|
32U, // SRDIo
|
|
34U, // SRWI
|
|
34U, // SRWIo
|
|
0U, // STIWX
|
|
4U, // SUBI
|
|
4U, // SUBIC
|
|
4U, // SUBICo
|
|
4U, // SUBIS
|
|
0U, // SUBPCIS
|
|
0U, // XFLOADf32
|
|
0U, // XFLOADf64
|
|
0U, // XFSTOREf32
|
|
0U, // XFSTOREf64
|
|
38U, // ADD4
|
|
38U, // ADD4TLS
|
|
38U, // ADD4o
|
|
38U, // ADD8
|
|
38U, // ADD8TLS
|
|
38U, // ADD8TLS_
|
|
38U, // ADD8o
|
|
38U, // ADDC
|
|
38U, // ADDC8
|
|
38U, // ADDC8o
|
|
38U, // ADDCo
|
|
38U, // ADDE
|
|
38U, // ADDE8
|
|
38U, // ADDE8o
|
|
38U, // ADDEo
|
|
4U, // ADDI
|
|
4U, // ADDI8
|
|
4U, // ADDIC
|
|
4U, // ADDIC8
|
|
4U, // ADDICo
|
|
4U, // ADDIS
|
|
4U, // ADDIS8
|
|
0U, // ADDISdtprelHA
|
|
0U, // ADDISdtprelHA32
|
|
0U, // ADDISgotTprelHA
|
|
0U, // ADDIStlsgdHA
|
|
0U, // ADDIStlsldHA
|
|
0U, // ADDIStocHA
|
|
0U, // ADDIdtprelL
|
|
0U, // ADDIdtprelL32
|
|
0U, // ADDItlsgdL
|
|
0U, // ADDItlsgdL32
|
|
0U, // ADDItlsgdLADDR
|
|
0U, // ADDItlsgdLADDR32
|
|
0U, // ADDItlsldL
|
|
0U, // ADDItlsldL32
|
|
0U, // ADDItlsldLADDR
|
|
0U, // ADDItlsldLADDR32
|
|
0U, // ADDItocL
|
|
0U, // ADDME
|
|
0U, // ADDME8
|
|
0U, // ADDME8o
|
|
0U, // ADDMEo
|
|
0U, // ADDPCIS
|
|
0U, // ADDZE
|
|
0U, // ADDZE8
|
|
0U, // ADDZE8o
|
|
0U, // ADDZEo
|
|
0U, // ADJCALLSTACKDOWN
|
|
0U, // ADJCALLSTACKUP
|
|
38U, // AND
|
|
38U, // AND8
|
|
38U, // AND8o
|
|
38U, // ANDC
|
|
38U, // ANDC8
|
|
38U, // ANDC8o
|
|
38U, // ANDCo
|
|
8U, // ANDISo
|
|
8U, // ANDISo8
|
|
8U, // ANDIo
|
|
8U, // ANDIo8
|
|
0U, // ANDIo_1_EQ_BIT
|
|
0U, // ANDIo_1_EQ_BIT8
|
|
0U, // ANDIo_1_GT_BIT
|
|
0U, // ANDIo_1_GT_BIT8
|
|
38U, // ANDo
|
|
0U, // ATOMIC_CMP_SWAP_I16
|
|
0U, // ATOMIC_CMP_SWAP_I32
|
|
0U, // ATOMIC_CMP_SWAP_I64
|
|
0U, // ATOMIC_CMP_SWAP_I8
|
|
0U, // ATOMIC_LOAD_ADD_I16
|
|
0U, // ATOMIC_LOAD_ADD_I32
|
|
0U, // ATOMIC_LOAD_ADD_I64
|
|
0U, // ATOMIC_LOAD_ADD_I8
|
|
0U, // ATOMIC_LOAD_AND_I16
|
|
0U, // ATOMIC_LOAD_AND_I32
|
|
0U, // ATOMIC_LOAD_AND_I64
|
|
0U, // ATOMIC_LOAD_AND_I8
|
|
0U, // ATOMIC_LOAD_MAX_I16
|
|
0U, // ATOMIC_LOAD_MAX_I32
|
|
0U, // ATOMIC_LOAD_MAX_I64
|
|
0U, // ATOMIC_LOAD_MAX_I8
|
|
0U, // ATOMIC_LOAD_MIN_I16
|
|
0U, // ATOMIC_LOAD_MIN_I32
|
|
0U, // ATOMIC_LOAD_MIN_I64
|
|
0U, // ATOMIC_LOAD_MIN_I8
|
|
0U, // ATOMIC_LOAD_NAND_I16
|
|
0U, // ATOMIC_LOAD_NAND_I32
|
|
0U, // ATOMIC_LOAD_NAND_I64
|
|
0U, // ATOMIC_LOAD_NAND_I8
|
|
0U, // ATOMIC_LOAD_OR_I16
|
|
0U, // ATOMIC_LOAD_OR_I32
|
|
0U, // ATOMIC_LOAD_OR_I64
|
|
0U, // ATOMIC_LOAD_OR_I8
|
|
0U, // ATOMIC_LOAD_SUB_I16
|
|
0U, // ATOMIC_LOAD_SUB_I32
|
|
0U, // ATOMIC_LOAD_SUB_I64
|
|
0U, // ATOMIC_LOAD_SUB_I8
|
|
0U, // ATOMIC_LOAD_UMAX_I16
|
|
0U, // ATOMIC_LOAD_UMAX_I32
|
|
0U, // ATOMIC_LOAD_UMAX_I64
|
|
0U, // ATOMIC_LOAD_UMAX_I8
|
|
0U, // ATOMIC_LOAD_UMIN_I16
|
|
0U, // ATOMIC_LOAD_UMIN_I32
|
|
0U, // ATOMIC_LOAD_UMIN_I64
|
|
0U, // ATOMIC_LOAD_UMIN_I8
|
|
0U, // ATOMIC_LOAD_XOR_I16
|
|
0U, // ATOMIC_LOAD_XOR_I32
|
|
0U, // ATOMIC_LOAD_XOR_I64
|
|
0U, // ATOMIC_LOAD_XOR_I8
|
|
0U, // ATOMIC_SWAP_I16
|
|
0U, // ATOMIC_SWAP_I32
|
|
0U, // ATOMIC_SWAP_I64
|
|
0U, // ATOMIC_SWAP_I8
|
|
0U, // ATTN
|
|
0U, // B
|
|
0U, // BA
|
|
0U, // BC
|
|
0U, // BCC
|
|
0U, // BCCA
|
|
0U, // BCCCTR
|
|
0U, // BCCCTR8
|
|
0U, // BCCCTRL
|
|
0U, // BCCCTRL8
|
|
0U, // BCCL
|
|
0U, // BCCLA
|
|
0U, // BCCLR
|
|
0U, // BCCLRL
|
|
0U, // BCCTR
|
|
0U, // BCCTR8
|
|
0U, // BCCTR8n
|
|
0U, // BCCTRL
|
|
0U, // BCCTRL8
|
|
0U, // BCCTRL8n
|
|
0U, // BCCTRLn
|
|
0U, // BCCTRn
|
|
42U, // BCDCFNo
|
|
42U, // BCDCFSQo
|
|
42U, // BCDCFZo
|
|
38U, // BCDCPSGNo
|
|
0U, // BCDCTNo
|
|
0U, // BCDCTSQo
|
|
42U, // BCDCTZo
|
|
42U, // BCDSETSGNo
|
|
198U, // BCDSRo
|
|
198U, // BCDSo
|
|
198U, // BCDTRUNCo
|
|
38U, // BCDUSo
|
|
38U, // BCDUTRUNCo
|
|
0U, // BCL
|
|
0U, // BCLR
|
|
0U, // BCLRL
|
|
0U, // BCLRLn
|
|
0U, // BCLRn
|
|
0U, // BCLalways
|
|
0U, // BCLn
|
|
0U, // BCTR
|
|
0U, // BCTR8
|
|
0U, // BCTRL
|
|
0U, // BCTRL8
|
|
0U, // BCTRL8_LDinto_toc
|
|
0U, // BCn
|
|
0U, // BDNZ
|
|
0U, // BDNZ8
|
|
0U, // BDNZA
|
|
0U, // BDNZAm
|
|
0U, // BDNZAp
|
|
0U, // BDNZL
|
|
0U, // BDNZLA
|
|
0U, // BDNZLAm
|
|
0U, // BDNZLAp
|
|
0U, // BDNZLR
|
|
0U, // BDNZLR8
|
|
0U, // BDNZLRL
|
|
0U, // BDNZLRLm
|
|
0U, // BDNZLRLp
|
|
0U, // BDNZLRm
|
|
0U, // BDNZLRp
|
|
0U, // BDNZLm
|
|
0U, // BDNZLp
|
|
0U, // BDNZm
|
|
0U, // BDNZp
|
|
0U, // BDZ
|
|
0U, // BDZ8
|
|
0U, // BDZA
|
|
0U, // BDZAm
|
|
0U, // BDZAp
|
|
0U, // BDZL
|
|
0U, // BDZLA
|
|
0U, // BDZLAm
|
|
0U, // BDZLAp
|
|
0U, // BDZLR
|
|
0U, // BDZLR8
|
|
0U, // BDZLRL
|
|
0U, // BDZLRLm
|
|
0U, // BDZLRLp
|
|
0U, // BDZLRm
|
|
0U, // BDZLRp
|
|
0U, // BDZLm
|
|
0U, // BDZLp
|
|
0U, // BDZm
|
|
0U, // BDZp
|
|
0U, // BL
|
|
0U, // BL8
|
|
0U, // BL8_NOP
|
|
0U, // BL8_NOP_TLS
|
|
0U, // BL8_TLS
|
|
0U, // BL8_TLS_
|
|
0U, // BLA
|
|
0U, // BLA8
|
|
0U, // BLA8_NOP
|
|
0U, // BLR
|
|
0U, // BLR8
|
|
0U, // BLRL
|
|
0U, // BL_TLS
|
|
38U, // BPERMD
|
|
38U, // BRINC
|
|
0U, // CLRBHRB
|
|
38U, // CMPB
|
|
38U, // CMPB8
|
|
38U, // CMPD
|
|
4U, // CMPDI
|
|
38U, // CMPEQB
|
|
38U, // CMPLD
|
|
8U, // CMPLDI
|
|
38U, // CMPLW
|
|
8U, // CMPLWI
|
|
0U, // CMPRB
|
|
0U, // CMPRB8
|
|
38U, // CMPW
|
|
4U, // CMPWI
|
|
0U, // CNTLZD
|
|
0U, // CNTLZDo
|
|
0U, // CNTLZW
|
|
0U, // CNTLZW8
|
|
0U, // CNTLZW8o
|
|
0U, // CNTLZWo
|
|
0U, // CNTTZD
|
|
0U, // CNTTZDo
|
|
0U, // CNTTZW
|
|
0U, // CNTTZW8
|
|
0U, // CNTTZW8o
|
|
0U, // CNTTZWo
|
|
0U, // CP_ABORT
|
|
42U, // CP_COPY
|
|
42U, // CP_COPY8
|
|
42U, // CP_PASTE
|
|
42U, // CP_PASTE8
|
|
42U, // CP_PASTE8o
|
|
42U, // CP_PASTEo
|
|
0U, // CR6SET
|
|
0U, // CR6UNSET
|
|
38U, // CRAND
|
|
38U, // CRANDC
|
|
38U, // CREQV
|
|
38U, // CRNAND
|
|
38U, // CRNOR
|
|
38U, // CROR
|
|
38U, // CRORC
|
|
12U, // CRSET
|
|
12U, // CRUNSET
|
|
38U, // CRXOR
|
|
0U, // CTRL_DEP
|
|
0U, // DARN
|
|
0U, // DCBA
|
|
0U, // DCBF
|
|
0U, // DCBFEP
|
|
0U, // DCBI
|
|
0U, // DCBST
|
|
0U, // DCBSTEP
|
|
0U, // DCBT
|
|
0U, // DCBTEP
|
|
0U, // DCBTST
|
|
0U, // DCBTSTEP
|
|
0U, // DCBZ
|
|
0U, // DCBZEP
|
|
0U, // DCBZL
|
|
0U, // DCBZLEP
|
|
0U, // DCCCI
|
|
38U, // DIVD
|
|
38U, // DIVDE
|
|
38U, // DIVDEU
|
|
38U, // DIVDEUo
|
|
38U, // DIVDEo
|
|
38U, // DIVDU
|
|
38U, // DIVDUo
|
|
38U, // DIVDo
|
|
38U, // DIVW
|
|
38U, // DIVWE
|
|
38U, // DIVWEU
|
|
38U, // DIVWEUo
|
|
38U, // DIVWEo
|
|
38U, // DIVWU
|
|
38U, // DIVWUo
|
|
38U, // DIVWo
|
|
0U, // DSS
|
|
0U, // DSSALL
|
|
0U, // DST
|
|
0U, // DST64
|
|
0U, // DSTST
|
|
0U, // DSTST64
|
|
0U, // DSTSTT
|
|
0U, // DSTSTT64
|
|
0U, // DSTT
|
|
0U, // DSTT64
|
|
0U, // DYNALLOC
|
|
0U, // DYNALLOC8
|
|
0U, // DYNAREAOFFSET
|
|
0U, // DYNAREAOFFSET8
|
|
0U, // EFDABS
|
|
38U, // EFDADD
|
|
0U, // EFDCFS
|
|
0U, // EFDCFSF
|
|
0U, // EFDCFSI
|
|
0U, // EFDCFSID
|
|
0U, // EFDCFUF
|
|
0U, // EFDCFUI
|
|
0U, // EFDCFUID
|
|
38U, // EFDCMPEQ
|
|
38U, // EFDCMPGT
|
|
38U, // EFDCMPLT
|
|
0U, // EFDCTSF
|
|
0U, // EFDCTSI
|
|
0U, // EFDCTSIDZ
|
|
0U, // EFDCTSIZ
|
|
0U, // EFDCTUF
|
|
0U, // EFDCTUI
|
|
0U, // EFDCTUIDZ
|
|
0U, // EFDCTUIZ
|
|
38U, // EFDDIV
|
|
38U, // EFDMUL
|
|
0U, // EFDNABS
|
|
0U, // EFDNEG
|
|
38U, // EFDSUB
|
|
38U, // EFDTSTEQ
|
|
38U, // EFDTSTGT
|
|
38U, // EFDTSTLT
|
|
0U, // EFSABS
|
|
38U, // EFSADD
|
|
0U, // EFSCFD
|
|
0U, // EFSCFSF
|
|
0U, // EFSCFSI
|
|
0U, // EFSCFUF
|
|
0U, // EFSCFUI
|
|
38U, // EFSCMPEQ
|
|
38U, // EFSCMPGT
|
|
38U, // EFSCMPLT
|
|
0U, // EFSCTSF
|
|
0U, // EFSCTSI
|
|
0U, // EFSCTSIZ
|
|
0U, // EFSCTUF
|
|
0U, // EFSCTUI
|
|
0U, // EFSCTUIZ
|
|
38U, // EFSDIV
|
|
38U, // EFSMUL
|
|
0U, // EFSNABS
|
|
0U, // EFSNEG
|
|
38U, // EFSSUB
|
|
38U, // EFSTSTEQ
|
|
38U, // EFSTSTGT
|
|
38U, // EFSTSTLT
|
|
0U, // EH_SjLj_LongJmp32
|
|
0U, // EH_SjLj_LongJmp64
|
|
0U, // EH_SjLj_SetJmp32
|
|
0U, // EH_SjLj_SetJmp64
|
|
0U, // EH_SjLj_Setup
|
|
38U, // EQV
|
|
38U, // EQV8
|
|
38U, // EQV8o
|
|
38U, // EQVo
|
|
0U, // EVABS
|
|
46U, // EVADDIW
|
|
0U, // EVADDSMIAAW
|
|
0U, // EVADDSSIAAW
|
|
0U, // EVADDUMIAAW
|
|
0U, // EVADDUSIAAW
|
|
38U, // EVADDW
|
|
38U, // EVAND
|
|
38U, // EVANDC
|
|
38U, // EVCMPEQ
|
|
38U, // EVCMPGTS
|
|
38U, // EVCMPGTU
|
|
38U, // EVCMPLTS
|
|
38U, // EVCMPLTU
|
|
0U, // EVCNTLSW
|
|
0U, // EVCNTLZW
|
|
38U, // EVDIVWS
|
|
38U, // EVDIVWU
|
|
38U, // EVEQV
|
|
0U, // EVEXTSB
|
|
0U, // EVEXTSH
|
|
0U, // EVFSABS
|
|
38U, // EVFSADD
|
|
0U, // EVFSCFSF
|
|
0U, // EVFSCFSI
|
|
0U, // EVFSCFUF
|
|
0U, // EVFSCFUI
|
|
38U, // EVFSCMPEQ
|
|
38U, // EVFSCMPGT
|
|
38U, // EVFSCMPLT
|
|
0U, // EVFSCTSF
|
|
0U, // EVFSCTSI
|
|
0U, // EVFSCTSIZ
|
|
0U, // EVFSCTUF
|
|
0U, // EVFSCTUI
|
|
0U, // EVFSCTUIZ
|
|
38U, // EVFSDIV
|
|
38U, // EVFSMUL
|
|
0U, // EVFSNABS
|
|
0U, // EVFSNEG
|
|
38U, // EVFSSUB
|
|
38U, // EVFSTSTEQ
|
|
38U, // EVFSTSTGT
|
|
38U, // EVFSTSTLT
|
|
0U, // EVLDD
|
|
0U, // EVLDDX
|
|
0U, // EVLDH
|
|
0U, // EVLDHX
|
|
0U, // EVLDW
|
|
0U, // EVLDWX
|
|
0U, // EVLHHESPLAT
|
|
0U, // EVLHHESPLATX
|
|
0U, // EVLHHOSSPLAT
|
|
0U, // EVLHHOSSPLATX
|
|
0U, // EVLHHOUSPLAT
|
|
0U, // EVLHHOUSPLATX
|
|
0U, // EVLWHE
|
|
0U, // EVLWHEX
|
|
0U, // EVLWHOS
|
|
0U, // EVLWHOSX
|
|
0U, // EVLWHOU
|
|
0U, // EVLWHOUX
|
|
0U, // EVLWHSPLAT
|
|
0U, // EVLWHSPLATX
|
|
0U, // EVLWWSPLAT
|
|
0U, // EVLWWSPLATX
|
|
38U, // EVMERGEHI
|
|
38U, // EVMERGEHILO
|
|
38U, // EVMERGELO
|
|
38U, // EVMERGELOHI
|
|
38U, // EVMHEGSMFAA
|
|
38U, // EVMHEGSMFAN
|
|
38U, // EVMHEGSMIAA
|
|
38U, // EVMHEGSMIAN
|
|
38U, // EVMHEGUMIAA
|
|
38U, // EVMHEGUMIAN
|
|
38U, // EVMHESMF
|
|
38U, // EVMHESMFA
|
|
38U, // EVMHESMFAAW
|
|
38U, // EVMHESMFANW
|
|
38U, // EVMHESMI
|
|
38U, // EVMHESMIA
|
|
38U, // EVMHESMIAAW
|
|
38U, // EVMHESMIANW
|
|
38U, // EVMHESSF
|
|
38U, // EVMHESSFA
|
|
38U, // EVMHESSFAAW
|
|
38U, // EVMHESSFANW
|
|
38U, // EVMHESSIAAW
|
|
38U, // EVMHESSIANW
|
|
38U, // EVMHEUMI
|
|
38U, // EVMHEUMIA
|
|
38U, // EVMHEUMIAAW
|
|
38U, // EVMHEUMIANW
|
|
38U, // EVMHEUSIAAW
|
|
38U, // EVMHEUSIANW
|
|
38U, // EVMHOGSMFAA
|
|
38U, // EVMHOGSMFAN
|
|
38U, // EVMHOGSMIAA
|
|
38U, // EVMHOGSMIAN
|
|
38U, // EVMHOGUMIAA
|
|
38U, // EVMHOGUMIAN
|
|
38U, // EVMHOSMF
|
|
38U, // EVMHOSMFA
|
|
38U, // EVMHOSMFAAW
|
|
38U, // EVMHOSMFANW
|
|
38U, // EVMHOSMI
|
|
38U, // EVMHOSMIA
|
|
38U, // EVMHOSMIAAW
|
|
38U, // EVMHOSMIANW
|
|
38U, // EVMHOSSF
|
|
38U, // EVMHOSSFA
|
|
38U, // EVMHOSSFAAW
|
|
38U, // EVMHOSSFANW
|
|
38U, // EVMHOSSIAAW
|
|
38U, // EVMHOSSIANW
|
|
38U, // EVMHOUMI
|
|
38U, // EVMHOUMIA
|
|
38U, // EVMHOUMIAAW
|
|
38U, // EVMHOUMIANW
|
|
38U, // EVMHOUSIAAW
|
|
38U, // EVMHOUSIANW
|
|
0U, // EVMRA
|
|
38U, // EVMWHSMF
|
|
38U, // EVMWHSMFA
|
|
38U, // EVMWHSMI
|
|
38U, // EVMWHSMIA
|
|
38U, // EVMWHSSF
|
|
38U, // EVMWHSSFA
|
|
38U, // EVMWHUMI
|
|
38U, // EVMWHUMIA
|
|
38U, // EVMWLSMIAAW
|
|
38U, // EVMWLSMIANW
|
|
38U, // EVMWLSSIAAW
|
|
38U, // EVMWLSSIANW
|
|
38U, // EVMWLUMI
|
|
38U, // EVMWLUMIA
|
|
38U, // EVMWLUMIAAW
|
|
38U, // EVMWLUMIANW
|
|
38U, // EVMWLUSIAAW
|
|
38U, // EVMWLUSIANW
|
|
38U, // EVMWSMF
|
|
38U, // EVMWSMFA
|
|
38U, // EVMWSMFAA
|
|
38U, // EVMWSMFAN
|
|
38U, // EVMWSMI
|
|
38U, // EVMWSMIA
|
|
38U, // EVMWSMIAA
|
|
38U, // EVMWSMIAN
|
|
38U, // EVMWSSF
|
|
38U, // EVMWSSFA
|
|
38U, // EVMWSSFAA
|
|
38U, // EVMWSSFAN
|
|
38U, // EVMWUMI
|
|
38U, // EVMWUMIA
|
|
38U, // EVMWUMIAA
|
|
38U, // EVMWUMIAN
|
|
38U, // EVNAND
|
|
0U, // EVNEG
|
|
38U, // EVNOR
|
|
38U, // EVOR
|
|
38U, // EVORC
|
|
38U, // EVRLW
|
|
34U, // EVRLWI
|
|
0U, // EVRNDW
|
|
0U, // EVSEL
|
|
38U, // EVSLW
|
|
34U, // EVSLWI
|
|
0U, // EVSPLATFI
|
|
0U, // EVSPLATI
|
|
34U, // EVSRWIS
|
|
34U, // EVSRWIU
|
|
38U, // EVSRWS
|
|
38U, // EVSRWU
|
|
0U, // EVSTDD
|
|
0U, // EVSTDDX
|
|
0U, // EVSTDH
|
|
0U, // EVSTDHX
|
|
0U, // EVSTDW
|
|
0U, // EVSTDWX
|
|
0U, // EVSTWHE
|
|
0U, // EVSTWHEX
|
|
0U, // EVSTWHO
|
|
0U, // EVSTWHOX
|
|
0U, // EVSTWWE
|
|
0U, // EVSTWWEX
|
|
0U, // EVSTWWO
|
|
0U, // EVSTWWOX
|
|
0U, // EVSUBFSMIAAW
|
|
0U, // EVSUBFSSIAAW
|
|
0U, // EVSUBFUMIAAW
|
|
0U, // EVSUBFUSIAAW
|
|
38U, // EVSUBFW
|
|
0U, // EVSUBIFW
|
|
38U, // EVXOR
|
|
0U, // EXTSB
|
|
0U, // EXTSB8
|
|
0U, // EXTSB8_32_64
|
|
0U, // EXTSB8o
|
|
0U, // EXTSBo
|
|
0U, // EXTSH
|
|
0U, // EXTSH8
|
|
0U, // EXTSH8_32_64
|
|
0U, // EXTSH8o
|
|
0U, // EXTSHo
|
|
0U, // EXTSW
|
|
32U, // EXTSWSLI
|
|
32U, // EXTSWSLIo
|
|
0U, // EXTSW_32
|
|
0U, // EXTSW_32_64
|
|
0U, // EXTSW_32_64o
|
|
0U, // EXTSWo
|
|
0U, // EnforceIEIO
|
|
0U, // FABSD
|
|
0U, // FABSDo
|
|
0U, // FABSS
|
|
0U, // FABSSo
|
|
38U, // FADD
|
|
38U, // FADDS
|
|
38U, // FADDSo
|
|
38U, // FADDo
|
|
0U, // FADDrtz
|
|
0U, // FCFID
|
|
0U, // FCFIDS
|
|
0U, // FCFIDSo
|
|
0U, // FCFIDU
|
|
0U, // FCFIDUS
|
|
0U, // FCFIDUSo
|
|
0U, // FCFIDUo
|
|
0U, // FCFIDo
|
|
38U, // FCMPUD
|
|
38U, // FCMPUS
|
|
38U, // FCPSGND
|
|
38U, // FCPSGNDo
|
|
38U, // FCPSGNS
|
|
38U, // FCPSGNSo
|
|
0U, // FCTID
|
|
0U, // FCTIDU
|
|
0U, // FCTIDUZ
|
|
0U, // FCTIDUZo
|
|
0U, // FCTIDUo
|
|
0U, // FCTIDZ
|
|
0U, // FCTIDZo
|
|
0U, // FCTIDo
|
|
0U, // FCTIW
|
|
0U, // FCTIWU
|
|
0U, // FCTIWUZ
|
|
0U, // FCTIWUZo
|
|
0U, // FCTIWUo
|
|
0U, // FCTIWZ
|
|
0U, // FCTIWZo
|
|
0U, // FCTIWo
|
|
38U, // FDIV
|
|
38U, // FDIVS
|
|
38U, // FDIVSo
|
|
38U, // FDIVo
|
|
134U, // FMADD
|
|
134U, // FMADDS
|
|
134U, // FMADDSo
|
|
134U, // FMADDo
|
|
0U, // FMR
|
|
0U, // FMRo
|
|
134U, // FMSUB
|
|
134U, // FMSUBS
|
|
134U, // FMSUBSo
|
|
134U, // FMSUBo
|
|
38U, // FMUL
|
|
38U, // FMULS
|
|
38U, // FMULSo
|
|
38U, // FMULo
|
|
0U, // FNABSD
|
|
0U, // FNABSDo
|
|
0U, // FNABSS
|
|
0U, // FNABSSo
|
|
0U, // FNEGD
|
|
0U, // FNEGDo
|
|
0U, // FNEGS
|
|
0U, // FNEGSo
|
|
134U, // FNMADD
|
|
134U, // FNMADDS
|
|
134U, // FNMADDSo
|
|
134U, // FNMADDo
|
|
134U, // FNMSUB
|
|
134U, // FNMSUBS
|
|
134U, // FNMSUBSo
|
|
134U, // FNMSUBo
|
|
0U, // FRE
|
|
0U, // FRES
|
|
0U, // FRESo
|
|
0U, // FREo
|
|
0U, // FRIMD
|
|
0U, // FRIMDo
|
|
0U, // FRIMS
|
|
0U, // FRIMSo
|
|
0U, // FRIND
|
|
0U, // FRINDo
|
|
0U, // FRINS
|
|
0U, // FRINSo
|
|
0U, // FRIPD
|
|
0U, // FRIPDo
|
|
0U, // FRIPS
|
|
0U, // FRIPSo
|
|
0U, // FRIZD
|
|
0U, // FRIZDo
|
|
0U, // FRIZS
|
|
0U, // FRIZSo
|
|
0U, // FRSP
|
|
0U, // FRSPo
|
|
0U, // FRSQRTE
|
|
0U, // FRSQRTES
|
|
0U, // FRSQRTESo
|
|
0U, // FRSQRTEo
|
|
134U, // FSELD
|
|
134U, // FSELDo
|
|
134U, // FSELS
|
|
134U, // FSELSo
|
|
0U, // FSQRT
|
|
0U, // FSQRTS
|
|
0U, // FSQRTSo
|
|
0U, // FSQRTo
|
|
38U, // FSUB
|
|
38U, // FSUBS
|
|
38U, // FSUBSo
|
|
38U, // FSUBo
|
|
38U, // FTDIV
|
|
0U, // FTSQRT
|
|
0U, // GETtlsADDR
|
|
0U, // GETtlsADDR32
|
|
0U, // GETtlsldADDR
|
|
0U, // GETtlsldADDR32
|
|
0U, // HRFID
|
|
0U, // ICBI
|
|
0U, // ICBIEP
|
|
0U, // ICBLC
|
|
0U, // ICBLQ
|
|
0U, // ICBT
|
|
0U, // ICBTLS
|
|
0U, // ICCCI
|
|
134U, // ISEL
|
|
134U, // ISEL8
|
|
0U, // ISYNC
|
|
0U, // LA
|
|
0U, // LBARX
|
|
0U, // LBARXL
|
|
0U, // LBEPX
|
|
0U, // LBZ
|
|
0U, // LBZ8
|
|
38U, // LBZCIX
|
|
0U, // LBZU
|
|
0U, // LBZU8
|
|
0U, // LBZUX
|
|
0U, // LBZUX8
|
|
0U, // LBZX
|
|
0U, // LBZX8
|
|
38U, // LBZXTLS
|
|
38U, // LBZXTLS_
|
|
38U, // LBZXTLS_32
|
|
0U, // LD
|
|
0U, // LDARX
|
|
0U, // LDARXL
|
|
34U, // LDAT
|
|
0U, // LDBRX
|
|
38U, // LDCIX
|
|
0U, // LDMX
|
|
0U, // LDU
|
|
0U, // LDUX
|
|
0U, // LDX
|
|
38U, // LDXTLS
|
|
38U, // LDXTLS_
|
|
0U, // LDgotTprelL
|
|
0U, // LDgotTprelL32
|
|
0U, // LDtoc
|
|
0U, // LDtocBA
|
|
0U, // LDtocCPT
|
|
0U, // LDtocJTI
|
|
0U, // LDtocL
|
|
0U, // LFD
|
|
0U, // LFDEPX
|
|
0U, // LFDU
|
|
0U, // LFDUX
|
|
0U, // LFDX
|
|
0U, // LFIWAX
|
|
0U, // LFIWZX
|
|
0U, // LFS
|
|
0U, // LFSU
|
|
0U, // LFSUX
|
|
0U, // LFSX
|
|
0U, // LHA
|
|
0U, // LHA8
|
|
0U, // LHARX
|
|
0U, // LHARXL
|
|
0U, // LHAU
|
|
0U, // LHAU8
|
|
0U, // LHAUX
|
|
0U, // LHAUX8
|
|
0U, // LHAX
|
|
0U, // LHAX8
|
|
0U, // LHBRX
|
|
0U, // LHBRX8
|
|
0U, // LHEPX
|
|
0U, // LHZ
|
|
0U, // LHZ8
|
|
38U, // LHZCIX
|
|
0U, // LHZU
|
|
0U, // LHZU8
|
|
0U, // LHZUX
|
|
0U, // LHZUX8
|
|
0U, // LHZX
|
|
0U, // LHZX8
|
|
38U, // LHZXTLS
|
|
38U, // LHZXTLS_
|
|
38U, // LHZXTLS_32
|
|
0U, // LI
|
|
0U, // LI8
|
|
0U, // LIS
|
|
0U, // LIS8
|
|
0U, // LMW
|
|
34U, // LSWI
|
|
0U, // LVEBX
|
|
0U, // LVEHX
|
|
0U, // LVEWX
|
|
0U, // LVSL
|
|
0U, // LVSR
|
|
0U, // LVX
|
|
0U, // LVXL
|
|
0U, // LWA
|
|
0U, // LWARX
|
|
0U, // LWARXL
|
|
34U, // LWAT
|
|
0U, // LWAUX
|
|
0U, // LWAX
|
|
0U, // LWAX_32
|
|
0U, // LWA_32
|
|
0U, // LWBRX
|
|
0U, // LWBRX8
|
|
0U, // LWEPX
|
|
0U, // LWZ
|
|
0U, // LWZ8
|
|
38U, // LWZCIX
|
|
0U, // LWZU
|
|
0U, // LWZU8
|
|
0U, // LWZUX
|
|
0U, // LWZUX8
|
|
0U, // LWZX
|
|
0U, // LWZX8
|
|
38U, // LWZXTLS
|
|
38U, // LWZXTLS_
|
|
38U, // LWZXTLS_32
|
|
0U, // LWZtoc
|
|
0U, // LXSD
|
|
0U, // LXSDX
|
|
0U, // LXSIBZX
|
|
0U, // LXSIHZX
|
|
0U, // LXSIWAX
|
|
0U, // LXSIWZX
|
|
0U, // LXSSP
|
|
0U, // LXSSPX
|
|
0U, // LXV
|
|
0U, // LXVB16X
|
|
0U, // LXVD2X
|
|
0U, // LXVDSX
|
|
0U, // LXVH8X
|
|
38U, // LXVL
|
|
38U, // LXVLL
|
|
0U, // LXVW4X
|
|
0U, // LXVWSX
|
|
0U, // LXVX
|
|
134U, // MADDHD
|
|
134U, // MADDHDU
|
|
134U, // MADDLD
|
|
0U, // MBAR
|
|
0U, // MCRF
|
|
0U, // MCRFS
|
|
0U, // MCRXRX
|
|
0U, // MFBHRBE
|
|
0U, // MFCR
|
|
0U, // MFCR8
|
|
0U, // MFCTR
|
|
0U, // MFCTR8
|
|
0U, // MFDCR
|
|
0U, // MFFS
|
|
0U, // MFFSCDRN
|
|
0U, // MFFSCDRNI
|
|
0U, // MFFSCE
|
|
0U, // MFFSCRN
|
|
0U, // MFFSCRNI
|
|
0U, // MFFSL
|
|
0U, // MFFSo
|
|
0U, // MFLR
|
|
0U, // MFLR8
|
|
0U, // MFMSR
|
|
0U, // MFOCRF
|
|
0U, // MFOCRF8
|
|
0U, // MFPMR
|
|
0U, // MFSPR
|
|
0U, // MFSPR8
|
|
0U, // MFSR
|
|
0U, // MFSRIN
|
|
0U, // MFTB
|
|
0U, // MFTB8
|
|
0U, // MFVRD
|
|
0U, // MFVRSAVE
|
|
0U, // MFVRSAVEv
|
|
0U, // MFVSCR
|
|
0U, // MFVSRD
|
|
0U, // MFVSRLD
|
|
0U, // MFVSRWZ
|
|
38U, // MODSD
|
|
38U, // MODSW
|
|
38U, // MODUD
|
|
38U, // MODUW
|
|
0U, // MSGSYNC
|
|
0U, // MSYNC
|
|
0U, // MTCRF
|
|
0U, // MTCRF8
|
|
0U, // MTCTR
|
|
0U, // MTCTR8
|
|
0U, // MTCTR8loop
|
|
0U, // MTCTRloop
|
|
0U, // MTDCR
|
|
0U, // MTFSB0
|
|
0U, // MTFSB1
|
|
134U, // MTFSF
|
|
38U, // MTFSFI
|
|
38U, // MTFSFIo
|
|
0U, // MTFSFb
|
|
134U, // MTFSFo
|
|
0U, // MTLR
|
|
0U, // MTLR8
|
|
0U, // MTMSR
|
|
0U, // MTMSRD
|
|
0U, // MTOCRF
|
|
0U, // MTOCRF8
|
|
0U, // MTPMR
|
|
0U, // MTSPR
|
|
0U, // MTSPR8
|
|
0U, // MTSR
|
|
0U, // MTSRIN
|
|
0U, // MTVRSAVE
|
|
0U, // MTVRSAVEv
|
|
0U, // MTVSCR
|
|
0U, // MTVSRD
|
|
38U, // MTVSRDD
|
|
0U, // MTVSRWA
|
|
0U, // MTVSRWS
|
|
0U, // MTVSRWZ
|
|
38U, // MULHD
|
|
38U, // MULHDU
|
|
38U, // MULHDUo
|
|
38U, // MULHDo
|
|
38U, // MULHW
|
|
38U, // MULHWU
|
|
38U, // MULHWUo
|
|
38U, // MULHWo
|
|
38U, // MULLD
|
|
38U, // MULLDo
|
|
4U, // MULLI
|
|
4U, // MULLI8
|
|
38U, // MULLW
|
|
38U, // MULLWo
|
|
0U, // MoveGOTtoLR
|
|
0U, // MovePCtoLR
|
|
0U, // MovePCtoLR8
|
|
38U, // NAND
|
|
38U, // NAND8
|
|
38U, // NAND8o
|
|
38U, // NANDo
|
|
0U, // NAP
|
|
0U, // NEG
|
|
0U, // NEG8
|
|
0U, // NEG8o
|
|
0U, // NEGo
|
|
0U, // NOP
|
|
0U, // NOP_GT_PWR6
|
|
0U, // NOP_GT_PWR7
|
|
38U, // NOR
|
|
38U, // NOR8
|
|
38U, // NOR8o
|
|
38U, // NORo
|
|
38U, // OR
|
|
38U, // OR8
|
|
38U, // OR8o
|
|
38U, // ORC
|
|
38U, // ORC8
|
|
38U, // ORC8o
|
|
38U, // ORCo
|
|
8U, // ORI
|
|
8U, // ORI8
|
|
8U, // ORIS
|
|
8U, // ORIS8
|
|
38U, // ORo
|
|
0U, // POPCNTB
|
|
0U, // POPCNTD
|
|
0U, // POPCNTW
|
|
0U, // PPC32GOT
|
|
0U, // PPC32PICGOT
|
|
262U, // QVALIGNI
|
|
262U, // QVALIGNIb
|
|
262U, // QVALIGNIs
|
|
16U, // QVESPLATI
|
|
16U, // QVESPLATIb
|
|
16U, // QVESPLATIs
|
|
0U, // QVFABS
|
|
0U, // QVFABSs
|
|
38U, // QVFADD
|
|
38U, // QVFADDS
|
|
38U, // QVFADDSs
|
|
0U, // QVFCFID
|
|
0U, // QVFCFIDS
|
|
0U, // QVFCFIDU
|
|
0U, // QVFCFIDUS
|
|
0U, // QVFCFIDb
|
|
38U, // QVFCMPEQ
|
|
38U, // QVFCMPEQb
|
|
38U, // QVFCMPEQbs
|
|
38U, // QVFCMPGT
|
|
38U, // QVFCMPGTb
|
|
38U, // QVFCMPGTbs
|
|
38U, // QVFCMPLT
|
|
38U, // QVFCMPLTb
|
|
38U, // QVFCMPLTbs
|
|
38U, // QVFCPSGN
|
|
38U, // QVFCPSGNs
|
|
0U, // QVFCTID
|
|
0U, // QVFCTIDU
|
|
0U, // QVFCTIDUZ
|
|
0U, // QVFCTIDZ
|
|
0U, // QVFCTIDb
|
|
0U, // QVFCTIW
|
|
0U, // QVFCTIWU
|
|
0U, // QVFCTIWUZ
|
|
0U, // QVFCTIWZ
|
|
326U, // QVFLOGICAL
|
|
326U, // QVFLOGICALb
|
|
326U, // QVFLOGICALs
|
|
18U, // QVFMADD
|
|
18U, // QVFMADDS
|
|
18U, // QVFMADDSs
|
|
0U, // QVFMR
|
|
0U, // QVFMRb
|
|
0U, // QVFMRs
|
|
18U, // QVFMSUB
|
|
18U, // QVFMSUBS
|
|
18U, // QVFMSUBSs
|
|
38U, // QVFMUL
|
|
38U, // QVFMULS
|
|
38U, // QVFMULSs
|
|
0U, // QVFNABS
|
|
0U, // QVFNABSs
|
|
0U, // QVFNEG
|
|
0U, // QVFNEGs
|
|
18U, // QVFNMADD
|
|
18U, // QVFNMADDS
|
|
18U, // QVFNMADDSs
|
|
18U, // QVFNMSUB
|
|
18U, // QVFNMSUBS
|
|
18U, // QVFNMSUBSs
|
|
134U, // QVFPERM
|
|
134U, // QVFPERMs
|
|
0U, // QVFRE
|
|
0U, // QVFRES
|
|
0U, // QVFRESs
|
|
0U, // QVFRIM
|
|
0U, // QVFRIMs
|
|
0U, // QVFRIN
|
|
0U, // QVFRINs
|
|
0U, // QVFRIP
|
|
0U, // QVFRIPs
|
|
0U, // QVFRIZ
|
|
0U, // QVFRIZs
|
|
0U, // QVFRSP
|
|
0U, // QVFRSPs
|
|
0U, // QVFRSQRTE
|
|
0U, // QVFRSQRTES
|
|
0U, // QVFRSQRTESs
|
|
18U, // QVFSEL
|
|
18U, // QVFSELb
|
|
18U, // QVFSELbb
|
|
18U, // QVFSELbs
|
|
38U, // QVFSUB
|
|
38U, // QVFSUBS
|
|
38U, // QVFSUBSs
|
|
38U, // QVFTSTNAN
|
|
38U, // QVFTSTNANb
|
|
38U, // QVFTSTNANbs
|
|
18U, // QVFXMADD
|
|
18U, // QVFXMADDS
|
|
38U, // QVFXMUL
|
|
38U, // QVFXMULS
|
|
18U, // QVFXXCPNMADD
|
|
18U, // QVFXXCPNMADDS
|
|
18U, // QVFXXMADD
|
|
18U, // QVFXXMADDS
|
|
18U, // QVFXXNPMADD
|
|
18U, // QVFXXNPMADDS
|
|
0U, // QVGPCI
|
|
0U, // QVLFCDUX
|
|
0U, // QVLFCDUXA
|
|
0U, // QVLFCDX
|
|
0U, // QVLFCDXA
|
|
0U, // QVLFCSUX
|
|
0U, // QVLFCSUXA
|
|
0U, // QVLFCSX
|
|
0U, // QVLFCSXA
|
|
0U, // QVLFCSXs
|
|
0U, // QVLFDUX
|
|
0U, // QVLFDUXA
|
|
0U, // QVLFDX
|
|
0U, // QVLFDXA
|
|
0U, // QVLFDXb
|
|
0U, // QVLFIWAX
|
|
0U, // QVLFIWAXA
|
|
0U, // QVLFIWZX
|
|
0U, // QVLFIWZXA
|
|
0U, // QVLFSUX
|
|
0U, // QVLFSUXA
|
|
0U, // QVLFSX
|
|
0U, // QVLFSXA
|
|
0U, // QVLFSXb
|
|
0U, // QVLFSXs
|
|
0U, // QVLPCLDX
|
|
0U, // QVLPCLSX
|
|
0U, // QVLPCLSXint
|
|
0U, // QVLPCRDX
|
|
0U, // QVLPCRSX
|
|
0U, // QVSTFCDUX
|
|
0U, // QVSTFCDUXA
|
|
0U, // QVSTFCDUXI
|
|
0U, // QVSTFCDUXIA
|
|
0U, // QVSTFCDX
|
|
0U, // QVSTFCDXA
|
|
0U, // QVSTFCDXI
|
|
0U, // QVSTFCDXIA
|
|
0U, // QVSTFCSUX
|
|
0U, // QVSTFCSUXA
|
|
0U, // QVSTFCSUXI
|
|
0U, // QVSTFCSUXIA
|
|
0U, // QVSTFCSX
|
|
0U, // QVSTFCSXA
|
|
0U, // QVSTFCSXI
|
|
0U, // QVSTFCSXIA
|
|
0U, // QVSTFCSXs
|
|
0U, // QVSTFDUX
|
|
0U, // QVSTFDUXA
|
|
0U, // QVSTFDUXI
|
|
0U, // QVSTFDUXIA
|
|
0U, // QVSTFDX
|
|
0U, // QVSTFDXA
|
|
0U, // QVSTFDXI
|
|
0U, // QVSTFDXIA
|
|
0U, // QVSTFDXb
|
|
0U, // QVSTFIWX
|
|
0U, // QVSTFIWXA
|
|
0U, // QVSTFSUX
|
|
0U, // QVSTFSUXA
|
|
0U, // QVSTFSUXI
|
|
0U, // QVSTFSUXIA
|
|
0U, // QVSTFSUXs
|
|
0U, // QVSTFSX
|
|
0U, // QVSTFSXA
|
|
0U, // QVSTFSXI
|
|
0U, // QVSTFSXIA
|
|
0U, // QVSTFSXs
|
|
0U, // RESTORE_CR
|
|
0U, // RESTORE_CRBIT
|
|
0U, // RESTORE_VRSAVE
|
|
0U, // RFCI
|
|
0U, // RFDI
|
|
0U, // RFEBB
|
|
0U, // RFI
|
|
0U, // RFID
|
|
0U, // RFMCI
|
|
6U, // RLDCL
|
|
6U, // RLDCLo
|
|
6U, // RLDCR
|
|
6U, // RLDCRo
|
|
0U, // RLDIC
|
|
0U, // RLDICL
|
|
0U, // RLDICL_32
|
|
0U, // RLDICL_32_64
|
|
0U, // RLDICL_32o
|
|
0U, // RLDICLo
|
|
0U, // RLDICR
|
|
0U, // RLDICR_32
|
|
0U, // RLDICRo
|
|
0U, // RLDICo
|
|
0U, // RLDIMI
|
|
0U, // RLDIMIo
|
|
0U, // RLWIMI
|
|
0U, // RLWIMI8
|
|
0U, // RLWIMI8o
|
|
0U, // RLWIMIo
|
|
578U, // RLWINM
|
|
578U, // RLWINM8
|
|
578U, // RLWINM8o
|
|
578U, // RLWINMo
|
|
582U, // RLWNM
|
|
582U, // RLWNM8
|
|
582U, // RLWNM8o
|
|
582U, // RLWNMo
|
|
0U, // ReadTB
|
|
0U, // SC
|
|
0U, // SELECT_CC_F16
|
|
0U, // SELECT_CC_F4
|
|
0U, // SELECT_CC_F8
|
|
0U, // SELECT_CC_I4
|
|
0U, // SELECT_CC_I8
|
|
0U, // SELECT_CC_QBRC
|
|
0U, // SELECT_CC_QFRC
|
|
0U, // SELECT_CC_QSRC
|
|
0U, // SELECT_CC_SPE
|
|
0U, // SELECT_CC_SPE4
|
|
0U, // SELECT_CC_VRRC
|
|
0U, // SELECT_CC_VSFRC
|
|
0U, // SELECT_CC_VSRC
|
|
0U, // SELECT_CC_VSSRC
|
|
0U, // SELECT_F16
|
|
0U, // SELECT_F4
|
|
0U, // SELECT_F8
|
|
0U, // SELECT_I4
|
|
0U, // SELECT_I8
|
|
0U, // SELECT_QBRC
|
|
0U, // SELECT_QFRC
|
|
0U, // SELECT_QSRC
|
|
0U, // SELECT_SPE
|
|
0U, // SELECT_SPE4
|
|
0U, // SELECT_VRRC
|
|
0U, // SELECT_VSFRC
|
|
0U, // SELECT_VSRC
|
|
0U, // SELECT_VSSRC
|
|
0U, // SETB
|
|
0U, // SLBIA
|
|
0U, // SLBIE
|
|
0U, // SLBIEG
|
|
0U, // SLBMFEE
|
|
0U, // SLBMFEV
|
|
0U, // SLBMTE
|
|
0U, // SLBSYNC
|
|
38U, // SLD
|
|
38U, // SLDo
|
|
38U, // SLW
|
|
38U, // SLW8
|
|
38U, // SLW8o
|
|
38U, // SLWo
|
|
0U, // SPELWZ
|
|
0U, // SPELWZX
|
|
0U, // SPESTW
|
|
0U, // SPESTWX
|
|
0U, // SPILL_CR
|
|
0U, // SPILL_CRBIT
|
|
0U, // SPILL_VRSAVE
|
|
38U, // SRAD
|
|
32U, // SRADI
|
|
32U, // SRADI_32
|
|
32U, // SRADIo
|
|
38U, // SRADo
|
|
38U, // SRAW
|
|
34U, // SRAWI
|
|
34U, // SRAWIo
|
|
38U, // SRAWo
|
|
38U, // SRD
|
|
38U, // SRDo
|
|
38U, // SRW
|
|
38U, // SRW8
|
|
38U, // SRW8o
|
|
38U, // SRWo
|
|
0U, // STB
|
|
0U, // STB8
|
|
38U, // STBCIX
|
|
0U, // STBCX
|
|
0U, // STBEPX
|
|
0U, // STBU
|
|
0U, // STBU8
|
|
0U, // STBUX
|
|
0U, // STBUX8
|
|
0U, // STBX
|
|
0U, // STBX8
|
|
38U, // STBXTLS
|
|
38U, // STBXTLS_
|
|
38U, // STBXTLS_32
|
|
0U, // STD
|
|
34U, // STDAT
|
|
0U, // STDBRX
|
|
38U, // STDCIX
|
|
0U, // STDCX
|
|
0U, // STDU
|
|
0U, // STDUX
|
|
0U, // STDX
|
|
38U, // STDXTLS
|
|
38U, // STDXTLS_
|
|
0U, // STFD
|
|
0U, // STFDEPX
|
|
0U, // STFDU
|
|
0U, // STFDUX
|
|
0U, // STFDX
|
|
0U, // STFIWX
|
|
0U, // STFS
|
|
0U, // STFSU
|
|
0U, // STFSUX
|
|
0U, // STFSX
|
|
0U, // STH
|
|
0U, // STH8
|
|
0U, // STHBRX
|
|
38U, // STHCIX
|
|
0U, // STHCX
|
|
0U, // STHEPX
|
|
0U, // STHU
|
|
0U, // STHU8
|
|
0U, // STHUX
|
|
0U, // STHUX8
|
|
0U, // STHX
|
|
0U, // STHX8
|
|
38U, // STHXTLS
|
|
38U, // STHXTLS_
|
|
38U, // STHXTLS_32
|
|
0U, // STMW
|
|
0U, // STOP
|
|
34U, // STSWI
|
|
0U, // STVEBX
|
|
0U, // STVEHX
|
|
0U, // STVEWX
|
|
0U, // STVX
|
|
0U, // STVXL
|
|
0U, // STW
|
|
0U, // STW8
|
|
34U, // STWAT
|
|
0U, // STWBRX
|
|
38U, // STWCIX
|
|
0U, // STWCX
|
|
0U, // STWEPX
|
|
0U, // STWU
|
|
0U, // STWU8
|
|
0U, // STWUX
|
|
0U, // STWUX8
|
|
0U, // STWX
|
|
0U, // STWX8
|
|
38U, // STWXTLS
|
|
38U, // STWXTLS_
|
|
38U, // STWXTLS_32
|
|
0U, // STXSD
|
|
0U, // STXSDX
|
|
0U, // STXSIBX
|
|
0U, // STXSIBXv
|
|
0U, // STXSIHX
|
|
0U, // STXSIHXv
|
|
0U, // STXSIWX
|
|
0U, // STXSSP
|
|
0U, // STXSSPX
|
|
0U, // STXV
|
|
0U, // STXVB16X
|
|
0U, // STXVD2X
|
|
0U, // STXVH8X
|
|
38U, // STXVL
|
|
38U, // STXVLL
|
|
0U, // STXVW4X
|
|
0U, // STXVX
|
|
38U, // SUBF
|
|
38U, // SUBF8
|
|
38U, // SUBF8o
|
|
38U, // SUBFC
|
|
38U, // SUBFC8
|
|
38U, // SUBFC8o
|
|
38U, // SUBFCo
|
|
38U, // SUBFE
|
|
38U, // SUBFE8
|
|
38U, // SUBFE8o
|
|
38U, // SUBFEo
|
|
4U, // SUBFIC
|
|
4U, // SUBFIC8
|
|
0U, // SUBFME
|
|
0U, // SUBFME8
|
|
0U, // SUBFME8o
|
|
0U, // SUBFMEo
|
|
0U, // SUBFZE
|
|
0U, // SUBFZE8
|
|
0U, // SUBFZE8o
|
|
0U, // SUBFZEo
|
|
38U, // SUBFo
|
|
0U, // SYNC
|
|
0U, // TABORT
|
|
0U, // TABORTDC
|
|
0U, // TABORTDCI
|
|
0U, // TABORTWC
|
|
0U, // TABORTWCI
|
|
0U, // TAILB
|
|
0U, // TAILB8
|
|
0U, // TAILBA
|
|
0U, // TAILBA8
|
|
0U, // TAILBCTR
|
|
0U, // TAILBCTR8
|
|
0U, // TBEGIN
|
|
0U, // TCHECK
|
|
0U, // TCHECK_RET
|
|
0U, // TCRETURNai
|
|
0U, // TCRETURNai8
|
|
0U, // TCRETURNdi
|
|
0U, // TCRETURNdi8
|
|
0U, // TCRETURNri
|
|
0U, // TCRETURNri8
|
|
38U, // TD
|
|
4U, // TDI
|
|
0U, // TEND
|
|
0U, // TLBIA
|
|
0U, // TLBIE
|
|
0U, // TLBIEL
|
|
0U, // TLBIVAX
|
|
0U, // TLBLD
|
|
0U, // TLBLI
|
|
0U, // TLBRE
|
|
38U, // TLBRE2
|
|
0U, // TLBSX
|
|
38U, // TLBSX2
|
|
38U, // TLBSX2D
|
|
0U, // TLBSYNC
|
|
0U, // TLBWE
|
|
38U, // TLBWE2
|
|
0U, // TRAP
|
|
0U, // TRECHKPT
|
|
0U, // TRECLAIM
|
|
0U, // TSR
|
|
38U, // TW
|
|
4U, // TWI
|
|
0U, // UPDATE_VRSAVE
|
|
0U, // UpdateGBR
|
|
38U, // VABSDUB
|
|
38U, // VABSDUH
|
|
38U, // VABSDUW
|
|
38U, // VADDCUQ
|
|
38U, // VADDCUW
|
|
134U, // VADDECUQ
|
|
134U, // VADDEUQM
|
|
38U, // VADDFP
|
|
38U, // VADDSBS
|
|
38U, // VADDSHS
|
|
38U, // VADDSWS
|
|
38U, // VADDUBM
|
|
38U, // VADDUBS
|
|
38U, // VADDUDM
|
|
38U, // VADDUHM
|
|
38U, // VADDUHS
|
|
38U, // VADDUQM
|
|
38U, // VADDUWM
|
|
38U, // VADDUWS
|
|
38U, // VAND
|
|
38U, // VANDC
|
|
38U, // VAVGSB
|
|
38U, // VAVGSH
|
|
38U, // VAVGSW
|
|
38U, // VAVGUB
|
|
38U, // VAVGUH
|
|
38U, // VAVGUW
|
|
38U, // VBPERMD
|
|
38U, // VBPERMQ
|
|
1U, // VCFSX
|
|
1U, // VCFSX_0
|
|
1U, // VCFUX
|
|
1U, // VCFUX_0
|
|
38U, // VCIPHER
|
|
38U, // VCIPHERLAST
|
|
0U, // VCLZB
|
|
0U, // VCLZD
|
|
0U, // VCLZH
|
|
0U, // VCLZLSBB
|
|
0U, // VCLZW
|
|
38U, // VCMPBFP
|
|
38U, // VCMPBFPo
|
|
38U, // VCMPEQFP
|
|
38U, // VCMPEQFPo
|
|
38U, // VCMPEQUB
|
|
38U, // VCMPEQUBo
|
|
38U, // VCMPEQUD
|
|
38U, // VCMPEQUDo
|
|
38U, // VCMPEQUH
|
|
38U, // VCMPEQUHo
|
|
38U, // VCMPEQUW
|
|
38U, // VCMPEQUWo
|
|
38U, // VCMPGEFP
|
|
38U, // VCMPGEFPo
|
|
38U, // VCMPGTFP
|
|
38U, // VCMPGTFPo
|
|
38U, // VCMPGTSB
|
|
38U, // VCMPGTSBo
|
|
38U, // VCMPGTSD
|
|
38U, // VCMPGTSDo
|
|
38U, // VCMPGTSH
|
|
38U, // VCMPGTSHo
|
|
38U, // VCMPGTSW
|
|
38U, // VCMPGTSWo
|
|
38U, // VCMPGTUB
|
|
38U, // VCMPGTUBo
|
|
38U, // VCMPGTUD
|
|
38U, // VCMPGTUDo
|
|
38U, // VCMPGTUH
|
|
38U, // VCMPGTUHo
|
|
38U, // VCMPGTUW
|
|
38U, // VCMPGTUWo
|
|
38U, // VCMPNEB
|
|
38U, // VCMPNEBo
|
|
38U, // VCMPNEH
|
|
38U, // VCMPNEHo
|
|
38U, // VCMPNEW
|
|
38U, // VCMPNEWo
|
|
38U, // VCMPNEZB
|
|
38U, // VCMPNEZBo
|
|
38U, // VCMPNEZH
|
|
38U, // VCMPNEZHo
|
|
38U, // VCMPNEZW
|
|
38U, // VCMPNEZWo
|
|
1U, // VCTSXS
|
|
1U, // VCTSXS_0
|
|
1U, // VCTUXS
|
|
1U, // VCTUXS_0
|
|
0U, // VCTZB
|
|
0U, // VCTZD
|
|
0U, // VCTZH
|
|
0U, // VCTZLSBB
|
|
0U, // VCTZW
|
|
38U, // VEQV
|
|
0U, // VEXPTEFP
|
|
1U, // VEXTRACTD
|
|
1U, // VEXTRACTUB
|
|
1U, // VEXTRACTUH
|
|
1U, // VEXTRACTUW
|
|
0U, // VEXTSB2D
|
|
0U, // VEXTSB2Ds
|
|
0U, // VEXTSB2W
|
|
0U, // VEXTSB2Ws
|
|
0U, // VEXTSH2D
|
|
0U, // VEXTSH2Ds
|
|
0U, // VEXTSH2W
|
|
0U, // VEXTSH2Ws
|
|
0U, // VEXTSW2D
|
|
0U, // VEXTSW2Ds
|
|
38U, // VEXTUBLX
|
|
38U, // VEXTUBRX
|
|
38U, // VEXTUHLX
|
|
38U, // VEXTUHRX
|
|
38U, // VEXTUWLX
|
|
38U, // VEXTUWRX
|
|
0U, // VGBBD
|
|
0U, // VINSERTB
|
|
1U, // VINSERTD
|
|
0U, // VINSERTH
|
|
1U, // VINSERTW
|
|
0U, // VLOGEFP
|
|
134U, // VMADDFP
|
|
38U, // VMAXFP
|
|
38U, // VMAXSB
|
|
38U, // VMAXSD
|
|
38U, // VMAXSH
|
|
38U, // VMAXSW
|
|
38U, // VMAXUB
|
|
38U, // VMAXUD
|
|
38U, // VMAXUH
|
|
38U, // VMAXUW
|
|
134U, // VMHADDSHS
|
|
134U, // VMHRADDSHS
|
|
38U, // VMINFP
|
|
38U, // VMINSB
|
|
38U, // VMINSD
|
|
38U, // VMINSH
|
|
38U, // VMINSW
|
|
38U, // VMINUB
|
|
38U, // VMINUD
|
|
38U, // VMINUH
|
|
38U, // VMINUW
|
|
134U, // VMLADDUHM
|
|
38U, // VMRGEW
|
|
38U, // VMRGHB
|
|
38U, // VMRGHH
|
|
38U, // VMRGHW
|
|
38U, // VMRGLB
|
|
38U, // VMRGLH
|
|
38U, // VMRGLW
|
|
38U, // VMRGOW
|
|
134U, // VMSUMMBM
|
|
134U, // VMSUMSHM
|
|
134U, // VMSUMSHS
|
|
134U, // VMSUMUBM
|
|
134U, // VMSUMUHM
|
|
134U, // VMSUMUHS
|
|
0U, // VMUL10CUQ
|
|
38U, // VMUL10ECUQ
|
|
38U, // VMUL10EUQ
|
|
0U, // VMUL10UQ
|
|
38U, // VMULESB
|
|
38U, // VMULESH
|
|
38U, // VMULESW
|
|
38U, // VMULEUB
|
|
38U, // VMULEUH
|
|
38U, // VMULEUW
|
|
38U, // VMULOSB
|
|
38U, // VMULOSH
|
|
38U, // VMULOSW
|
|
38U, // VMULOUB
|
|
38U, // VMULOUH
|
|
38U, // VMULOUW
|
|
38U, // VMULUWM
|
|
38U, // VNAND
|
|
38U, // VNCIPHER
|
|
38U, // VNCIPHERLAST
|
|
0U, // VNEGD
|
|
0U, // VNEGW
|
|
134U, // VNMSUBFP
|
|
38U, // VNOR
|
|
38U, // VOR
|
|
38U, // VORC
|
|
134U, // VPERM
|
|
134U, // VPERMR
|
|
134U, // VPERMXOR
|
|
38U, // VPKPX
|
|
38U, // VPKSDSS
|
|
38U, // VPKSDUS
|
|
38U, // VPKSHSS
|
|
38U, // VPKSHUS
|
|
38U, // VPKSWSS
|
|
38U, // VPKSWUS
|
|
38U, // VPKUDUM
|
|
38U, // VPKUDUS
|
|
38U, // VPKUHUM
|
|
38U, // VPKUHUS
|
|
38U, // VPKUWUM
|
|
38U, // VPKUWUS
|
|
38U, // VPMSUMB
|
|
38U, // VPMSUMD
|
|
38U, // VPMSUMH
|
|
38U, // VPMSUMW
|
|
0U, // VPOPCNTB
|
|
0U, // VPOPCNTD
|
|
0U, // VPOPCNTH
|
|
0U, // VPOPCNTW
|
|
0U, // VPRTYBD
|
|
0U, // VPRTYBQ
|
|
0U, // VPRTYBW
|
|
0U, // VREFP
|
|
0U, // VRFIM
|
|
0U, // VRFIN
|
|
0U, // VRFIP
|
|
0U, // VRFIZ
|
|
38U, // VRLB
|
|
38U, // VRLD
|
|
38U, // VRLDMI
|
|
38U, // VRLDNM
|
|
38U, // VRLH
|
|
38U, // VRLW
|
|
38U, // VRLWMI
|
|
38U, // VRLWNM
|
|
0U, // VRSQRTEFP
|
|
0U, // VSBOX
|
|
134U, // VSEL
|
|
394U, // VSHASIGMAD
|
|
394U, // VSHASIGMAW
|
|
38U, // VSL
|
|
38U, // VSLB
|
|
38U, // VSLD
|
|
390U, // VSLDOI
|
|
38U, // VSLH
|
|
38U, // VSLO
|
|
38U, // VSLV
|
|
38U, // VSLW
|
|
1U, // VSPLTB
|
|
1U, // VSPLTBs
|
|
1U, // VSPLTH
|
|
1U, // VSPLTHs
|
|
0U, // VSPLTISB
|
|
0U, // VSPLTISH
|
|
0U, // VSPLTISW
|
|
1U, // VSPLTW
|
|
38U, // VSR
|
|
38U, // VSRAB
|
|
38U, // VSRAD
|
|
38U, // VSRAH
|
|
38U, // VSRAW
|
|
38U, // VSRB
|
|
38U, // VSRD
|
|
38U, // VSRH
|
|
38U, // VSRO
|
|
38U, // VSRV
|
|
38U, // VSRW
|
|
38U, // VSUBCUQ
|
|
38U, // VSUBCUW
|
|
134U, // VSUBECUQ
|
|
134U, // VSUBEUQM
|
|
38U, // VSUBFP
|
|
38U, // VSUBSBS
|
|
38U, // VSUBSHS
|
|
38U, // VSUBSWS
|
|
38U, // VSUBUBM
|
|
38U, // VSUBUBS
|
|
38U, // VSUBUDM
|
|
38U, // VSUBUHM
|
|
38U, // VSUBUHS
|
|
38U, // VSUBUQM
|
|
38U, // VSUBUWM
|
|
38U, // VSUBUWS
|
|
38U, // VSUM2SWS
|
|
38U, // VSUM4SBS
|
|
38U, // VSUM4SHS
|
|
38U, // VSUM4UBS
|
|
38U, // VSUMSWS
|
|
0U, // VUPKHPX
|
|
0U, // VUPKHSB
|
|
0U, // VUPKHSH
|
|
0U, // VUPKHSW
|
|
0U, // VUPKLPX
|
|
0U, // VUPKLSB
|
|
0U, // VUPKLSH
|
|
0U, // VUPKLSW
|
|
38U, // VXOR
|
|
12U, // V_SET0
|
|
12U, // V_SET0B
|
|
12U, // V_SET0H
|
|
0U, // V_SETALLONES
|
|
0U, // V_SETALLONESB
|
|
0U, // V_SETALLONESH
|
|
0U, // WAIT
|
|
0U, // WRTEE
|
|
0U, // WRTEEI
|
|
38U, // XOR
|
|
38U, // XOR8
|
|
38U, // XOR8o
|
|
8U, // XORI
|
|
8U, // XORI8
|
|
8U, // XORIS
|
|
8U, // XORIS8
|
|
38U, // XORo
|
|
0U, // XSABSDP
|
|
0U, // XSABSQP
|
|
38U, // XSADDDP
|
|
38U, // XSADDQP
|
|
38U, // XSADDQPO
|
|
38U, // XSADDSP
|
|
38U, // XSCMPEQDP
|
|
38U, // XSCMPEXPDP
|
|
38U, // XSCMPEXPQP
|
|
38U, // XSCMPGEDP
|
|
38U, // XSCMPGTDP
|
|
38U, // XSCMPODP
|
|
38U, // XSCMPOQP
|
|
38U, // XSCMPUDP
|
|
38U, // XSCMPUQP
|
|
38U, // XSCPSGNDP
|
|
38U, // XSCPSGNQP
|
|
0U, // XSCVDPHP
|
|
0U, // XSCVDPQP
|
|
0U, // XSCVDPSP
|
|
0U, // XSCVDPSPN
|
|
0U, // XSCVDPSXDS
|
|
0U, // XSCVDPSXDSs
|
|
0U, // XSCVDPSXWS
|
|
0U, // XSCVDPSXWSs
|
|
0U, // XSCVDPUXDS
|
|
0U, // XSCVDPUXDSs
|
|
0U, // XSCVDPUXWS
|
|
0U, // XSCVDPUXWSs
|
|
0U, // XSCVHPDP
|
|
0U, // XSCVQPDP
|
|
0U, // XSCVQPDPO
|
|
0U, // XSCVQPSDZ
|
|
0U, // XSCVQPSWZ
|
|
0U, // XSCVQPUDZ
|
|
0U, // XSCVQPUWZ
|
|
0U, // XSCVSDQP
|
|
0U, // XSCVSPDP
|
|
0U, // XSCVSPDPN
|
|
0U, // XSCVSXDDP
|
|
0U, // XSCVSXDSP
|
|
0U, // XSCVUDQP
|
|
0U, // XSCVUXDDP
|
|
0U, // XSCVUXDSP
|
|
38U, // XSDIVDP
|
|
38U, // XSDIVQP
|
|
38U, // XSDIVQPO
|
|
38U, // XSDIVSP
|
|
38U, // XSIEXPDP
|
|
38U, // XSIEXPQP
|
|
1U, // XSMADDADP
|
|
1U, // XSMADDASP
|
|
1U, // XSMADDMDP
|
|
1U, // XSMADDMSP
|
|
1U, // XSMADDQP
|
|
1U, // XSMADDQPO
|
|
38U, // XSMAXCDP
|
|
38U, // XSMAXDP
|
|
38U, // XSMAXJDP
|
|
38U, // XSMINCDP
|
|
38U, // XSMINDP
|
|
38U, // XSMINJDP
|
|
1U, // XSMSUBADP
|
|
1U, // XSMSUBASP
|
|
1U, // XSMSUBMDP
|
|
1U, // XSMSUBMSP
|
|
1U, // XSMSUBQP
|
|
1U, // XSMSUBQPO
|
|
38U, // XSMULDP
|
|
38U, // XSMULQP
|
|
38U, // XSMULQPO
|
|
38U, // XSMULSP
|
|
0U, // XSNABSDP
|
|
0U, // XSNABSQP
|
|
0U, // XSNEGDP
|
|
0U, // XSNEGQP
|
|
1U, // XSNMADDADP
|
|
1U, // XSNMADDASP
|
|
1U, // XSNMADDMDP
|
|
1U, // XSNMADDMSP
|
|
1U, // XSNMADDQP
|
|
1U, // XSNMADDQPO
|
|
1U, // XSNMSUBADP
|
|
1U, // XSNMSUBASP
|
|
1U, // XSNMSUBMDP
|
|
1U, // XSNMSUBMSP
|
|
1U, // XSNMSUBQP
|
|
1U, // XSNMSUBQPO
|
|
0U, // XSRDPI
|
|
0U, // XSRDPIC
|
|
0U, // XSRDPIM
|
|
0U, // XSRDPIP
|
|
0U, // XSRDPIZ
|
|
0U, // XSREDP
|
|
0U, // XSRESP
|
|
262U, // XSRQPI
|
|
262U, // XSRQPIX
|
|
262U, // XSRQPXP
|
|
0U, // XSRSP
|
|
0U, // XSRSQRTEDP
|
|
0U, // XSRSQRTESP
|
|
0U, // XSSQRTDP
|
|
0U, // XSSQRTQP
|
|
0U, // XSSQRTQPO
|
|
0U, // XSSQRTSP
|
|
38U, // XSSUBDP
|
|
38U, // XSSUBQP
|
|
38U, // XSSUBQPO
|
|
38U, // XSSUBSP
|
|
38U, // XSTDIVDP
|
|
0U, // XSTSQRTDP
|
|
1U, // XSTSTDCDP
|
|
1U, // XSTSTDCQP
|
|
1U, // XSTSTDCSP
|
|
0U, // XSXEXPDP
|
|
0U, // XSXEXPQP
|
|
0U, // XSXSIGDP
|
|
0U, // XSXSIGQP
|
|
0U, // XVABSDP
|
|
0U, // XVABSSP
|
|
38U, // XVADDDP
|
|
38U, // XVADDSP
|
|
38U, // XVCMPEQDP
|
|
38U, // XVCMPEQDPo
|
|
38U, // XVCMPEQSP
|
|
38U, // XVCMPEQSPo
|
|
38U, // XVCMPGEDP
|
|
38U, // XVCMPGEDPo
|
|
38U, // XVCMPGESP
|
|
38U, // XVCMPGESPo
|
|
38U, // XVCMPGTDP
|
|
38U, // XVCMPGTDPo
|
|
38U, // XVCMPGTSP
|
|
38U, // XVCMPGTSPo
|
|
38U, // XVCPSGNDP
|
|
38U, // XVCPSGNSP
|
|
0U, // XVCVDPSP
|
|
0U, // XVCVDPSXDS
|
|
0U, // XVCVDPSXWS
|
|
0U, // XVCVDPUXDS
|
|
0U, // XVCVDPUXWS
|
|
0U, // XVCVHPSP
|
|
0U, // XVCVSPDP
|
|
0U, // XVCVSPHP
|
|
0U, // XVCVSPSXDS
|
|
0U, // XVCVSPSXWS
|
|
0U, // XVCVSPUXDS
|
|
0U, // XVCVSPUXWS
|
|
0U, // XVCVSXDDP
|
|
0U, // XVCVSXDSP
|
|
0U, // XVCVSXWDP
|
|
0U, // XVCVSXWSP
|
|
0U, // XVCVUXDDP
|
|
0U, // XVCVUXDSP
|
|
0U, // XVCVUXWDP
|
|
0U, // XVCVUXWSP
|
|
38U, // XVDIVDP
|
|
38U, // XVDIVSP
|
|
38U, // XVIEXPDP
|
|
38U, // XVIEXPSP
|
|
1U, // XVMADDADP
|
|
1U, // XVMADDASP
|
|
1U, // XVMADDMDP
|
|
1U, // XVMADDMSP
|
|
38U, // XVMAXDP
|
|
38U, // XVMAXSP
|
|
38U, // XVMINDP
|
|
38U, // XVMINSP
|
|
1U, // XVMSUBADP
|
|
1U, // XVMSUBASP
|
|
1U, // XVMSUBMDP
|
|
1U, // XVMSUBMSP
|
|
38U, // XVMULDP
|
|
38U, // XVMULSP
|
|
0U, // XVNABSDP
|
|
0U, // XVNABSSP
|
|
0U, // XVNEGDP
|
|
0U, // XVNEGSP
|
|
1U, // XVNMADDADP
|
|
1U, // XVNMADDASP
|
|
1U, // XVNMADDMDP
|
|
1U, // XVNMADDMSP
|
|
1U, // XVNMSUBADP
|
|
1U, // XVNMSUBASP
|
|
1U, // XVNMSUBMDP
|
|
1U, // XVNMSUBMSP
|
|
0U, // XVRDPI
|
|
0U, // XVRDPIC
|
|
0U, // XVRDPIM
|
|
0U, // XVRDPIP
|
|
0U, // XVRDPIZ
|
|
0U, // XVREDP
|
|
0U, // XVRESP
|
|
0U, // XVRSPI
|
|
0U, // XVRSPIC
|
|
0U, // XVRSPIM
|
|
0U, // XVRSPIP
|
|
0U, // XVRSPIZ
|
|
0U, // XVRSQRTEDP
|
|
0U, // XVRSQRTESP
|
|
0U, // XVSQRTDP
|
|
0U, // XVSQRTSP
|
|
38U, // XVSUBDP
|
|
38U, // XVSUBSP
|
|
38U, // XVTDIVDP
|
|
38U, // XVTDIVSP
|
|
0U, // XVTSQRTDP
|
|
0U, // XVTSQRTSP
|
|
1U, // XVTSTDCDP
|
|
1U, // XVTSTDCSP
|
|
0U, // XVXEXPDP
|
|
0U, // XVXEXPSP
|
|
0U, // XVXSIGDP
|
|
0U, // XVXSIGSP
|
|
0U, // XXBRD
|
|
0U, // XXBRH
|
|
0U, // XXBRQ
|
|
0U, // XXBRW
|
|
20U, // XXEXTRACTUW
|
|
1U, // XXINSERTW
|
|
38U, // XXLAND
|
|
38U, // XXLANDC
|
|
38U, // XXLEQV
|
|
38U, // XXLNAND
|
|
38U, // XXLNOR
|
|
38U, // XXLOR
|
|
38U, // XXLORC
|
|
38U, // XXLORf
|
|
38U, // XXLXOR
|
|
12U, // XXLXORdpz
|
|
12U, // XXLXORspz
|
|
12U, // XXLXORz
|
|
38U, // XXMRGHW
|
|
38U, // XXMRGLW
|
|
38U, // XXPERM
|
|
262U, // XXPERMDI
|
|
462U, // XXPERMDIs
|
|
38U, // XXPERMR
|
|
134U, // XXSEL
|
|
262U, // XXSLDWI
|
|
462U, // XXSLDWIs
|
|
0U, // XXSPLTIB
|
|
16U, // XXSPLTW
|
|
16U, // XXSPLTWs
|
|
22U, // gBC
|
|
24U, // gBCA
|
|
0U, // gBCAat
|
|
38U, // gBCCTR
|
|
38U, // gBCCTRL
|
|
22U, // gBCL
|
|
24U, // gBCLA
|
|
0U, // gBCLAat
|
|
38U, // gBCLR
|
|
38U, // gBCLRL
|
|
0U, // gBCLat
|
|
0U, // gBCat
|
|
};
|
|
|
|
unsigned int opcode = MCInst_getOpcode(MI);
|
|
// printf("opcode = %u\n", opcode);
|
|
|
|
// Emit the opcode for the instruction.
|
|
uint64_t Bits = 0;
|
|
Bits |= (uint64_t)OpInfo0[opcode] << 0;
|
|
Bits |= (uint64_t)OpInfo1[opcode] << 32;
|
|
#ifndef CAPSTONE_DIET
|
|
SStream_concat0(O, AsmStrs+(Bits & 16383)-1);
|
|
#endif
|
|
|
|
|
|
// Fragment 0 encoded into 5 bits for 20 unique commands.
|
|
// printf("Fragment 0: %"PRIu64"\n", ((Bits >> 14) & 31));
|
|
switch ((Bits >> 14) & 31) {
|
|
default: // unreachable
|
|
case 0:
|
|
// DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL...
|
|
return;
|
|
break;
|
|
case 1:
|
|
// CLRLSLDI, CLRLSLDIo, CLRLSLWI, CLRLSLWIo, CLRRDI, CLRRDIo, CLRRWI, CLR...
|
|
printOperand(MI, 0, O);
|
|
break;
|
|
case 2:
|
|
// DCBFL, DCBFLP, DCBFx, DCBTCT, DCBTDS, DCBTSTCT, DCBTSTDS, DCBTSTT, DCB...
|
|
printMemRegReg(MI, 0, O);
|
|
break;
|
|
case 3:
|
|
// ADJCALLSTACKDOWN, ADJCALLSTACKUP
|
|
printU16ImmOperand(MI, 0, O);
|
|
SStream_concat0(O, " ");
|
|
printU16ImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 4:
|
|
// B, BCLalways, BDNZ, BDNZ8, BDNZL, BDNZLm, BDNZLp, BDNZm, BDNZp, BDZ, B...
|
|
printBranchOperand(MI, 0, O);
|
|
break;
|
|
case 5:
|
|
// BA, BDNZA, BDNZAm, BDNZAp, BDNZLA, BDNZLAm, BDNZLAp, BDZA, BDZAm, BDZA...
|
|
printAbsBranchOperand(MI, 0, O);
|
|
break;
|
|
case 6:
|
|
// BCC, BCCA, BCCCTR, BCCCTR8, BCCCTRL, BCCCTRL8, BCCL, BCCLA, BCCLR, BCC...
|
|
printPredicateOperand(MI, 0, O, "cc");
|
|
break;
|
|
case 7:
|
|
// BCTRL8_LDinto_toc
|
|
printMemRegImm(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 8:
|
|
// BL8_NOP_TLS, BL8_TLS, BL8_TLS_, BL_TLS
|
|
printTLSCall(MI, 0, O);
|
|
break;
|
|
case 9:
|
|
// DCBF, DCBT, DCBTST
|
|
printMemRegReg(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printU5ImmOperand(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 10:
|
|
// DCBTEP, DCBTSTEP
|
|
printU5ImmOperand(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
printMemRegReg(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 11:
|
|
// DSS, MBAR, MTFSB0, MTFSB1, TD, TDI, TW, TWI, gBC, gBCA, gBCCTR, gBCCTR...
|
|
printU5ImmOperand(MI, 0, O);
|
|
break;
|
|
case 12:
|
|
// DST, DST64, DSTST, DSTST64, DSTSTT, DSTSTT64, DSTT, DSTT64, MTDCR, MTV...
|
|
printOperand(MI, 1, O);
|
|
break;
|
|
case 13:
|
|
// ICBLC, ICBLQ, ICBT, ICBTLS
|
|
printU4ImmOperand(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
printMemRegReg(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 14:
|
|
// MTOCRF, MTOCRF8
|
|
printcrbitm(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 15:
|
|
// MTSR
|
|
printU4ImmOperand(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 16:
|
|
// RFEBB, TBEGIN
|
|
printU1ImmOperand(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 17:
|
|
// TABORTDC, TABORTDCI, TABORTWC, TABORTWCI
|
|
printU5ImmOperand(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 18:
|
|
// TEND, TSR, XSRQPI, XSRQPIX, XSRQPXP
|
|
printU1ImmOperand(MI, 1, O);
|
|
break;
|
|
case 19:
|
|
// gBCAat, gBCLAat, gBCLat, gBCat
|
|
printATBitsAsHint(MI, 1, O);
|
|
SStream_concat0(O, " ");
|
|
printU5ImmOperand(MI, 0, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 1 encoded into 5 bits for 22 unique commands.
|
|
// printf("Fragment 1: %"PRIu64"\n", ((Bits >> 19) & 31));
|
|
switch ((Bits >> 19) & 31) {
|
|
default: // unreachable
|
|
case 0:
|
|
// CLRLSLDI, CLRLSLDIo, CLRLSLWI, CLRLSLWIo, CLRRDI, CLRRDIo, CLRRWI, CLR...
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 1:
|
|
// DCBFL, DCBFLP, DCBFx, DCBTSTT, DCBTSTx, DCBTT, DCBTx, B, BA, BCLalways...
|
|
return;
|
|
break;
|
|
case 2:
|
|
// ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP_I32, TCRETURNai, TCRETURNai8, TCR...
|
|
SStream_concat0(O, " ");
|
|
break;
|
|
case 3:
|
|
// BCC, CTRL_DEP
|
|
printPredicateOperand(MI, 0, O, "pm");
|
|
SStream_concat0(O, " ");
|
|
printPredicateOperand(MI, 0, O, "reg");
|
|
SStream_concat0(O, ", ");
|
|
printBranchOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 4:
|
|
// BCCA
|
|
SStream_concat0(O, "a");
|
|
printPredicateOperand(MI, 0, O, "pm");
|
|
SStream_concat0(O, " ");
|
|
printPredicateOperand(MI, 0, O, "reg");
|
|
SStream_concat0(O, ", ");
|
|
printAbsBranchOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 5:
|
|
// BCCCTR, BCCCTR8
|
|
SStream_concat0(O, "ctr");
|
|
printPredicateOperand(MI, 0, O, "pm");
|
|
SStream_concat0(O, " ");
|
|
printPredicateOperand(MI, 0, O, "reg");
|
|
return;
|
|
break;
|
|
case 6:
|
|
// BCCCTRL, BCCCTRL8
|
|
SStream_concat0(O, "ctrl");
|
|
printPredicateOperand(MI, 0, O, "pm");
|
|
SStream_concat0(O, " ");
|
|
printPredicateOperand(MI, 0, O, "reg");
|
|
return;
|
|
break;
|
|
case 7:
|
|
// BCCL
|
|
SStream_concat0(O, "l");
|
|
printPredicateOperand(MI, 0, O, "pm");
|
|
SStream_concat0(O, " ");
|
|
printPredicateOperand(MI, 0, O, "reg");
|
|
SStream_concat0(O, ", ");
|
|
printBranchOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 8:
|
|
// BCCLA
|
|
SStream_concat0(O, "la");
|
|
printPredicateOperand(MI, 0, O, "pm");
|
|
SStream_concat0(O, " ");
|
|
printPredicateOperand(MI, 0, O, "reg");
|
|
SStream_concat0(O, ", ");
|
|
printAbsBranchOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 9:
|
|
// BCCLR
|
|
SStream_concat0(O, "lr");
|
|
printPredicateOperand(MI, 0, O, "pm");
|
|
SStream_concat0(O, " ");
|
|
printPredicateOperand(MI, 0, O, "reg");
|
|
return;
|
|
break;
|
|
case 10:
|
|
// BCCLRL
|
|
SStream_concat0(O, "lrl");
|
|
printPredicateOperand(MI, 0, O, "pm");
|
|
SStream_concat0(O, " ");
|
|
printPredicateOperand(MI, 0, O, "reg");
|
|
return;
|
|
break;
|
|
case 11:
|
|
// BCCTR, BCCTR8, BCCTR8n, BCCTRL, BCCTRL8, BCCTRL8n, BCCTRLn, BCCTRn, BC...
|
|
SStream_concat0(O, ", 0");
|
|
op_addImm(MI, 0);
|
|
return;
|
|
break;
|
|
case 12:
|
|
// BL8_NOP, BL8_NOP_TLS, BLA8_NOP
|
|
SStream_concat0(O, "\n\tnop");
|
|
return;
|
|
break;
|
|
case 13:
|
|
// EVSEL, TLBIE
|
|
SStream_concat0(O, ",");
|
|
break;
|
|
case 14:
|
|
// MFTB8
|
|
SStream_concat0(O, ", 268");
|
|
op_addImm(MI, 268);
|
|
return;
|
|
break;
|
|
case 15:
|
|
// MFVRSAVE, MFVRSAVEv
|
|
SStream_concat0(O, ", 256");
|
|
op_addImm(MI, 256);
|
|
return;
|
|
break;
|
|
case 16:
|
|
// QVLPCLSXint
|
|
SStream_concat0(O, ", 0, ");
|
|
op_addImm(MI, 0);
|
|
printOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 17:
|
|
// TABORTDC, TABORTWC
|
|
printOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 18:
|
|
// TABORTDCI, TABORTWCI
|
|
printU5ImmOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 19:
|
|
// V_SETALLONES, V_SETALLONESB, V_SETALLONESH
|
|
SStream_concat0(O, ", -1");
|
|
op_addImm(MI, -1);
|
|
return;
|
|
break;
|
|
case 20:
|
|
// gBCAat, gBCLAat
|
|
printAbsBranchOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 21:
|
|
// gBCLat, gBCat
|
|
printBranchOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 2 encoded into 5 bits for 22 unique commands.
|
|
// printf("Fragment 2: %"PRIu64"\n", ((Bits >> 24) & 31));
|
|
switch ((Bits >> 24) & 31) {
|
|
default: // unreachable
|
|
case 0:
|
|
// CLRLSLDI, CLRLSLDIo, CLRLSLWI, CLRLSLWIo, CLRRDI, CLRRDIo, CLRRWI, CLR...
|
|
printOperand(MI, 1, O);
|
|
break;
|
|
case 1:
|
|
// DCBTCT, DCBTDS, DCBTSTCT, DCBTSTDS, EVADDIW
|
|
printU5ImmOperand(MI, 2, O);
|
|
break;
|
|
case 2:
|
|
// LAx, EVLDD, EVLDH, EVLDW, EVLHHESPLAT, EVLHHOSSPLAT, EVLHHOUSPLAT, EVL...
|
|
printMemRegImm(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 3:
|
|
// SUBPCIS, LI, LI8, LIS, LIS8
|
|
printS16ImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 4:
|
|
// ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP_I32, EVLDDX, EVLDHX, EVLDWX, EVLH...
|
|
printMemRegReg(MI, 1, O);
|
|
break;
|
|
case 5:
|
|
// BC, BCL, BCLn, BCn
|
|
printBranchOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 6:
|
|
// CMPRB, CMPRB8
|
|
printU1ImmOperand(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 7:
|
|
// CRSET, CRUNSET, MTDCR, TLBIE, V_SET0, V_SET0B, V_SET0H, XSRQPI, XSRQPI...
|
|
printOperand(MI, 0, O);
|
|
break;
|
|
case 8:
|
|
// DST, DST64, DSTST, DSTST64, DSTSTT, DSTSTT64, DSTT, DSTT64, RLDIMI, RL...
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 9:
|
|
// EVSPLATFI, EVSPLATI, VSPLTISB, VSPLTISH, VSPLTISW
|
|
printS5ImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 10:
|
|
// EVSUBIFW
|
|
printU5ImmOperand(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 11:
|
|
// LA
|
|
printS16ImmOperand(MI, 2, O);
|
|
SStream_concat0(O, "(");
|
|
printOperand(MI, 1, O);
|
|
SStream_concat0(O, ")");
|
|
return;
|
|
break;
|
|
case 12:
|
|
// LBZU, LBZU8, LDU, LFDU, LFSU, LHAU, LHAU8, LHZU, LHZU8, LWZU, LWZU8, S...
|
|
printMemRegImm(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 13:
|
|
// LBZUX, LBZUX8, LDUX, LFDUX, LFSUX, LHAUX, LHAUX8, LHZUX, LHZUX8, LWAUX...
|
|
printMemRegReg(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 14:
|
|
// MFBHRBE
|
|
printU10ImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 15:
|
|
// MFFSCDRNI
|
|
printU3ImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 16:
|
|
// MFFSCRNI
|
|
printU2ImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 17:
|
|
// MFOCRF, MFOCRF8
|
|
printcrbitm(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 18:
|
|
// MFSR
|
|
printU4ImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 19:
|
|
// QVGPCI
|
|
printU12ImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 20:
|
|
// VINSERTB, VINSERTH
|
|
printOperand(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
printU4ImmOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 21:
|
|
// XXSPLTIB
|
|
printU8ImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 3 encoded into 4 bits for 14 unique commands.
|
|
// printf("Fragment 3: %"PRIu64"\n", ((Bits >> 29) & 15));
|
|
switch ((Bits >> 29) & 15) {
|
|
default: // unreachable
|
|
case 0:
|
|
// CLRLSLDI, CLRLSLDIo, CLRLSLWI, CLRLSLWIo, CLRRDI, CLRRDIo, CLRRWI, CLR...
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 1:
|
|
// CP_COPY_FIRST, CP_COPYx, CP_PASTE_LAST, CP_PASTEx, DCBTCT, DCBTDS, DCB...
|
|
return;
|
|
break;
|
|
case 2:
|
|
// ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP_I32
|
|
SStream_concat0(O, " ");
|
|
printOperand(MI, 3, O);
|
|
SStream_concat0(O, " ");
|
|
printOperand(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 3:
|
|
// DST, DST64, DSTST, DSTST64, DSTSTT, DSTSTT64, DSTT, DSTT64
|
|
printU5ImmOperand(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 4:
|
|
// EVSEL
|
|
SStream_concat0(O, ",");
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 5:
|
|
// LBARXL, LDARXL, LHARXL, LWARXL
|
|
SStream_concat0(O, ", 1");
|
|
op_addImm(MI, 1);
|
|
return;
|
|
break;
|
|
case 6:
|
|
// RLDIMI, RLDIMIo
|
|
printU6ImmOperand(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
printU6ImmOperand(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 7:
|
|
// RLWIMI, RLWIMI8, RLWIMI8o, RLWIMIo
|
|
printU5ImmOperand(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
printU5ImmOperand(MI, 4, O);
|
|
SStream_concat0(O, ", ");
|
|
printU5ImmOperand(MI, 5, O);
|
|
return;
|
|
break;
|
|
case 8:
|
|
// VCFSX, VCFUX, VCTSXS, VCTUXS, VSPLTB, VSPLTBs, VSPLTH, VSPLTHs, VSPLTW
|
|
printU5ImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 9:
|
|
// VCFSX_0, VCFUX_0, VCTSXS_0, VCTUXS_0
|
|
SStream_concat0(O, ", 0");
|
|
op_addImm(MI, 0);
|
|
return;
|
|
break;
|
|
case 10:
|
|
// VEXTRACTD, VEXTRACTUB, VEXTRACTUH, VEXTRACTUW, VINSERTD, VINSERTW
|
|
printU4ImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 11:
|
|
// XSMADDADP, XSMADDASP, XSMADDMDP, XSMADDMSP, XSMADDQP, XSMADDQPO, XSMSU...
|
|
printOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 12:
|
|
// XSTSTDCDP, XSTSTDCQP, XSTSTDCSP, XVTSTDCDP, XVTSTDCSP
|
|
printU7ImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 13:
|
|
// XXINSERTW
|
|
printU4ImmOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 4 encoded into 4 bits for 13 unique commands.
|
|
// printf("Fragment 4: %"PRIu64"\n", ((Bits >> 33) & 15));
|
|
switch ((Bits >> 33) & 15) {
|
|
default: // unreachable
|
|
case 0:
|
|
// CLRLSLDI, CLRLSLDIo, CLRRDI, CLRRDIo, EXTLDI, EXTLDIo, EXTRDI, EXTRDIo...
|
|
printU6ImmOperand(MI, 2, O);
|
|
break;
|
|
case 1:
|
|
// CLRLSLWI, CLRLSLWIo, CLRRWI, CLRRWIo, EXTLWI, EXTLWIo, EXTRWI, EXTRWIo...
|
|
printU5ImmOperand(MI, 2, O);
|
|
break;
|
|
case 2:
|
|
// SUBI, SUBIC, SUBICo, SUBIS, ADDI, ADDI8, ADDIC, ADDIC8, ADDICo, ADDIS,...
|
|
printS16ImmOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 3:
|
|
// ADD4, ADD4TLS, ADD4o, ADD8, ADD8TLS, ADD8TLS_, ADD8o, ADDC, ADDC8, ADD...
|
|
printOperand(MI, 2, O);
|
|
break;
|
|
case 4:
|
|
// ANDISo, ANDISo8, ANDIo, ANDIo8, CMPLDI, CMPLWI, ORI, ORI8, ORIS, ORIS8...
|
|
printU16ImmOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 5:
|
|
// BCDCFNo, BCDCFSQo, BCDCFZo, BCDCTZo, BCDSETSGNo, CP_COPY, CP_COPY8, CP...
|
|
printU1ImmOperand(MI, 2, O);
|
|
break;
|
|
case 6:
|
|
// CRSET, CRUNSET, V_SET0, V_SET0B, V_SET0H, XXLXORdpz, XXLXORspz, XXLXOR...
|
|
printOperand(MI, 0, O);
|
|
return;
|
|
break;
|
|
case 7:
|
|
// EVADDIW, XXPERMDIs, XXSLDWIs
|
|
printOperand(MI, 1, O);
|
|
break;
|
|
case 8:
|
|
// QVESPLATI, QVESPLATIb, QVESPLATIs, XXSPLTW, XXSPLTWs
|
|
printU2ImmOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 9:
|
|
// QVFMADD, QVFMADDS, QVFMADDSs, QVFMSUB, QVFMSUBS, QVFMSUBSs, QVFNMADD, ...
|
|
printOperand(MI, 3, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 10:
|
|
// XXEXTRACTUW
|
|
printU4ImmOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 11:
|
|
// gBC, gBCL
|
|
printBranchOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 12:
|
|
// gBCA, gBCLA
|
|
printAbsBranchOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 5 encoded into 1 bits for 2 unique commands.
|
|
// printf("Fragment 5: %"PRIu64"\n", ((Bits >> 37) & 1));
|
|
if ((Bits >> 37) & 1) {
|
|
// CLRRDI, CLRRDIo, CLRRWI, CLRRWIo, ROTRDI, ROTRDIo, ROTRWI, ROTRWIo, SL...
|
|
return;
|
|
} else {
|
|
// CLRLSLDI, CLRLSLDIo, CLRLSLWI, CLRLSLWIo, EXTLDI, EXTLDIo, EXTLWI, EXT...
|
|
SStream_concat0(O, ", ");
|
|
}
|
|
|
|
|
|
// Fragment 6 encoded into 3 bits for 8 unique commands.
|
|
// printf("Fragment 6: %"PRIu64"\n", ((Bits >> 38) & 7));
|
|
switch ((Bits >> 38) & 7) {
|
|
default: // unreachable
|
|
case 0:
|
|
// CLRLSLDI, CLRLSLDIo, EXTLDI, EXTLDIo, EXTRDI, EXTRDIo, INSRDI, INSRDIo...
|
|
printU6ImmOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 1:
|
|
// CLRLSLWI, CLRLSLWIo, EXTLWI, EXTLWIo, EXTRWI, EXTRWIo, INSLWI, INSLWIo...
|
|
printU5ImmOperand(MI, 3, O);
|
|
break;
|
|
case 2:
|
|
// RLWIMIbm, RLWIMIobm, RLWINMbm, RLWINMobm, RLWNMbm, RLWNMobm, FMADD, FM...
|
|
printOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 3:
|
|
// BCDSRo, BCDSo, BCDTRUNCo
|
|
printU1ImmOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 4:
|
|
// QVALIGNI, QVALIGNIb, QVALIGNIs, XSRQPI, XSRQPIX, XSRQPXP, XXPERMDI, XX...
|
|
printU2ImmOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 5:
|
|
// QVFLOGICAL, QVFLOGICALb, QVFLOGICALs
|
|
printU12ImmOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 6:
|
|
// VSHASIGMAD, VSHASIGMAW, VSLDOI
|
|
printU4ImmOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 7:
|
|
// XXPERMDIs, XXSLDWIs
|
|
printU2ImmOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 7 encoded into 1 bits for 2 unique commands.
|
|
// printf("Fragment 7: %"PRIu64"\n", ((Bits >> 41) & 1));
|
|
if ((Bits >> 41) & 1) {
|
|
// RLWINM, RLWINM8, RLWINM8o, RLWINMo, RLWNM, RLWNM8, RLWNM8o, RLWNMo
|
|
SStream_concat0(O, ", ");
|
|
printU5ImmOperand(MI, 4, O);
|
|
return;
|
|
} else {
|
|
// CLRLSLWI, CLRLSLWIo, EXTLWI, EXTLWIo, EXTRWI, EXTRWIo, INSLWI, INSLWIo...
|
|
return;
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef PRINT_ALIAS_INSTR
|
|
#undef PRINT_ALIAS_INSTR
|
|
|
|
static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)
|
|
{
|
|
#define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
|
|
unsigned int I = 0, OpIdx, PrintMethodIdx;
|
|
char *tmpString;
|
|
const char *AsmString;
|
|
switch (MCInst_getOpcode(MI)) {
|
|
default: return false;
|
|
case PPC_ADDPCIS:
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
|
|
// (ADDPCIS g8rc:$RT, 0)
|
|
AsmString = "lnia $\x01";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_BCC:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCC 12, crrc:$cc, condbrtarget:$dst)
|
|
AsmString = "blt $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCC 12, CR0, condbrtarget:$dst)
|
|
AsmString = "blt $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCC 14, crrc:$cc, condbrtarget:$dst)
|
|
AsmString = "blt- $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCC 14, CR0, condbrtarget:$dst)
|
|
AsmString = "blt- $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCC 15, crrc:$cc, condbrtarget:$dst)
|
|
AsmString = "blt+ $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCC 15, CR0, condbrtarget:$dst)
|
|
AsmString = "blt+ $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCC 44, crrc:$cc, condbrtarget:$dst)
|
|
AsmString = "bgt $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCC 44, CR0, condbrtarget:$dst)
|
|
AsmString = "bgt $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCC 46, crrc:$cc, condbrtarget:$dst)
|
|
AsmString = "bgt- $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCC 46, CR0, condbrtarget:$dst)
|
|
AsmString = "bgt- $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCC 47, crrc:$cc, condbrtarget:$dst)
|
|
AsmString = "bgt+ $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCC 47, CR0, condbrtarget:$dst)
|
|
AsmString = "bgt+ $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCC 76, crrc:$cc, condbrtarget:$dst)
|
|
AsmString = "beq $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCC 76, CR0, condbrtarget:$dst)
|
|
AsmString = "beq $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCC 78, crrc:$cc, condbrtarget:$dst)
|
|
AsmString = "beq- $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCC 78, CR0, condbrtarget:$dst)
|
|
AsmString = "beq- $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCC 79, crrc:$cc, condbrtarget:$dst)
|
|
AsmString = "beq+ $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCC 79, CR0, condbrtarget:$dst)
|
|
AsmString = "beq+ $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCC 68, crrc:$cc, condbrtarget:$dst)
|
|
AsmString = "bne $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCC 68, CR0, condbrtarget:$dst)
|
|
AsmString = "bne $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCC 70, crrc:$cc, condbrtarget:$dst)
|
|
AsmString = "bne- $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCC 70, CR0, condbrtarget:$dst)
|
|
AsmString = "bne- $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCC 71, crrc:$cc, condbrtarget:$dst)
|
|
AsmString = "bne+ $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCC 71, CR0, condbrtarget:$dst)
|
|
AsmString = "bne+ $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_BCCA:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCA 12, crrc:$cc, abscondbrtarget:$dst)
|
|
AsmString = "blta $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCA 12, CR0, abscondbrtarget:$dst)
|
|
AsmString = "blta $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCA 14, crrc:$cc, abscondbrtarget:$dst)
|
|
AsmString = "blta- $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCA 14, CR0, abscondbrtarget:$dst)
|
|
AsmString = "blta- $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCA 15, crrc:$cc, abscondbrtarget:$dst)
|
|
AsmString = "blta+ $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCA 15, CR0, abscondbrtarget:$dst)
|
|
AsmString = "blta+ $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCA 44, crrc:$cc, abscondbrtarget:$dst)
|
|
AsmString = "bgta $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCA 44, CR0, abscondbrtarget:$dst)
|
|
AsmString = "bgta $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCA 46, crrc:$cc, abscondbrtarget:$dst)
|
|
AsmString = "bgta- $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCA 46, CR0, abscondbrtarget:$dst)
|
|
AsmString = "bgta- $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCA 47, crrc:$cc, abscondbrtarget:$dst)
|
|
AsmString = "bgta+ $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCA 47, CR0, abscondbrtarget:$dst)
|
|
AsmString = "bgta+ $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCA 76, crrc:$cc, abscondbrtarget:$dst)
|
|
AsmString = "beqa $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCA 76, CR0, abscondbrtarget:$dst)
|
|
AsmString = "beqa $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCA 78, crrc:$cc, abscondbrtarget:$dst)
|
|
AsmString = "beqa- $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCA 78, CR0, abscondbrtarget:$dst)
|
|
AsmString = "beqa- $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCA 79, crrc:$cc, abscondbrtarget:$dst)
|
|
AsmString = "beqa+ $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCA 79, CR0, abscondbrtarget:$dst)
|
|
AsmString = "beqa+ $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCA 68, crrc:$cc, abscondbrtarget:$dst)
|
|
AsmString = "bnea $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCA 68, CR0, abscondbrtarget:$dst)
|
|
AsmString = "bnea $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCA 70, crrc:$cc, abscondbrtarget:$dst)
|
|
AsmString = "bnea- $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCA 70, CR0, abscondbrtarget:$dst)
|
|
AsmString = "bnea- $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCA 71, crrc:$cc, abscondbrtarget:$dst)
|
|
AsmString = "bnea+ $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCA 71, CR0, abscondbrtarget:$dst)
|
|
AsmString = "bnea+ $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_BCCCTR:
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCCTR 12, crrc:$cc)
|
|
AsmString = "bltctr $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCCTR 12, CR0)
|
|
AsmString = "bltctr";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCCTR 14, crrc:$cc)
|
|
AsmString = "bltctr- $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCCTR 14, CR0)
|
|
AsmString = "bltctr-";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCCTR 15, crrc:$cc)
|
|
AsmString = "bltctr+ $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCCTR 15, CR0)
|
|
AsmString = "bltctr+";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCCTR 44, crrc:$cc)
|
|
AsmString = "bgtctr $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCCTR 44, CR0)
|
|
AsmString = "bgtctr";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCCTR 46, crrc:$cc)
|
|
AsmString = "bgtctr- $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCCTR 46, CR0)
|
|
AsmString = "bgtctr-";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCCTR 47, crrc:$cc)
|
|
AsmString = "bgtctr+ $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCCTR 47, CR0)
|
|
AsmString = "bgtctr+";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCCTR 76, crrc:$cc)
|
|
AsmString = "beqctr $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCCTR 76, CR0)
|
|
AsmString = "beqctr";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCCTR 78, crrc:$cc)
|
|
AsmString = "beqctr- $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCCTR 78, CR0)
|
|
AsmString = "beqctr-";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCCTR 79, crrc:$cc)
|
|
AsmString = "beqctr+ $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCCTR 79, CR0)
|
|
AsmString = "beqctr+";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCCTR 68, crrc:$cc)
|
|
AsmString = "bnectr $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCCTR 68, CR0)
|
|
AsmString = "bnectr";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCCTR 70, crrc:$cc)
|
|
AsmString = "bnectr- $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCCTR 70, CR0)
|
|
AsmString = "bnectr-";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCCTR 71, crrc:$cc)
|
|
AsmString = "bnectr+ $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCCTR 71, CR0)
|
|
AsmString = "bnectr+";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_BCCCTRL:
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCCTRL 12, crrc:$cc)
|
|
AsmString = "bltctrl $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCCTRL 12, CR0)
|
|
AsmString = "bltctrl";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCCTRL 14, crrc:$cc)
|
|
AsmString = "bltctrl- $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCCTRL 14, CR0)
|
|
AsmString = "bltctrl-";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCCTRL 15, crrc:$cc)
|
|
AsmString = "bltctrl+ $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCCTRL 15, CR0)
|
|
AsmString = "bltctrl+";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCCTRL 44, crrc:$cc)
|
|
AsmString = "bgtctrl $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCCTRL 44, CR0)
|
|
AsmString = "bgtctrl";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCCTRL 46, crrc:$cc)
|
|
AsmString = "bgtctrl- $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCCTRL 46, CR0)
|
|
AsmString = "bgtctrl-";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCCTRL 47, crrc:$cc)
|
|
AsmString = "bgtctrl+ $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCCTRL 47, CR0)
|
|
AsmString = "bgtctrl+";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCCTRL 76, crrc:$cc)
|
|
AsmString = "beqctrl $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCCTRL 76, CR0)
|
|
AsmString = "beqctrl";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCCTRL 78, crrc:$cc)
|
|
AsmString = "beqctrl- $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCCTRL 78, CR0)
|
|
AsmString = "beqctrl-";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCCTRL 79, crrc:$cc)
|
|
AsmString = "beqctrl+ $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCCTRL 79, CR0)
|
|
AsmString = "beqctrl+";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCCTRL 68, crrc:$cc)
|
|
AsmString = "bnectrl $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCCTRL 68, CR0)
|
|
AsmString = "bnectrl";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCCTRL 70, crrc:$cc)
|
|
AsmString = "bnectrl- $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCCTRL 70, CR0)
|
|
AsmString = "bnectrl-";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCCTRL 71, crrc:$cc)
|
|
AsmString = "bnectrl+ $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCCTRL 71, CR0)
|
|
AsmString = "bnectrl+";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_BCCL:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCL 12, crrc:$cc, condbrtarget:$dst)
|
|
AsmString = "bltl $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCL 12, CR0, condbrtarget:$dst)
|
|
AsmString = "bltl $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCL 14, crrc:$cc, condbrtarget:$dst)
|
|
AsmString = "bltl- $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCL 14, CR0, condbrtarget:$dst)
|
|
AsmString = "bltl- $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCL 15, crrc:$cc, condbrtarget:$dst)
|
|
AsmString = "bltl+ $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCL 15, CR0, condbrtarget:$dst)
|
|
AsmString = "bltl+ $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCL 44, crrc:$cc, condbrtarget:$dst)
|
|
AsmString = "bgtl $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCL 44, CR0, condbrtarget:$dst)
|
|
AsmString = "bgtl $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCL 46, crrc:$cc, condbrtarget:$dst)
|
|
AsmString = "bgtl- $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCL 46, CR0, condbrtarget:$dst)
|
|
AsmString = "bgtl- $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCL 47, crrc:$cc, condbrtarget:$dst)
|
|
AsmString = "bgtl+ $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCL 47, CR0, condbrtarget:$dst)
|
|
AsmString = "bgtl+ $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCL 76, crrc:$cc, condbrtarget:$dst)
|
|
AsmString = "beql $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCL 76, CR0, condbrtarget:$dst)
|
|
AsmString = "beql $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCL 78, crrc:$cc, condbrtarget:$dst)
|
|
AsmString = "beql- $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCL 78, CR0, condbrtarget:$dst)
|
|
AsmString = "beql- $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCL 79, crrc:$cc, condbrtarget:$dst)
|
|
AsmString = "beql+ $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCL 79, CR0, condbrtarget:$dst)
|
|
AsmString = "beql+ $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCL 68, crrc:$cc, condbrtarget:$dst)
|
|
AsmString = "bnel $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCL 68, CR0, condbrtarget:$dst)
|
|
AsmString = "bnel $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCL 70, crrc:$cc, condbrtarget:$dst)
|
|
AsmString = "bnel- $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCL 70, CR0, condbrtarget:$dst)
|
|
AsmString = "bnel- $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCL 71, crrc:$cc, condbrtarget:$dst)
|
|
AsmString = "bnel+ $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCL 71, CR0, condbrtarget:$dst)
|
|
AsmString = "bnel+ $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_BCCLA:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLA 12, crrc:$cc, abscondbrtarget:$dst)
|
|
AsmString = "bltla $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLA 12, CR0, abscondbrtarget:$dst)
|
|
AsmString = "bltla $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLA 14, crrc:$cc, abscondbrtarget:$dst)
|
|
AsmString = "bltla- $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLA 14, CR0, abscondbrtarget:$dst)
|
|
AsmString = "bltla- $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLA 15, crrc:$cc, abscondbrtarget:$dst)
|
|
AsmString = "bltla+ $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLA 15, CR0, abscondbrtarget:$dst)
|
|
AsmString = "bltla+ $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLA 44, crrc:$cc, abscondbrtarget:$dst)
|
|
AsmString = "bgtla $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLA 44, CR0, abscondbrtarget:$dst)
|
|
AsmString = "bgtla $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLA 46, crrc:$cc, abscondbrtarget:$dst)
|
|
AsmString = "bgtla- $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLA 46, CR0, abscondbrtarget:$dst)
|
|
AsmString = "bgtla- $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLA 47, crrc:$cc, abscondbrtarget:$dst)
|
|
AsmString = "bgtla+ $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLA 47, CR0, abscondbrtarget:$dst)
|
|
AsmString = "bgtla+ $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLA 76, crrc:$cc, abscondbrtarget:$dst)
|
|
AsmString = "beqla $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLA 76, CR0, abscondbrtarget:$dst)
|
|
AsmString = "beqla $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLA 78, crrc:$cc, abscondbrtarget:$dst)
|
|
AsmString = "beqla- $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLA 78, CR0, abscondbrtarget:$dst)
|
|
AsmString = "beqla- $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLA 79, crrc:$cc, abscondbrtarget:$dst)
|
|
AsmString = "beqla+ $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLA 79, CR0, abscondbrtarget:$dst)
|
|
AsmString = "beqla+ $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLA 68, crrc:$cc, abscondbrtarget:$dst)
|
|
AsmString = "bnela $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLA 68, CR0, abscondbrtarget:$dst)
|
|
AsmString = "bnela $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLA 70, crrc:$cc, abscondbrtarget:$dst)
|
|
AsmString = "bnela- $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLA 70, CR0, abscondbrtarget:$dst)
|
|
AsmString = "bnela- $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLA 71, crrc:$cc, abscondbrtarget:$dst)
|
|
AsmString = "bnela+ $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLA 71, CR0, abscondbrtarget:$dst)
|
|
AsmString = "bnela+ $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_BCCLR:
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLR 12, crrc:$cc)
|
|
AsmString = "bltlr $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLR 12, CR0)
|
|
AsmString = "bltlr";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLR 14, crrc:$cc)
|
|
AsmString = "bltlr- $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLR 14, CR0)
|
|
AsmString = "bltlr-";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLR 15, crrc:$cc)
|
|
AsmString = "bltlr+ $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLR 15, CR0)
|
|
AsmString = "bltlr+";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLR 44, crrc:$cc)
|
|
AsmString = "bgtlr $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLR 44, CR0)
|
|
AsmString = "bgtlr";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLR 46, crrc:$cc)
|
|
AsmString = "bgtlr- $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLR 46, CR0)
|
|
AsmString = "bgtlr-";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLR 47, crrc:$cc)
|
|
AsmString = "bgtlr+ $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLR 47, CR0)
|
|
AsmString = "bgtlr+";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLR 76, crrc:$cc)
|
|
AsmString = "beqlr $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLR 76, CR0)
|
|
AsmString = "beqlr";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLR 78, crrc:$cc)
|
|
AsmString = "beqlr- $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLR 78, CR0)
|
|
AsmString = "beqlr-";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLR 79, crrc:$cc)
|
|
AsmString = "beqlr+ $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLR 79, CR0)
|
|
AsmString = "beqlr+";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLR 68, crrc:$cc)
|
|
AsmString = "bnelr $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLR 68, CR0)
|
|
AsmString = "bnelr";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLR 70, crrc:$cc)
|
|
AsmString = "bnelr- $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLR 70, CR0)
|
|
AsmString = "bnelr-";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLR 71, crrc:$cc)
|
|
AsmString = "bnelr+ $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLR 71, CR0)
|
|
AsmString = "bnelr+";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_BCCLRL:
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLRL 12, crrc:$cc)
|
|
AsmString = "bltlrl $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLRL 12, CR0)
|
|
AsmString = "bltlrl";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLRL 14, crrc:$cc)
|
|
AsmString = "bltlrl- $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLRL 14, CR0)
|
|
AsmString = "bltlrl-";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLRL 15, crrc:$cc)
|
|
AsmString = "bltlrl+ $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLRL 15, CR0)
|
|
AsmString = "bltlrl+";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLRL 44, crrc:$cc)
|
|
AsmString = "bgtlrl $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLRL 44, CR0)
|
|
AsmString = "bgtlrl";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLRL 46, crrc:$cc)
|
|
AsmString = "bgtlrl- $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLRL 46, CR0)
|
|
AsmString = "bgtlrl-";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLRL 47, crrc:$cc)
|
|
AsmString = "bgtlrl+ $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLRL 47, CR0)
|
|
AsmString = "bgtlrl+";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLRL 76, crrc:$cc)
|
|
AsmString = "beqlrl $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLRL 76, CR0)
|
|
AsmString = "beqlrl";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLRL 78, crrc:$cc)
|
|
AsmString = "beqlrl- $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLRL 78, CR0)
|
|
AsmString = "beqlrl-";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLRL 79, crrc:$cc)
|
|
AsmString = "beqlrl+ $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLRL 79, CR0)
|
|
AsmString = "beqlrl+";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLRL 68, crrc:$cc)
|
|
AsmString = "bnelrl $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLRL 68, CR0)
|
|
AsmString = "bnelrl";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLRL 70, crrc:$cc)
|
|
AsmString = "bnelrl- $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLRL 70, CR0)
|
|
AsmString = "bnelrl-";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) {
|
|
// (BCCLRL 71, crrc:$cc)
|
|
AsmString = "bnelrl+ $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
|
|
// (BCCLRL 71, CR0)
|
|
AsmString = "bnelrl+";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_CMPD:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_CR0 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) {
|
|
// (CMPD CR0, g8rc:$rA, g8rc:$rB)
|
|
AsmString = "cmpd $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_CMPDI:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_CR0 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) {
|
|
// (CMPDI CR0, g8rc:$rA, s16imm64:$imm)
|
|
AsmString = "cmpdi $\x02, $\xFF\x03\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_CMPLD:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_CR0 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) {
|
|
// (CMPLD CR0, g8rc:$rA, g8rc:$rB)
|
|
AsmString = "cmpld $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_CMPLDI:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_CR0 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) {
|
|
// (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)
|
|
AsmString = "cmpldi $\x02, $\xFF\x03\x04";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_CMPLW:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_CR0 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2)) {
|
|
// (CMPLW CR0, gprc:$rA, gprc:$rB)
|
|
AsmString = "cmplw $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_CMPLWI:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_CR0 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (CMPLWI CR0, gprc:$rA, u16imm:$imm)
|
|
AsmString = "cmplwi $\x02, $\xFF\x03\x04";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_CMPW:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_CR0 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2)) {
|
|
// (CMPW CR0, gprc:$rA, gprc:$rB)
|
|
AsmString = "cmpw $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_CMPWI:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_CR0 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (CMPWI CR0, gprc:$rA, s16imm:$imm)
|
|
AsmString = "cmpwi $\x02, $\xFF\x03\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_CNTLZW:
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (CNTLZW gprc:$rA, gprc:$rS)
|
|
AsmString = "cntlzw $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_CNTLZWo:
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (CNTLZWo gprc:$rA, gprc:$rS)
|
|
AsmString = "cntlzw. $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_CREQV:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) {
|
|
// (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)
|
|
AsmString = "crset $\x01";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_CRNOR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
|
|
// (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)
|
|
AsmString = "crnot $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_CROR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
|
|
// (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)
|
|
AsmString = "crmove $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_CRXOR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) {
|
|
// (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)
|
|
AsmString = "crclr $\x01";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_MBAR:
|
|
if (MCInst_getNumOperands(MI) == 1 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) {
|
|
// (MBAR 0)
|
|
AsmString = "mbar";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_MFDCR:
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 128) {
|
|
// (MFDCR gprc:$Rx, 128)
|
|
AsmString = "mfbr0 $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 129) {
|
|
// (MFDCR gprc:$Rx, 129)
|
|
AsmString = "mfbr1 $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 130) {
|
|
// (MFDCR gprc:$Rx, 130)
|
|
AsmString = "mfbr2 $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 131) {
|
|
// (MFDCR gprc:$Rx, 131)
|
|
AsmString = "mfbr3 $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 132) {
|
|
// (MFDCR gprc:$Rx, 132)
|
|
AsmString = "mfbr4 $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 133) {
|
|
// (MFDCR gprc:$Rx, 133)
|
|
AsmString = "mfbr5 $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 134) {
|
|
// (MFDCR gprc:$Rx, 134)
|
|
AsmString = "mfbr6 $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 135) {
|
|
// (MFDCR gprc:$Rx, 135)
|
|
AsmString = "mfbr7 $\x01";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_MFSPR:
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
|
|
// (MFSPR gprc:$Rx, 1)
|
|
AsmString = "mfxer $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
|
|
// (MFSPR gprc:$Rx, 4)
|
|
AsmString = "mfrtcu $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
|
|
// (MFSPR gprc:$Rx, 5)
|
|
AsmString = "mfrtcl $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 17) {
|
|
// (MFSPR gprc:$Rx, 17)
|
|
AsmString = "mfdscr $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 18) {
|
|
// (MFSPR gprc:$Rx, 18)
|
|
AsmString = "mfdsisr $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 19) {
|
|
// (MFSPR gprc:$Rx, 19)
|
|
AsmString = "mfdar $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 990) {
|
|
// (MFSPR gprc:$Rx, 990)
|
|
AsmString = "mfsrr2 $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 991) {
|
|
// (MFSPR gprc:$Rx, 991)
|
|
AsmString = "mfsrr3 $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 28) {
|
|
// (MFSPR gprc:$Rx, 28)
|
|
AsmString = "mfcfar $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 29) {
|
|
// (MFSPR gprc:$Rx, 29)
|
|
AsmString = "mfamr $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 48) {
|
|
// (MFSPR gprc:$Rx, 48)
|
|
AsmString = "mfpid $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 989) {
|
|
// (MFSPR gprc:$Rx, 989)
|
|
AsmString = "mftblo $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 988) {
|
|
// (MFSPR gprc:$Rx, 988)
|
|
AsmString = "mftbhi $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 536) {
|
|
// (MFSPR gprc:$Rx, 536)
|
|
AsmString = "mfdbatu $\x01, 0";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 537) {
|
|
// (MFSPR gprc:$Rx, 537)
|
|
AsmString = "mfdbatl $\x01, 0";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 528) {
|
|
// (MFSPR gprc:$Rx, 528)
|
|
AsmString = "mfibatu $\x01, 0";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 529) {
|
|
// (MFSPR gprc:$Rx, 529)
|
|
AsmString = "mfibatl $\x01, 0";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 538) {
|
|
// (MFSPR gprc:$Rx, 538)
|
|
AsmString = "mfdbatu $\x01, 1";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 539) {
|
|
// (MFSPR gprc:$Rx, 539)
|
|
AsmString = "mfdbatl $\x01, 1";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 530) {
|
|
// (MFSPR gprc:$Rx, 530)
|
|
AsmString = "mfibatu $\x01, 1";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 531) {
|
|
// (MFSPR gprc:$Rx, 531)
|
|
AsmString = "mfibatl $\x01, 1";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 540) {
|
|
// (MFSPR gprc:$Rx, 540)
|
|
AsmString = "mfdbatu $\x01, 2";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 541) {
|
|
// (MFSPR gprc:$Rx, 541)
|
|
AsmString = "mfdbatl $\x01, 2";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 532) {
|
|
// (MFSPR gprc:$Rx, 532)
|
|
AsmString = "mfibatu $\x01, 2";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 533) {
|
|
// (MFSPR gprc:$Rx, 533)
|
|
AsmString = "mfibatl $\x01, 2";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 542) {
|
|
// (MFSPR gprc:$Rx, 542)
|
|
AsmString = "mfdbatu $\x01, 3";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 543) {
|
|
// (MFSPR gprc:$Rx, 543)
|
|
AsmString = "mfdbatl $\x01, 3";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 534) {
|
|
// (MFSPR gprc:$Rx, 534)
|
|
AsmString = "mfibatu $\x01, 3";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 535) {
|
|
// (MFSPR gprc:$Rx, 535)
|
|
AsmString = "mfibatl $\x01, 3";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1018) {
|
|
// (MFSPR gprc:$Rx, 1018)
|
|
AsmString = "mfdccr $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1019) {
|
|
// (MFSPR gprc:$Rx, 1019)
|
|
AsmString = "mficcr $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 981) {
|
|
// (MFSPR gprc:$Rx, 981)
|
|
AsmString = "mfdear $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 980) {
|
|
// (MFSPR gprc:$Rx, 980)
|
|
AsmString = "mfesr $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 512) {
|
|
// (MFSPR gprc:$Rx, 512)
|
|
AsmString = "mfspefscr $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 986) {
|
|
// (MFSPR gprc:$Rx, 986)
|
|
AsmString = "mftcr $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 280) {
|
|
// (MFSPR gprc:$RT, 280)
|
|
AsmString = "mfasr $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 287) {
|
|
// (MFSPR gprc:$RT, 287)
|
|
AsmString = "mfpvr $\x01";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_MFTB:
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 269) {
|
|
// (MFTB gprc:$Rx, 269)
|
|
AsmString = "mftbu $\x01";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_MFVRSAVE:
|
|
if (MCInst_getNumOperands(MI) == 1 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0)) {
|
|
// (MFVRSAVE gprc:$rS)
|
|
AsmString = "mfvrsave $\x01";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_MFVSRD:
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_F8RCRegClassID, 1)) {
|
|
// (MFVSRD g8rc:$rA, f8rc:$src)
|
|
AsmString = "mffprd $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_MTCRF8:
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 255 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) {
|
|
// (MTCRF8 255, g8rc:$rA)
|
|
AsmString = "mtcr $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_MTDCR:
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 128) {
|
|
// (MTDCR gprc:$Rx, 128)
|
|
AsmString = "mtbr0 $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 129) {
|
|
// (MTDCR gprc:$Rx, 129)
|
|
AsmString = "mtbr1 $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 130) {
|
|
// (MTDCR gprc:$Rx, 130)
|
|
AsmString = "mtbr2 $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 131) {
|
|
// (MTDCR gprc:$Rx, 131)
|
|
AsmString = "mtbr3 $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 132) {
|
|
// (MTDCR gprc:$Rx, 132)
|
|
AsmString = "mtbr4 $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 133) {
|
|
// (MTDCR gprc:$Rx, 133)
|
|
AsmString = "mtbr5 $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 134) {
|
|
// (MTDCR gprc:$Rx, 134)
|
|
AsmString = "mtbr6 $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 135) {
|
|
// (MTDCR gprc:$Rx, 135)
|
|
AsmString = "mtbr7 $\x01";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_MTFSF:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_F8RCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)
|
|
AsmString = "mtfsf $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_MTFSFI:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (MTFSFI crrc:$BF, i32imm:$U, 0)
|
|
AsmString = "mtfsfi $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_MTFSFIo:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (MTFSFIo crrc:$BF, i32imm:$U, 0)
|
|
AsmString = "mtfsfi. $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_MTFSFo:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_F8RCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (MTFSFo i32imm:$FLM, f8rc:$FRB, 0, 0)
|
|
AsmString = "mtfsf. $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_MTMSR:
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
|
|
// (MTMSR gprc:$RS, 0)
|
|
AsmString = "mtmsr $\x01";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_MTMSRD:
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
|
|
// (MTMSRD gprc:$RS, 0)
|
|
AsmString = "mtmsrd $\x01";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_MTSPR:
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 1, gprc:$Rx)
|
|
AsmString = "mtxer $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 17 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 17, gprc:$Rx)
|
|
AsmString = "mtdscr $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 18 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 18, gprc:$Rx)
|
|
AsmString = "mtdsisr $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 19 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 19, gprc:$Rx)
|
|
AsmString = "mtdar $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 990 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 990, gprc:$Rx)
|
|
AsmString = "mtsrr2 $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 991 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 991, gprc:$Rx)
|
|
AsmString = "mtsrr3 $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 28 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 28, gprc:$Rx)
|
|
AsmString = "mtcfar $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 29 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 29, gprc:$Rx)
|
|
AsmString = "mtamr $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 48 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 48, gprc:$Rx)
|
|
AsmString = "mtpid $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 284 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 284, gprc:$Rx)
|
|
AsmString = "mttbl $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 285 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 285, gprc:$Rx)
|
|
AsmString = "mttbu $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 989 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 989, gprc:$Rx)
|
|
AsmString = "mttblo $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 988 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 988, gprc:$Rx)
|
|
AsmString = "mttbhi $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 536 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 536, gprc:$Rx)
|
|
AsmString = "mtdbatu 0, $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 537 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 537, gprc:$Rx)
|
|
AsmString = "mtdbatl 0, $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 528 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 528, gprc:$Rx)
|
|
AsmString = "mtibatu 0, $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 529 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 529, gprc:$Rx)
|
|
AsmString = "mtibatl 0, $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 538 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 538, gprc:$Rx)
|
|
AsmString = "mtdbatu 1, $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 539 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 539, gprc:$Rx)
|
|
AsmString = "mtdbatl 1, $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 530 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 530, gprc:$Rx)
|
|
AsmString = "mtibatu 1, $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 531 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 531, gprc:$Rx)
|
|
AsmString = "mtibatl 1, $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 540 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 540, gprc:$Rx)
|
|
AsmString = "mtdbatu 2, $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 541 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 541, gprc:$Rx)
|
|
AsmString = "mtdbatl 2, $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 532 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 532, gprc:$Rx)
|
|
AsmString = "mtibatu 2, $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 533 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 533, gprc:$Rx)
|
|
AsmString = "mtibatl 2, $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 542 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 542, gprc:$Rx)
|
|
AsmString = "mtdbatu 3, $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 543 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 543, gprc:$Rx)
|
|
AsmString = "mtdbatl 3, $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 534 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 534, gprc:$Rx)
|
|
AsmString = "mtibatu 3, $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 535 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 535, gprc:$Rx)
|
|
AsmString = "mtibatl 3, $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1018 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 1018, gprc:$Rx)
|
|
AsmString = "mtdccr $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1019 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 1019, gprc:$Rx)
|
|
AsmString = "mticcr $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 981 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 981, gprc:$Rx)
|
|
AsmString = "mtdear $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 980 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 980, gprc:$Rx)
|
|
AsmString = "mtesr $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 512 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 512, gprc:$Rx)
|
|
AsmString = "mtspefscr $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 986 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (MTSPR 986, gprc:$Rx)
|
|
AsmString = "mttcr $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_MTVRSAVE:
|
|
if (MCInst_getNumOperands(MI) == 1 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0)) {
|
|
// (MTVRSAVE gprc:$rS)
|
|
AsmString = "mtvrsave $\x01";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_NOR8:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
|
|
// (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)
|
|
AsmString = "not $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_NOR8o:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
|
|
// (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)
|
|
AsmString = "not. $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_OR8:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
|
|
// (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)
|
|
AsmString = "mr $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_OR8o:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
|
|
// (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)
|
|
AsmString = "mr. $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_QVFLOGICALb:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (QVFLOGICALb qbrc:$FRT, qbrc:$FRT, qbrc:$FRT, 0)
|
|
AsmString = "qvfclr $\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
|
|
// (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 1)
|
|
AsmString = "qvfand $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
|
|
// (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 4)
|
|
AsmString = "qvfandc $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
|
|
// (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRA, 5)
|
|
AsmString = "qvfctfb $\x01, $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
|
|
// (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 6)
|
|
AsmString = "qvfxor $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
|
|
// (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 7)
|
|
AsmString = "qvfor $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
|
|
// (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 8)
|
|
AsmString = "qvfnor $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
|
|
// (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 9)
|
|
AsmString = "qvfequ $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
|
|
// (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRA, 10)
|
|
AsmString = "qvfnot $\x01, $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
|
|
// (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 13)
|
|
AsmString = "qvforc $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
|
|
// (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 14)
|
|
AsmString = "qvfnand $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
|
|
// (QVFLOGICALb qbrc:$FRT, qbrc:$FRT, qbrc:$FRT, 15)
|
|
AsmString = "qvfset $\x01";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_RLDCL:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)
|
|
AsmString = "rotld $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_RLDCLo:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)
|
|
AsmString = "rotld. $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_RLDICL:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)
|
|
AsmString = "rotldi $\x01, $\x02, $\xFF\x03\x05";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)
|
|
AsmString = "clrldi $\x01, $\x02, $\xFF\x04\x05";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_RLDICL_32_64:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (RLDICL_32_64 g8rc:$rA, gprc:$rS, 0, u6imm:$n)
|
|
AsmString = "clrldi $\x01, $\x02, $\xFF\x04\x05";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_RLDICLo:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)
|
|
AsmString = "rotldi. $\x01, $\x02, $\xFF\x03\x05";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)
|
|
AsmString = "clrldi. $\x01, $\x02, $\xFF\x04\x05";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_RLWINM:
|
|
if (MCInst_getNumOperands(MI) == 5 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 4)) == 31) {
|
|
// (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)
|
|
AsmString = "rotlwi $\x01, $\x02, $\xFF\x03\x06";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 5 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 4)) == 31) {
|
|
// (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)
|
|
AsmString = "clrlwi $\x01, $\x02, $\xFF\x04\x06";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_RLWINMo:
|
|
if (MCInst_getNumOperands(MI) == 5 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 4)) == 31) {
|
|
// (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)
|
|
AsmString = "rotlwi. $\x01, $\x02, $\xFF\x03\x06";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 5 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 4)) == 31) {
|
|
// (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)
|
|
AsmString = "clrlwi. $\x01, $\x02, $\xFF\x04\x06";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_RLWNM:
|
|
if (MCInst_getNumOperands(MI) == 5 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 4)) == 31) {
|
|
// (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)
|
|
AsmString = "rotlw $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_RLWNMo:
|
|
if (MCInst_getNumOperands(MI) == 5 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 4)) == 31) {
|
|
// (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)
|
|
AsmString = "rotlw. $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_SC:
|
|
if (MCInst_getNumOperands(MI) == 1 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) {
|
|
// (SC 0)
|
|
AsmString = "sc";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_SUBF8:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) {
|
|
// (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)
|
|
AsmString = "sub $\x01, $\x03, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_SUBF8o:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) {
|
|
// (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)
|
|
AsmString = "sub. $\x01, $\x03, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_SUBFC8:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) {
|
|
// (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)
|
|
AsmString = "subc $\x01, $\x03, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_SUBFC8o:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) {
|
|
// (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)
|
|
AsmString = "subc. $\x01, $\x03, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_SYNC:
|
|
if (MCInst_getNumOperands(MI) == 1 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) {
|
|
// (SYNC 0)
|
|
AsmString = "sync";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 1 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1) {
|
|
// (SYNC 1)
|
|
AsmString = "lwsync";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 1 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2) {
|
|
// (SYNC 2)
|
|
AsmString = "ptesync";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_TD:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 16 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) {
|
|
// (TD 16, g8rc:$rA, g8rc:$rB)
|
|
AsmString = "tdlt $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) {
|
|
// (TD 4, g8rc:$rA, g8rc:$rB)
|
|
AsmString = "tdeq $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) {
|
|
// (TD 8, g8rc:$rA, g8rc:$rB)
|
|
AsmString = "tdgt $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 24 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) {
|
|
// (TD 24, g8rc:$rA, g8rc:$rB)
|
|
AsmString = "tdne $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) {
|
|
// (TD 2, g8rc:$rA, g8rc:$rB)
|
|
AsmString = "tdllt $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) {
|
|
// (TD 1, g8rc:$rA, g8rc:$rB)
|
|
AsmString = "tdlgt $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 31 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) {
|
|
// (TD 31, g8rc:$rA, g8rc:$rB)
|
|
AsmString = "tdu $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_TDI:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 16 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) {
|
|
// (TDI 16, g8rc:$rA, s16imm:$imm)
|
|
AsmString = "tdlti $\x02, $\xFF\x03\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) {
|
|
// (TDI 4, g8rc:$rA, s16imm:$imm)
|
|
AsmString = "tdeqi $\x02, $\xFF\x03\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) {
|
|
// (TDI 8, g8rc:$rA, s16imm:$imm)
|
|
AsmString = "tdgti $\x02, $\xFF\x03\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 24 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) {
|
|
// (TDI 24, g8rc:$rA, s16imm:$imm)
|
|
AsmString = "tdnei $\x02, $\xFF\x03\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) {
|
|
// (TDI 2, g8rc:$rA, s16imm:$imm)
|
|
AsmString = "tdllti $\x02, $\xFF\x03\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) {
|
|
// (TDI 1, g8rc:$rA, s16imm:$imm)
|
|
AsmString = "tdlgti $\x02, $\xFF\x03\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 31 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) {
|
|
// (TDI 31, g8rc:$rA, s16imm:$imm)
|
|
AsmString = "tdui $\x02, $\xFF\x03\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_TLBIE:
|
|
if (MCInst_getNumOperands(MI) == 2 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_R0 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (TLBIE R0, gprc:$RB)
|
|
AsmString = "tlbie $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_TLBRE2:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (TLBRE2 gprc:$RS, gprc:$A, 0)
|
|
AsmString = "tlbrehi $\x01, $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
|
|
// (TLBRE2 gprc:$RS, gprc:$A, 1)
|
|
AsmString = "tlbrelo $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_TLBWE2:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (TLBWE2 gprc:$RS, gprc:$A, 0)
|
|
AsmString = "tlbwehi $\x01, $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
|
|
// (TLBWE2 gprc:$RS, gprc:$A, 1)
|
|
AsmString = "tlbwelo $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_TW:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 16 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2)) {
|
|
// (TW 16, gprc:$rA, gprc:$rB)
|
|
AsmString = "twlt $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2)) {
|
|
// (TW 4, gprc:$rA, gprc:$rB)
|
|
AsmString = "tweq $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2)) {
|
|
// (TW 8, gprc:$rA, gprc:$rB)
|
|
AsmString = "twgt $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 24 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2)) {
|
|
// (TW 24, gprc:$rA, gprc:$rB)
|
|
AsmString = "twne $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2)) {
|
|
// (TW 2, gprc:$rA, gprc:$rB)
|
|
AsmString = "twllt $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2)) {
|
|
// (TW 1, gprc:$rA, gprc:$rB)
|
|
AsmString = "twlgt $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 31 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2)) {
|
|
// (TW 31, gprc:$rA, gprc:$rB)
|
|
AsmString = "twu $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_TWI:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 16 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (TWI 16, gprc:$rA, s16imm:$imm)
|
|
AsmString = "twlti $\x02, $\xFF\x03\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (TWI 4, gprc:$rA, s16imm:$imm)
|
|
AsmString = "tweqi $\x02, $\xFF\x03\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (TWI 8, gprc:$rA, s16imm:$imm)
|
|
AsmString = "twgti $\x02, $\xFF\x03\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 24 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (TWI 24, gprc:$rA, s16imm:$imm)
|
|
AsmString = "twnei $\x02, $\xFF\x03\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (TWI 2, gprc:$rA, s16imm:$imm)
|
|
AsmString = "twllti $\x02, $\xFF\x03\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (TWI 1, gprc:$rA, s16imm:$imm)
|
|
AsmString = "twlgti $\x02, $\xFF\x03\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 31 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) {
|
|
// (TWI 31, gprc:$rA, s16imm:$imm)
|
|
AsmString = "twui $\x02, $\xFF\x03\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_VNOR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_VRRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_VRRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
|
|
// (VNOR vrrc:$vD, vrrc:$vA, vrrc:$vA)
|
|
AsmString = "vnot $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_VOR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_VRRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_VRRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
|
|
// (VOR vrrc:$vD, vrrc:$vA, vrrc:$vA)
|
|
AsmString = "vmr $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_WAIT:
|
|
if (MCInst_getNumOperands(MI) == 1 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) {
|
|
// (WAIT 0)
|
|
AsmString = "wait";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 1 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1) {
|
|
// (WAIT 1)
|
|
AsmString = "waitrsv";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 1 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2) {
|
|
// (WAIT 2)
|
|
AsmString = "waitimpl";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_XORI:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_R0 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_R0 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (XORI R0, R0, 0)
|
|
AsmString = "xnop";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_XVCPSGNDP:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
|
|
// (XVCPSGNDP vsrc:$XT, vsrc:$XB, vsrc:$XB)
|
|
AsmString = "xvmovdp $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_XVCPSGNSP:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
|
|
// (XVCPSGNSP vsrc:$XT, vsrc:$XB, vsrc:$XB)
|
|
AsmString = "xvmovsp $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_XXPERMDI:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 0)
|
|
AsmString = "xxspltd $\x01, $\x02, 0";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
|
|
// (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 3)
|
|
AsmString = "xxspltd $\x01, $\x02, 1";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 0)
|
|
AsmString = "xxmrghd $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
|
|
// (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 3)
|
|
AsmString = "xxmrgld $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
|
|
// (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 2)
|
|
AsmString = "xxswapd $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_XXPERMDIs:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_VSFRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (XXPERMDIs vsrc:$XT, vsfrc:$XB, 0)
|
|
AsmString = "xxspltd $\x01, $\x02, 0";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_VSFRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
|
|
// (XXPERMDIs vsrc:$XT, vsfrc:$XB, 3)
|
|
AsmString = "xxspltd $\x01, $\x02, 1";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_VSFRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
|
|
// (XXPERMDIs vsrc:$XT, vsfrc:$XB, 2)
|
|
AsmString = "xxswapd $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_gBC:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBC 12, crbitrc:$bi, condbrtarget:$dst)
|
|
AsmString = "bt $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBC 4, crbitrc:$bi, condbrtarget:$dst)
|
|
AsmString = "bf $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBC 14, crbitrc:$bi, condbrtarget:$dst)
|
|
AsmString = "bt- $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 6 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBC 6, crbitrc:$bi, condbrtarget:$dst)
|
|
AsmString = "bf- $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBC 15, crbitrc:$bi, condbrtarget:$dst)
|
|
AsmString = "bt+ $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 7 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBC 7, crbitrc:$bi, condbrtarget:$dst)
|
|
AsmString = "bf+ $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBC 8, crbitrc:$bi, condbrtarget:$dst)
|
|
AsmString = "bdnzt $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBC 0, crbitrc:$bi, condbrtarget:$dst)
|
|
AsmString = "bdnzf $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBC 10, crbitrc:$bi, condbrtarget:$dst)
|
|
AsmString = "bdzt $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBC 2, crbitrc:$bi, condbrtarget:$dst)
|
|
AsmString = "bdzf $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_gBCA:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCA 12, crbitrc:$bi, abscondbrtarget:$dst)
|
|
AsmString = "bta $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCA 4, crbitrc:$bi, abscondbrtarget:$dst)
|
|
AsmString = "bfa $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCA 14, crbitrc:$bi, abscondbrtarget:$dst)
|
|
AsmString = "bta- $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 6 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCA 6, crbitrc:$bi, abscondbrtarget:$dst)
|
|
AsmString = "bfa- $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCA 15, crbitrc:$bi, abscondbrtarget:$dst)
|
|
AsmString = "bta+ $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 7 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCA 7, crbitrc:$bi, abscondbrtarget:$dst)
|
|
AsmString = "bfa+ $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCA 8, crbitrc:$bi, abscondbrtarget:$dst)
|
|
AsmString = "bdnzta $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCA 0, crbitrc:$bi, abscondbrtarget:$dst)
|
|
AsmString = "bdnzfa $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCA 10, crbitrc:$bi, abscondbrtarget:$dst)
|
|
AsmString = "bdzta $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCA 2, crbitrc:$bi, abscondbrtarget:$dst)
|
|
AsmString = "bdzfa $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_gBCAat:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 2)) {
|
|
// (gBCAat u5imm:$bo, 3, crbitrc:$bi, condbrtarget:$dst)
|
|
AsmString = "bca+ $\xFF\x01\x06, $\x03, $\xFF\x04\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 2)) {
|
|
// (gBCAat u5imm:$bo, 2, crbitrc:$bi, condbrtarget:$dst)
|
|
AsmString = "bca- $\xFF\x01\x06, $\x03, $\xFF\x04\x01";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_gBCCTR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCCTR u5imm:$bo, crbitrc:$bi, 0)
|
|
AsmString = "bcctr $\xFF\x01\x06, $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCCTR 12, crbitrc:$bi, 0)
|
|
AsmString = "btctr $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCCTR 4, crbitrc:$bi, 0)
|
|
AsmString = "bfctr $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCCTR 14, crbitrc:$bi, 0)
|
|
AsmString = "btctr- $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 6 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCCTR 6, crbitrc:$bi, 0)
|
|
AsmString = "bfctr- $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCCTR 15, crbitrc:$bi, 0)
|
|
AsmString = "btctr+ $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 7 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCCTR 7, crbitrc:$bi, 0)
|
|
AsmString = "bfctr+ $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_gBCCTRL:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)
|
|
AsmString = "bcctrl $\xFF\x01\x06, $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCCTRL 12, crbitrc:$bi, 0)
|
|
AsmString = "btctrl $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCCTRL 4, crbitrc:$bi, 0)
|
|
AsmString = "bfctrl $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCCTRL 14, crbitrc:$bi, 0)
|
|
AsmString = "btctrl- $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 6 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCCTRL 6, crbitrc:$bi, 0)
|
|
AsmString = "bfctrl- $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCCTRL 15, crbitrc:$bi, 0)
|
|
AsmString = "btctrl+ $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 7 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCCTRL 7, crbitrc:$bi, 0)
|
|
AsmString = "bfctrl+ $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_gBCL:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCL 12, crbitrc:$bi, condbrtarget:$dst)
|
|
AsmString = "btl $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCL 4, crbitrc:$bi, condbrtarget:$dst)
|
|
AsmString = "bfl $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCL 14, crbitrc:$bi, condbrtarget:$dst)
|
|
AsmString = "btl- $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 6 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCL 6, crbitrc:$bi, condbrtarget:$dst)
|
|
AsmString = "bfl- $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCL 15, crbitrc:$bi, condbrtarget:$dst)
|
|
AsmString = "btl+ $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 7 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCL 7, crbitrc:$bi, condbrtarget:$dst)
|
|
AsmString = "bfl+ $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCL 8, crbitrc:$bi, condbrtarget:$dst)
|
|
AsmString = "bdnztl $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCL 0, crbitrc:$bi, condbrtarget:$dst)
|
|
AsmString = "bdnzfl $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCL 10, crbitrc:$bi, condbrtarget:$dst)
|
|
AsmString = "bdztl $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCL 2, crbitrc:$bi, condbrtarget:$dst)
|
|
AsmString = "bdzfl $\x02, $\xFF\x03\x01";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_gBCLA:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCLA 12, crbitrc:$bi, abscondbrtarget:$dst)
|
|
AsmString = "btla $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCLA 4, crbitrc:$bi, abscondbrtarget:$dst)
|
|
AsmString = "bfla $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCLA 14, crbitrc:$bi, abscondbrtarget:$dst)
|
|
AsmString = "btla- $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 6 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCLA 6, crbitrc:$bi, abscondbrtarget:$dst)
|
|
AsmString = "bfla- $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCLA 15, crbitrc:$bi, abscondbrtarget:$dst)
|
|
AsmString = "btla+ $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 7 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCLA 7, crbitrc:$bi, abscondbrtarget:$dst)
|
|
AsmString = "bfla+ $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCLA 8, crbitrc:$bi, abscondbrtarget:$dst)
|
|
AsmString = "bdnztla $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCLA 0, crbitrc:$bi, abscondbrtarget:$dst)
|
|
AsmString = "bdnzfla $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCLA 10, crbitrc:$bi, abscondbrtarget:$dst)
|
|
AsmString = "bdztla $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
// (gBCLA 2, crbitrc:$bi, abscondbrtarget:$dst)
|
|
AsmString = "bdzfla $\x02, $\xFF\x03\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_gBCLAat:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 2)) {
|
|
// (gBCLAat u5imm:$bo, 3, crbitrc:$bi, condbrtarget:$dst)
|
|
AsmString = "bcla+ $\xFF\x01\x06, $\x03, $\xFF\x04\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 2)) {
|
|
// (gBCLAat u5imm:$bo, 2, crbitrc:$bi, condbrtarget:$dst)
|
|
AsmString = "bcla- $\xFF\x01\x06, $\x03, $\xFF\x04\x01";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_gBCLR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCLR u5imm:$bo, crbitrc:$bi, 0)
|
|
AsmString = "bclr $\xFF\x01\x06, $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCLR 12, crbitrc:$bi, 0)
|
|
AsmString = "btlr $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCLR 4, crbitrc:$bi, 0)
|
|
AsmString = "bflr $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCLR 14, crbitrc:$bi, 0)
|
|
AsmString = "btlr- $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 6 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCLR 6, crbitrc:$bi, 0)
|
|
AsmString = "bflr- $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCLR 15, crbitrc:$bi, 0)
|
|
AsmString = "btlr+ $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 7 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCLR 7, crbitrc:$bi, 0)
|
|
AsmString = "bflr+ $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCLR 8, crbitrc:$bi, 0)
|
|
AsmString = "bdnztlr $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCLR 0, crbitrc:$bi, 0)
|
|
AsmString = "bdnzflr $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCLR 10, crbitrc:$bi, 0)
|
|
AsmString = "bdztlr $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCLR 2, crbitrc:$bi, 0)
|
|
AsmString = "bdzflr $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_gBCLRL:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCLRL u5imm:$bo, crbitrc:$bi, 0)
|
|
AsmString = "bclrl $\xFF\x01\x06, $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCLRL 12, crbitrc:$bi, 0)
|
|
AsmString = "btlrl $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCLRL 4, crbitrc:$bi, 0)
|
|
AsmString = "bflrl $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCLRL 14, crbitrc:$bi, 0)
|
|
AsmString = "btlrl- $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 6 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCLRL 6, crbitrc:$bi, 0)
|
|
AsmString = "bflrl- $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCLRL 15, crbitrc:$bi, 0)
|
|
AsmString = "btlrl+ $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 7 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCLRL 7, crbitrc:$bi, 0)
|
|
AsmString = "bflrl+ $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCLRL 8, crbitrc:$bi, 0)
|
|
AsmString = "bdnztlrl $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCLRL 0, crbitrc:$bi, 0)
|
|
AsmString = "bdnzflrl $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCLRL 10, crbitrc:$bi, 0)
|
|
AsmString = "bdztlrl $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (gBCLRL 2, crbitrc:$bi, 0)
|
|
AsmString = "bdzflrl $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_gBCLat:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 2)) {
|
|
// (gBCLat u5imm:$bo, 3, crbitrc:$bi, condbrtarget:$dst)
|
|
AsmString = "bcl+ $\xFF\x01\x06, $\x03, $\xFF\x04\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 2)) {
|
|
// (gBCLat u5imm:$bo, 2, crbitrc:$bi, condbrtarget:$dst)
|
|
AsmString = "bcl- $\xFF\x01\x06, $\x03, $\xFF\x04\x01";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case PPC_gBCat:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 2)) {
|
|
// (gBCat u5imm:$bo, 3, crbitrc:$bi, condbrtarget:$dst)
|
|
AsmString = "bc+ $\xFF\x01\x06, $\x03, $\xFF\x04\x01";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 2)) {
|
|
// (gBCat u5imm:$bo, 2, crbitrc:$bi, condbrtarget:$dst)
|
|
AsmString = "bc- $\xFF\x01\x06, $\x03, $\xFF\x04\x01";
|
|
break;
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
|
|
tmpString = cs_strdup(AsmString);
|
|
|
|
while (AsmString[I] != ' ' && AsmString[I] != '\t' &&
|
|
AsmString[I] != '$' && AsmString[I] != '\0')
|
|
++I;
|
|
|
|
tmpString[I] = 0;
|
|
SStream_concat0(OS, tmpString);
|
|
|
|
if (AsmString[I] != '\0') {
|
|
if (AsmString[I] == ' ' || AsmString[I] == '\t') {
|
|
SStream_concat0(OS, " ");
|
|
++I;
|
|
}
|
|
|
|
do {
|
|
if (AsmString[I] == '$') {
|
|
++I;
|
|
if (AsmString[I] == (char)0xff) {
|
|
++I;
|
|
OpIdx = AsmString[I++] - 1;
|
|
PrintMethodIdx = AsmString[I++] - 1;
|
|
printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
|
|
} else
|
|
printOperand(MI, (unsigned)(AsmString[I++]) - 1, OS);
|
|
} else {
|
|
SStream_concat1(OS, AsmString[I++]);
|
|
}
|
|
} while (AsmString[I] != '\0');
|
|
}
|
|
|
|
return tmpString;
|
|
}
|
|
|
|
static void printCustomAliasOperand(
|
|
MCInst *MI, unsigned OpIdx,
|
|
unsigned PrintMethodIdx,
|
|
SStream *OS)
|
|
{
|
|
switch (PrintMethodIdx) {
|
|
default:
|
|
break;
|
|
case 0:
|
|
printBranchOperand(MI, OpIdx, OS);
|
|
break;
|
|
case 1:
|
|
printAbsBranchOperand(MI, OpIdx, OS);
|
|
break;
|
|
case 2:
|
|
printS16ImmOperand(MI, OpIdx, OS);
|
|
break;
|
|
case 3:
|
|
printU16ImmOperand(MI, OpIdx, OS);
|
|
break;
|
|
case 4:
|
|
printU6ImmOperand(MI, OpIdx, OS);
|
|
break;
|
|
case 5:
|
|
printU5ImmOperand(MI, OpIdx, OS);
|
|
break;
|
|
}
|
|
}
|
|
|
|
#endif // PRINT_ALIAS_INSTR
|