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capstone/arch
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billow 2fa188ec5a refactor: Improve TriCore instruction handling. 
- Add new instructions for TriCore architecture
- Implement changes to TriCoreInstrInfo.td
2023-04-14 00:35:30 +08:00
..
AArch64
Merge pull request #1974 from thomasdangl/next
2023-03-19 17:35:46 +08:00
ARM
correct register accesses for ARM's sxtb/uxtb and similar instructions
2023-03-07 18:59:06 +01:00
BPF
Merge pull request #1886 from terorie/ebpf-callx
2022-06-09 21:37:40 +08:00
EVM
Dont format sstreams when there's nothing to format
2021-12-10 10:59:16 +01:00
M68K
m68k: Add support for the FNOP instruction (fixes #1916)
2022-10-02 08:07:33 +02:00
M680X
Dont format sstreams when there's nothing to format
2021-12-10 10:59:16 +01:00
Mips
Constify backends (#1549)
2019-12-23 20:30:57 +08:00
MOS65XX
Dont format sstreams when there's nothing to format
2021-12-10 10:59:16 +01:00
PowerPC
PPC: fix out of bound memory access
2022-09-07 17:27:54 +02:00
RISCV
Fix potential array out of bounds
2022-11-26 15:59:18 +01:00
SH
Remove unused variable
2023-04-06 03:57:28 -05:00
Sparc
Constify backends (#1549)
2019-12-23 20:30:57 +08:00
SystemZ
Constify backends (#1549)
2019-12-23 20:30:57 +08:00
TMS320C64x
Fix potential array out of bounds
2022-11-26 15:59:18 +01:00
TriCore
refactor: Improve TriCore instruction handling.
2023-04-14 00:35:30 +08:00
WASM
Constify backends (#1549)
2019-12-23 20:30:57 +08:00
X86
One semicolon is enough in C (#1892)
2022-07-08 07:06:38 +08:00
XCore
Constify backends (#1549)
2019-12-23 20:30:57 +08:00