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https://github.com/capstone-engine/capstone.git
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e8d1f1d4d2
* Added new M680X target. Supports M6800/1/2/3/9, HD6301 * M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT * M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec > k cpu type, no default. * M680X: Add python bindings. Added python tests. * M680X: Added cpu types to usage message. * cstool: Avoid segfault for invalid <arch+mode>. * Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched. * M680X: Update CMake/make for m680x support. Update .gitignore. * M680X: Reduce compiler warnings. * M680X: Reduce compiler warnings. * M680X: Reduce compiler warnings. * M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). * M680X: Add ocaml bindings and tests. * M680X: Add java bindings and tests. * M680X: Added tests for all indexed addressing modes. C/Python/Ocaml * M680X: Naming, use page1 for PAGE1 instructions (without prefix). * M680X: Naming, use page1 for PAGE1 instructions (without prefix). * M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml. * M680X: Added access property to cs_m680x_op. * M680X: Added operand size. * M680X: Remove compiler warnings. * M680X: Added READ/WRITE access property per operator. * M680X: Make reg_inherent_hdlr independent of CPU type. * M680X: Add HD6309 support + bug fixes * M680X: Remove errors and warning. * M680X: Add Bcc/LBcc to group BRAREL (relative branch). * M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN. * M680X: Remove LBRN from group BRAREL. * M680X: Refactored cpu_type initialization for better readability. * M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX. * M680X: Remove typo in cstool.c * M680X: Some format improvements in changed_regs. * M680X: Remove insn id string list from tests (C/python/java/ocaml). * M680X: SEXW, set access of reg. D to WRITE. * M680X: Sort changed_regs in increasing m680x_insn order. * M680X: Add M68HC11 support + Reduced from two to one INDEXED operand. * M680X: cstool, also write '(in mnemonic)' for second reg. operand. * M680X: Add BRN/LBRN to group JUMP and BRAREL. * M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access. * M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED. * M680X: Rename some instruction handlers. * M680X: Add M68HC05 support. * M680X: Dont print prefix '<' for direct addr. mode. * M680X: Add M68HC08 support + resorted tables + bug fixes. * M680X: Add Freescale HCS08 support. * M680X: Changed group names, avoid spaces. * M680X: Refactoring, rename addessing mode handlers. * M680X: indexed addr. mode, changed pre/post inc-/decrement representation. * M680X: Rename some M6809/HD6309 specific functions. * M680X: Add CPU12 (68HC12/HCS12) support. * M680X: Correctly display illegal instruction as FCB . * M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg. * M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing. * M680X: Better support for changing insn id within handler for addessing mode. * M680X: Remove warnings. * M680X: In set_changed_regs_read_write_counts use own access_mode. * M680X: Split cpu specific tables into separate *.inc files. * M680X: Remove warnings. * M680X: Removed address_mode. Addressing mode is available in operand.type * M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg. * M680X: Remove register TMP1. It is first visible in CPU12X. * M680X: Performance improvement + bug fixes. * M680X: Performance improvement, make cpu_tables const static. * M680X: Simplify operand decoding by using two handlers. * M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings. * M680X: Format with astyle. * M680X: Update documentation. * M680X: Corrected author for m680x specific files. * M680X: Make max. number of architectures single source.
223 lines
4.4 KiB
C
223 lines
4.4 KiB
C
#include <stdio.h>
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#include <stdlib.h>
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#include <inttypes.h>
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#include <capstone.h>
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struct platform {
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cs_arch arch;
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cs_mode mode;
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char *comment;
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};
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int main(int argc, char **argv)
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{
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if (argc != 2) {
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printf("Usage: %s <testcase>\n", argv[0]);
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return 1;
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}
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struct platform platforms[] = {
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{
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CS_ARCH_X86,
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CS_MODE_32,
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"X86 32 (Intel syntax)"
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},
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{
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CS_ARCH_X86,
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CS_MODE_64,
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"X86 64 (Intel syntax)"
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},
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{
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CS_ARCH_ARM,
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CS_MODE_ARM,
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"ARM"
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},
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{
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CS_ARCH_ARM,
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CS_MODE_THUMB,
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"THUMB-2"
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},
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{
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CS_ARCH_ARM,
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CS_MODE_ARM,
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"ARM: Cortex-A15 + NEON"
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},
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{
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CS_ARCH_ARM,
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CS_MODE_THUMB,
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"THUMB"
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},
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{
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CS_ARCH_ARM,
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(cs_mode)(CS_MODE_THUMB + CS_MODE_MCLASS),
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"Thumb-MClass"
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},
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{
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CS_ARCH_ARM,
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(cs_mode)(CS_MODE_ARM + CS_MODE_V8),
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"Arm-V8"
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},
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{
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CS_ARCH_MIPS,
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(cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN),
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"MIPS-32 (Big-endian)"
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},
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{
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CS_ARCH_MIPS,
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(cs_mode)(CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN),
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"MIPS-64-EL (Little-endian)"
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},
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{
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CS_ARCH_MIPS,
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(cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
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"MIPS-32R6 | Micro (Big-endian)"
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},
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{
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CS_ARCH_MIPS,
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(cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN),
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"MIPS-32R6 (Big-endian)"
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},
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{
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CS_ARCH_ARM64,
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CS_MODE_ARM,
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"ARM-64"
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},
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{
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CS_ARCH_PPC,
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CS_MODE_BIG_ENDIAN,
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"PPC-64"
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},
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{
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CS_ARCH_SPARC,
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CS_MODE_BIG_ENDIAN,
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"Sparc"
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},
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{
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CS_ARCH_SPARC,
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(cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9),
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"SparcV9"
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},
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{
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CS_ARCH_SYSZ,
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(cs_mode)0,
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"SystemZ"
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},
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{
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CS_ARCH_XCORE,
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(cs_mode)0,
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"XCore"
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},
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{
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CS_ARCH_M68K,
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(cs_mode)0,
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"M68K"
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},
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{
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CS_ARCH_M680X,
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(cs_mode)CS_MODE_M680X_6809,
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"M680X_M6809"
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},
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};
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// Read input
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long bufsize = 0;
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unsigned char *buf = NULL;
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FILE *fp = fopen(argv[1], "r");
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if (fp == NULL) return 1;
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if (fseek(fp, 0L, SEEK_END) == 0) {
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bufsize = ftell(fp);
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if (bufsize == -1) return 1;
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buf = malloc(bufsize + 1);
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if (buf == NULL) return 1;
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if (fseek(fp, 0L, SEEK_SET) != 0) return 1;
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size_t len = fread(buf, sizeof(char), bufsize, fp);
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if (len == 0) return 2;
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}
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fclose(fp);
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// Disassemble
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csh handle;
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cs_insn *all_insn;
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cs_detail *detail;
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cs_err err;
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if (bufsize < 3) return 0;
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int platforms_len = sizeof(platforms)/sizeof(platforms[0]);
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int i = (int)buf[0] % platforms_len;
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unsigned char *buf_ptr = buf + 1;
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long buf_ptr_size = bufsize - 1;
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printf("Platform: %s (0x%.2x of 0x%.2x)\n", platforms[i].comment, i, platforms_len);
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err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
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if (err) {
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printf("Failed on cs_open() with error returned: %u\n", err);
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return 1;
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}
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cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
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uint64_t address = 0x1000;
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size_t count = cs_disasm(handle, buf_ptr, buf_ptr_size, address, 0, &all_insn);
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if (count) {
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size_t j;
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int n;
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printf("Disasm:\n");
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for (j = 0; j < count; j++) {
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cs_insn *i = &(all_insn[j]);
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printf("0x%"PRIx64":\t%s\t\t%s // insn-ID: %u, insn-mnem: %s\n",
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i->address, i->mnemonic, i->op_str,
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i->id, cs_insn_name(handle, i->id));
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detail = i->detail;
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if (detail->regs_read_count > 0) {
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printf("\tImplicit registers read: ");
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for (n = 0; n < detail->regs_read_count; n++) {
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printf("%s ", cs_reg_name(handle, detail->regs_read[n]));
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}
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printf("\n");
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}
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if (detail->regs_write_count > 0) {
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printf("\tImplicit registers modified: ");
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for (n = 0; n < detail->regs_write_count; n++) {
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printf("%s ", cs_reg_name(handle, detail->regs_write[n]));
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}
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printf("\n");
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}
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if (detail->groups_count > 0) {
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printf("\tThis instruction belongs to groups: ");
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for (n = 0; n < detail->groups_count; n++) {
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printf("%s ", cs_group_name(handle, detail->groups[n]));
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}
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printf("\n");
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}
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}
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printf("0x%"PRIx64":\n", all_insn[j-1].address + all_insn[j-1].size);
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cs_free(all_insn, count);
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} else {
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printf("ERROR: Failed to disasm given code!\n");
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}
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printf("\n");
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free(buf);
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cs_close(&handle);
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return 0;
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}
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