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691 lines
12 KiB
C
691 lines
12 KiB
C
#ifndef __CS_ARM_H__
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#define __CS_ARM_H__
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/* Capstone Disassembler Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include <stdbool.h>
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//> ARM shift type
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typedef enum arm_shifter {
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ARM_SFT_INVALID = 0,
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ARM_SFT_ASR, // shift with immediate const
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ARM_SFT_LSL, // shift with immediate const
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ARM_SFT_LSR, // shift with immediate const
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ARM_SFT_ROR, // shift with immediate const
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ARM_SFT_RRX, // shift with immediate const
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ARM_SFT_ASR_REG, // shift with register
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ARM_SFT_LSL_REG, // shift with register
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ARM_SFT_LSR_REG, // shift with register
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ARM_SFT_ROR_REG, // shift with register
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ARM_SFT_RRX_REG, // shift with register
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} arm_shifter;
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//> ARM condition code
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typedef enum arm_cc {
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ARM_CC_INVALID = 0,
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ARM_CC_EQ, // Equal Equal
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ARM_CC_NE, // Not equal Not equal, or unordered
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ARM_CC_HS, // Carry set >, ==, or unordered
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ARM_CC_LO, // Carry clear Less than
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ARM_CC_MI, // Minus, negative Less than
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ARM_CC_PL, // Plus, positive or zero >, ==, or unordered
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ARM_CC_VS, // Overflow Unordered
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ARM_CC_VC, // No overflow Not unordered
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ARM_CC_HI, // Unsigned higher Greater than, or unordered
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ARM_CC_LS, // Unsigned lower or same Less than or equal
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ARM_CC_GE, // Greater than or equal Greater than or equal
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ARM_CC_LT, // Less than Less than, or unordered
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ARM_CC_GT, // Greater than Greater than
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ARM_CC_LE, // Less than or equal <, ==, or unordered
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ARM_CC_AL // Always (unconditional) Always (unconditional)
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} arm_cc;
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//> Operand type for instruction's operands
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typedef enum arm_op_type {
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ARM_OP_INVALID = 0, // Uninitialized.
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ARM_OP_REG, // Register operand.
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ARM_OP_CIMM, // C-Immediate
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ARM_OP_PIMM, // P-Immediate
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ARM_OP_IMM, // Immediate operand.
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ARM_OP_FP, // Floating-Point immediate operand.
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ARM_OP_MEM, // Memory operand
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} arm_op_type;
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// Instruction's operand referring to memory
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// This is associated with ARM_OP_MEM operand type above
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typedef struct arm_op_mem {
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unsigned int base; // base register
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unsigned int index; // index register
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int scale; // scale for index register (can be 1, or -1)
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int disp; // displacement/offset value
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} arm_op_mem;
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// Instruction operand
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typedef struct cs_arm_op {
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struct {
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arm_shifter type;
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unsigned int value;
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} shift;
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arm_op_type type; // operand type
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union {
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unsigned int reg; // register value for REG operand
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unsigned int imm; // immediate value for C-IMM, P-IMM or IMM operand
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double fp; // floating point value for FP operand
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arm_op_mem mem; // base/index/scale/disp value for MEM operand
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};
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} cs_arm_op;
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// Instruction structure
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typedef struct cs_arm {
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arm_cc cc; // conditional code for this insn
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bool update_flags; // does this insn update flags?
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bool writeback; // does this insn write-back?
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// Number of operands of this instruction,
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// or 0 when instruction has no operand.
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uint8_t op_count;
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cs_arm_op operands[20]; // operands for this instruction.
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} cs_arm;
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//> ARM registers
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typedef enum arm_reg {
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ARM_REG_INVALID = 0,
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ARM_REG_APSR,
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ARM_REG_APSR_NZCV,
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ARM_REG_CPSR,
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ARM_REG_FPEXC,
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ARM_REG_FPINST,
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ARM_REG_FPSCR,
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ARM_REG_FPSCR_NZCV,
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ARM_REG_FPSID,
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ARM_REG_ITSTATE,
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ARM_REG_LR,
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ARM_REG_PC,
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ARM_REG_SP,
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ARM_REG_SPSR,
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ARM_REG_D0,
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ARM_REG_D1,
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ARM_REG_D2,
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ARM_REG_D3,
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ARM_REG_D4,
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ARM_REG_D5,
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ARM_REG_D6,
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ARM_REG_D7,
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ARM_REG_D8,
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ARM_REG_D9,
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ARM_REG_D10,
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ARM_REG_D11,
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ARM_REG_D12,
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ARM_REG_D13,
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ARM_REG_D14,
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ARM_REG_D15,
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ARM_REG_D16,
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ARM_REG_D17,
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ARM_REG_D18,
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ARM_REG_D19,
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ARM_REG_D20,
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ARM_REG_D21,
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ARM_REG_D22,
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ARM_REG_D23,
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ARM_REG_D24,
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ARM_REG_D25,
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ARM_REG_D26,
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ARM_REG_D27,
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ARM_REG_D28,
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ARM_REG_D29,
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ARM_REG_D30,
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ARM_REG_D31,
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ARM_REG_FPINST2,
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ARM_REG_MVFR0,
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ARM_REG_MVFR1,
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ARM_REG_MVFR2,
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ARM_REG_Q0,
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ARM_REG_Q1,
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ARM_REG_Q2,
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ARM_REG_Q3,
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ARM_REG_Q4,
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ARM_REG_Q5,
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ARM_REG_Q6,
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ARM_REG_Q7,
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ARM_REG_Q8,
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ARM_REG_Q9,
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ARM_REG_Q10,
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ARM_REG_Q11,
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ARM_REG_Q12,
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ARM_REG_Q13,
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ARM_REG_Q14,
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ARM_REG_Q15,
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ARM_REG_R0,
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ARM_REG_R1,
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ARM_REG_R2,
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ARM_REG_R3,
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ARM_REG_R4,
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ARM_REG_R5,
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ARM_REG_R6,
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ARM_REG_R7,
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ARM_REG_R8,
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ARM_REG_R9,
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ARM_REG_R10,
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ARM_REG_R11,
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ARM_REG_R12,
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ARM_REG_S0,
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ARM_REG_S1,
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ARM_REG_S2,
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ARM_REG_S3,
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ARM_REG_S4,
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ARM_REG_S5,
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ARM_REG_S6,
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ARM_REG_S7,
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ARM_REG_S8,
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ARM_REG_S9,
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ARM_REG_S10,
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ARM_REG_S11,
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ARM_REG_S12,
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ARM_REG_S13,
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ARM_REG_S14,
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ARM_REG_S15,
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ARM_REG_S16,
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ARM_REG_S17,
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ARM_REG_S18,
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ARM_REG_S19,
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ARM_REG_S20,
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ARM_REG_S21,
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ARM_REG_S22,
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ARM_REG_S23,
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ARM_REG_S24,
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ARM_REG_S25,
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ARM_REG_S26,
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ARM_REG_S27,
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ARM_REG_S28,
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ARM_REG_S29,
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ARM_REG_S30,
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ARM_REG_S31,
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ARM_REG_MAX, // <-- mark the end of the list or registers
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// alias registers
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ARM_REG_R13 = ARM_REG_SP,
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ARM_REG_R14 = ARM_REG_LR,
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ARM_REG_R15 = ARM_REG_PC,
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} arm_reg;
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//> ARM instruction
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typedef enum arm_insn {
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ARM_INS_INVALID = 0,
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ARM_INS_ADC,
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ARM_INS_ADD,
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ARM_INS_ADR,
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ARM_INS_AESD,
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ARM_INS_AESE,
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ARM_INS_AESIMC,
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ARM_INS_AESMC,
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ARM_INS_AND,
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ARM_INS_BFC,
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ARM_INS_BFI,
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ARM_INS_BIC,
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ARM_INS_BKPT,
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ARM_INS_BL,
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ARM_INS_BLX,
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ARM_INS_BX,
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ARM_INS_BXJ,
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ARM_INS_B,
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ARM_INS_CDP,
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ARM_INS_CDP2,
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ARM_INS_CLREX,
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ARM_INS_CLZ,
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ARM_INS_CMN,
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ARM_INS_CMP,
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ARM_INS_CPS,
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ARM_INS_CRC32B,
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ARM_INS_CRC32CB,
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ARM_INS_CRC32CH,
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ARM_INS_CRC32CW,
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ARM_INS_CRC32H,
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ARM_INS_CRC32W,
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ARM_INS_DBG,
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ARM_INS_DMB,
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ARM_INS_DSB,
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ARM_INS_EOR,
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ARM_INS_VMOV,
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ARM_INS_FLDMDBX,
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ARM_INS_FLDMIAX,
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ARM_INS_VMRS,
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ARM_INS_FSTMDBX,
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ARM_INS_FSTMIAX,
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ARM_INS_HINT,
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ARM_INS_HLT,
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ARM_INS_ISB,
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ARM_INS_LDA,
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ARM_INS_LDAB,
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ARM_INS_LDAEX,
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ARM_INS_LDAEXB,
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ARM_INS_LDAEXD,
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ARM_INS_LDAEXH,
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ARM_INS_LDAH,
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ARM_INS_LDC2L,
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ARM_INS_LDC2,
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ARM_INS_LDCL,
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ARM_INS_LDC,
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ARM_INS_LDMDA,
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ARM_INS_LDMDB,
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ARM_INS_LDM,
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ARM_INS_LDMIB,
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ARM_INS_LDRBT,
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ARM_INS_LDRB,
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ARM_INS_LDRD,
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ARM_INS_LDREX,
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ARM_INS_LDREXB,
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ARM_INS_LDREXD,
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ARM_INS_LDREXH,
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ARM_INS_LDRH,
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ARM_INS_LDRHT,
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ARM_INS_LDRSB,
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ARM_INS_LDRSBT,
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ARM_INS_LDRSH,
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ARM_INS_LDRSHT,
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ARM_INS_LDRT,
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ARM_INS_LDR,
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ARM_INS_MCR,
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ARM_INS_MCR2,
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ARM_INS_MCRR,
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ARM_INS_MCRR2,
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ARM_INS_MLA,
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ARM_INS_MLS,
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ARM_INS_MOV,
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ARM_INS_MOVT,
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ARM_INS_MOVW,
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ARM_INS_MRC,
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ARM_INS_MRC2,
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ARM_INS_MRRC,
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ARM_INS_MRRC2,
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ARM_INS_MRS,
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ARM_INS_MSR,
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ARM_INS_MUL,
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ARM_INS_MVN,
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ARM_INS_ORR,
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ARM_INS_PKHBT,
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ARM_INS_PKHTB,
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ARM_INS_PLDW,
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ARM_INS_PLD,
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ARM_INS_PLI,
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ARM_INS_QADD,
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ARM_INS_QADD16,
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ARM_INS_QADD8,
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ARM_INS_QASX,
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ARM_INS_QDADD,
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ARM_INS_QDSUB,
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ARM_INS_QSAX,
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ARM_INS_QSUB,
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ARM_INS_QSUB16,
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ARM_INS_QSUB8,
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ARM_INS_RBIT,
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ARM_INS_REV,
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ARM_INS_REV16,
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ARM_INS_REVSH,
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ARM_INS_RFEDA,
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ARM_INS_RFEDB,
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ARM_INS_RFEIA,
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ARM_INS_RFEIB,
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ARM_INS_RSB,
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ARM_INS_RSC,
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ARM_INS_SADD16,
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ARM_INS_SADD8,
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ARM_INS_SASX,
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ARM_INS_SBC,
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ARM_INS_SBFX,
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ARM_INS_SDIV,
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ARM_INS_SEL,
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ARM_INS_SETEND,
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ARM_INS_SHA1C,
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ARM_INS_SHA1H,
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ARM_INS_SHA1M,
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ARM_INS_SHA1P,
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ARM_INS_SHA1SU0,
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ARM_INS_SHA1SU1,
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ARM_INS_SHA256H,
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ARM_INS_SHA256H2,
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ARM_INS_SHA256SU0,
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ARM_INS_SHA256SU1,
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ARM_INS_SHADD16,
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ARM_INS_SHADD8,
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ARM_INS_SHASX,
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ARM_INS_SHSAX,
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ARM_INS_SHSUB16,
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ARM_INS_SHSUB8,
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ARM_INS_SMC,
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ARM_INS_SMLABB,
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ARM_INS_SMLABT,
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ARM_INS_SMLAD,
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ARM_INS_SMLADX,
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ARM_INS_SMLAL,
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ARM_INS_SMLALBB,
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ARM_INS_SMLALBT,
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ARM_INS_SMLALD,
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ARM_INS_SMLALDX,
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ARM_INS_SMLALTB,
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ARM_INS_SMLALTT,
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ARM_INS_SMLATB,
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ARM_INS_SMLATT,
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ARM_INS_SMLAWB,
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ARM_INS_SMLAWT,
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ARM_INS_SMLSD,
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ARM_INS_SMLSDX,
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ARM_INS_SMLSLD,
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ARM_INS_SMLSLDX,
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ARM_INS_SMMLA,
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ARM_INS_SMMLAR,
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ARM_INS_SMMLS,
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ARM_INS_SMMLSR,
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ARM_INS_SMMUL,
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ARM_INS_SMMULR,
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ARM_INS_SMUAD,
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ARM_INS_SMUADX,
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ARM_INS_SMULBB,
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ARM_INS_SMULBT,
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ARM_INS_SMULL,
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ARM_INS_SMULTB,
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ARM_INS_SMULTT,
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ARM_INS_SMULWB,
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ARM_INS_SMULWT,
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ARM_INS_SMUSD,
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ARM_INS_SMUSDX,
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ARM_INS_SRSDA,
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ARM_INS_SRSDB,
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ARM_INS_SRSIA,
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ARM_INS_SRSIB,
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ARM_INS_SSAT,
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ARM_INS_SSAT16,
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ARM_INS_SSAX,
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ARM_INS_SSUB16,
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ARM_INS_SSUB8,
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ARM_INS_STC2L,
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ARM_INS_STC2,
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ARM_INS_STCL,
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ARM_INS_STC,
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ARM_INS_STL,
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ARM_INS_STLB,
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ARM_INS_STLEX,
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ARM_INS_STLEXB,
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ARM_INS_STLEXD,
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ARM_INS_STLEXH,
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ARM_INS_STLH,
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ARM_INS_STMDA,
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ARM_INS_STMDB,
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ARM_INS_STM,
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ARM_INS_STMIB,
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ARM_INS_STRBT,
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ARM_INS_STRB,
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ARM_INS_STRD,
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ARM_INS_STREX,
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ARM_INS_STREXB,
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ARM_INS_STREXD,
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ARM_INS_STREXH,
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ARM_INS_STRH,
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ARM_INS_STRHT,
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ARM_INS_STRT,
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ARM_INS_STR,
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ARM_INS_SUB,
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ARM_INS_SVC,
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ARM_INS_SWP,
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ARM_INS_SWPB,
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ARM_INS_SXTAB,
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ARM_INS_SXTAB16,
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ARM_INS_SXTAH,
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ARM_INS_SXTB,
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ARM_INS_SXTB16,
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ARM_INS_SXTH,
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ARM_INS_TEQ,
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ARM_INS_TRAP,
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ARM_INS_TST,
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ARM_INS_UADD16,
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ARM_INS_UADD8,
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ARM_INS_UASX,
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ARM_INS_UBFX,
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ARM_INS_UDIV,
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ARM_INS_UHADD16,
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ARM_INS_UHADD8,
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ARM_INS_UHASX,
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ARM_INS_UHSAX,
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ARM_INS_UHSUB16,
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ARM_INS_UHSUB8,
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ARM_INS_UMAAL,
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ARM_INS_UMLAL,
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ARM_INS_UMULL,
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ARM_INS_UQADD16,
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ARM_INS_UQADD8,
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ARM_INS_UQASX,
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ARM_INS_UQSAX,
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ARM_INS_UQSUB16,
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ARM_INS_UQSUB8,
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ARM_INS_USAD8,
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ARM_INS_USADA8,
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ARM_INS_USAT,
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ARM_INS_USAT16,
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ARM_INS_USAX,
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ARM_INS_USUB16,
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ARM_INS_USUB8,
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ARM_INS_UXTAB,
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ARM_INS_UXTAB16,
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ARM_INS_UXTAH,
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ARM_INS_UXTB,
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ARM_INS_UXTB16,
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ARM_INS_UXTH,
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ARM_INS_VABAL,
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ARM_INS_VABA,
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ARM_INS_VABDL,
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ARM_INS_VABD,
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ARM_INS_VABS,
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ARM_INS_VACGE,
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ARM_INS_VACGT,
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ARM_INS_VADD,
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ARM_INS_VADDHN,
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ARM_INS_VADDL,
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ARM_INS_VADDW,
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ARM_INS_VAND,
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ARM_INS_VBIC,
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ARM_INS_VBIF,
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ARM_INS_VBIT,
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ARM_INS_VBSL,
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ARM_INS_VCEQ,
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ARM_INS_VCGE,
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ARM_INS_VCGT,
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ARM_INS_VCLS,
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ARM_INS_VCLZ,
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ARM_INS_VCMP,
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ARM_INS_VCMPE,
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ARM_INS_VCNT,
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ARM_INS_VCVTA,
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ARM_INS_VCVTB,
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ARM_INS_VCVT,
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ARM_INS_VCVTM,
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ARM_INS_VCVTN,
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ARM_INS_VCVTP,
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ARM_INS_VCVTT,
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ARM_INS_VDIV,
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ARM_INS_VDUP,
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ARM_INS_VEOR,
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ARM_INS_VEXT,
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ARM_INS_VFMA,
|
|
ARM_INS_VFMS,
|
|
ARM_INS_VFNMA,
|
|
ARM_INS_VFNMS,
|
|
ARM_INS_VHADD,
|
|
ARM_INS_VHSUB,
|
|
ARM_INS_VLD1,
|
|
ARM_INS_VLD2,
|
|
ARM_INS_VLD3,
|
|
ARM_INS_VLD4,
|
|
ARM_INS_VLDMDB,
|
|
ARM_INS_VLDMIA,
|
|
ARM_INS_VLDR,
|
|
ARM_INS_VMAXNM,
|
|
ARM_INS_VMAX,
|
|
ARM_INS_VMINNM,
|
|
ARM_INS_VMIN,
|
|
ARM_INS_VMLA,
|
|
ARM_INS_VMLAL,
|
|
ARM_INS_VMLS,
|
|
ARM_INS_VMLSL,
|
|
ARM_INS_VMOVL,
|
|
ARM_INS_VMOVN,
|
|
ARM_INS_VMSR,
|
|
ARM_INS_VMUL,
|
|
ARM_INS_VMULL,
|
|
ARM_INS_VMVN,
|
|
ARM_INS_VNEG,
|
|
ARM_INS_VNMLA,
|
|
ARM_INS_VNMLS,
|
|
ARM_INS_VNMUL,
|
|
ARM_INS_VORN,
|
|
ARM_INS_VORR,
|
|
ARM_INS_VPADAL,
|
|
ARM_INS_VPADDL,
|
|
ARM_INS_VPADD,
|
|
ARM_INS_VPMAX,
|
|
ARM_INS_VPMIN,
|
|
ARM_INS_VQABS,
|
|
ARM_INS_VQADD,
|
|
ARM_INS_VQDMLAL,
|
|
ARM_INS_VQDMLSL,
|
|
ARM_INS_VQDMULH,
|
|
ARM_INS_VQDMULL,
|
|
ARM_INS_VQMOVUN,
|
|
ARM_INS_VQMOVN,
|
|
ARM_INS_VQNEG,
|
|
ARM_INS_VQRDMULH,
|
|
ARM_INS_VQRSHL,
|
|
ARM_INS_VQRSHRN,
|
|
ARM_INS_VQRSHRUN,
|
|
ARM_INS_VQSHL,
|
|
ARM_INS_VQSHLU,
|
|
ARM_INS_VQSHRN,
|
|
ARM_INS_VQSHRUN,
|
|
ARM_INS_VQSUB,
|
|
ARM_INS_VRADDHN,
|
|
ARM_INS_VRECPE,
|
|
ARM_INS_VRECPS,
|
|
ARM_INS_VREV16,
|
|
ARM_INS_VREV32,
|
|
ARM_INS_VREV64,
|
|
ARM_INS_VRHADD,
|
|
ARM_INS_VRINTA,
|
|
ARM_INS_VRINTM,
|
|
ARM_INS_VRINTN,
|
|
ARM_INS_VRINTP,
|
|
ARM_INS_VRINTR,
|
|
ARM_INS_VRINTX,
|
|
ARM_INS_VRINTZ,
|
|
ARM_INS_VRSHL,
|
|
ARM_INS_VRSHRN,
|
|
ARM_INS_VRSHR,
|
|
ARM_INS_VRSQRTE,
|
|
ARM_INS_VRSQRTS,
|
|
ARM_INS_VRSRA,
|
|
ARM_INS_VRSUBHN,
|
|
ARM_INS_VSELEQ,
|
|
ARM_INS_VSELGE,
|
|
ARM_INS_VSELGT,
|
|
ARM_INS_VSELVS,
|
|
ARM_INS_VSHLL,
|
|
ARM_INS_VSHL,
|
|
ARM_INS_VSHRN,
|
|
ARM_INS_VSHR,
|
|
ARM_INS_VSLI,
|
|
ARM_INS_VSQRT,
|
|
ARM_INS_VSRA,
|
|
ARM_INS_VSRI,
|
|
ARM_INS_VST1,
|
|
ARM_INS_VST2,
|
|
ARM_INS_VST3,
|
|
ARM_INS_VST4,
|
|
ARM_INS_VSTMDB,
|
|
ARM_INS_VSTMIA,
|
|
ARM_INS_VSTR,
|
|
ARM_INS_VSUB,
|
|
ARM_INS_VSUBHN,
|
|
ARM_INS_VSUBL,
|
|
ARM_INS_VSUBW,
|
|
ARM_INS_VSWP,
|
|
ARM_INS_VTBL,
|
|
ARM_INS_VTBX,
|
|
ARM_INS_VCVTR,
|
|
ARM_INS_VTRN,
|
|
ARM_INS_VTST,
|
|
ARM_INS_VUZP,
|
|
ARM_INS_VZIP,
|
|
ARM_INS_ADDW,
|
|
ARM_INS_ASR,
|
|
ARM_INS_DCPS1,
|
|
ARM_INS_DCPS2,
|
|
ARM_INS_DCPS3,
|
|
ARM_INS_IT,
|
|
ARM_INS_LSL,
|
|
ARM_INS_LSR,
|
|
ARM_INS_ORN,
|
|
ARM_INS_ROR,
|
|
ARM_INS_RRX,
|
|
ARM_INS_SUBS,
|
|
ARM_INS_SUBW,
|
|
ARM_INS_TBB,
|
|
ARM_INS_TBH,
|
|
ARM_INS_CBNZ,
|
|
ARM_INS_CBZ,
|
|
ARM_INS_MOVS,
|
|
ARM_INS_POP,
|
|
ARM_INS_PUSH,
|
|
ARM_INS_MAX,
|
|
} arm_insn;
|
|
|
|
//> Group of ARM instructions
|
|
typedef enum arm_insn_group {
|
|
ARM_GRP_INVALID = 0,
|
|
ARM_GRP_CRYPTO,
|
|
ARM_GRP_DATABARRIER,
|
|
ARM_GRP_DIVIDE,
|
|
ARM_GRP_FPARMV8,
|
|
ARM_GRP_MULTPRO,
|
|
ARM_GRP_NEON,
|
|
ARM_GRP_T2EXTRACTPACK,
|
|
ARM_GRP_THUMB2DSP,
|
|
ARM_GRP_TRUSTZONE,
|
|
ARM_GRP_V4T,
|
|
ARM_GRP_V5T,
|
|
ARM_GRP_V5TE,
|
|
ARM_GRP_V6,
|
|
ARM_GRP_V6T2,
|
|
ARM_GRP_V7,
|
|
ARM_GRP_V8,
|
|
ARM_GRP_VFP2,
|
|
ARM_GRP_VFP3,
|
|
ARM_GRP_VFP4,
|
|
ARM_GRP_ARM,
|
|
ARM_GRP_MCLASS,
|
|
ARM_GRP_NOTMCLASS,
|
|
ARM_GRP_THUMB,
|
|
ARM_GRP_THUMB1ONLY,
|
|
ARM_GRP_THUMB2,
|
|
ARM_GRP_PREV8,
|
|
ARM_GRP_FPVMLX,
|
|
ARM_GRP_MULOPS,
|
|
ARM_GRP_CRC,
|
|
ARM_GRP_DPVFP,
|
|
ARM_GRP_V6M,
|
|
|
|
ARM_GRP_JUMP, // all jump instructions (conditional+direct+indirect jumps)
|
|
|
|
ARM_GRP_MAX,
|
|
} arm_insn_group;
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif
|