mirror of
https://github.com/capstone-engine/capstone.git
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590 lines
9.0 KiB
C
590 lines
9.0 KiB
C
/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
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#ifdef CAPSTONE_HAS_ARM64
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#include <stdio.h> // debug
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#include <string.h>
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#include "../../utils.h"
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#include "AArch64Mapping.h"
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#define GET_INSTRINFO_ENUM
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#include "AArch64GenInstrInfo.inc"
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#ifndef CAPSTONE_DIET
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// NOTE: this reg_name_maps[] reflects the order of registers in arm64_reg
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static const char *reg_name_maps[] = {
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NULL, /* ARM64_REG_INVALID */
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"ffr",
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"fp",
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"lr",
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"nzcv",
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"sp",
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"wsp",
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"wzr",
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"xzr",
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"b0",
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"b1",
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"b2",
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"b3",
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"b4",
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"b5",
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"b6",
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"b7",
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"b8",
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"b9",
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"b10",
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"b11",
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"b12",
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"b13",
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"b14",
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"b15",
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"b16",
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"b17",
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"b18",
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"b19",
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"b20",
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"b21",
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"b22",
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"b23",
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"b24",
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"b25",
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"b26",
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"b27",
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"b28",
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"b29",
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"b30",
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"b31",
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"d0",
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"d1",
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"d2",
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"d3",
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"d4",
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"d5",
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"d6",
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"d7",
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"d8",
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"d9",
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"d10",
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"d11",
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"d12",
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"d13",
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"d14",
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"d15",
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"d16",
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"d17",
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"d18",
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"d19",
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"d20",
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"d21",
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"d22",
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"d23",
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"d24",
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"d25",
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"d26",
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"d27",
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"d28",
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"d29",
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"d30",
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"d31",
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"h0",
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"h1",
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"h2",
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"h3",
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"h4",
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"h5",
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"h6",
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"h7",
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"h8",
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"h9",
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"h10",
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"h11",
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"h12",
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"h13",
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"h14",
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"h15",
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"h16",
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"h17",
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"h18",
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"h19",
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"h20",
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"h21",
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"h22",
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"h23",
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"h24",
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"h25",
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"h26",
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"h27",
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"h28",
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"h29",
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"h30",
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"h31",
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"p0",
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"p1",
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"p2",
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"p3",
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"p4",
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"p5",
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"p6",
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"p7",
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"p8",
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"p9",
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"p10",
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"p11",
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"p12",
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"p13",
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"p14",
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"p15",
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"q0",
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"q1",
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"q2",
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"q3",
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"q4",
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"q5",
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"q6",
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"q7",
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"q8",
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"q9",
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"q10",
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"q11",
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"q12",
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"q13",
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"q14",
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"q15",
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"q16",
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"q17",
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"q18",
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"q19",
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"q20",
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"q21",
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"q22",
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"q23",
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"q24",
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"q25",
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"q26",
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"q27",
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"q28",
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"q29",
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"q30",
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"q31",
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"s0",
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"s1",
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"s2",
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"s3",
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"s4",
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"s5",
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"s6",
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"s7",
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"s8",
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"s9",
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"s10",
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"s11",
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"s12",
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"s13",
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"s14",
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"s15",
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"s16",
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"s17",
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"s18",
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"s19",
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"s20",
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"s21",
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"s22",
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"s23",
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"s24",
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"s25",
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"s26",
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"s27",
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"s28",
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"s29",
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"s30",
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"s31",
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"w0",
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"w1",
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"w2",
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"w3",
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"w4",
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"w5",
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"w6",
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"w7",
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"w8",
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"w9",
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"w10",
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"w11",
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"w12",
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"w13",
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"w14",
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"w15",
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"w16",
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"w17",
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"w18",
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"w19",
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"w20",
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"w21",
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"w22",
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"w23",
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"w24",
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"w25",
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"w26",
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"w27",
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"w28",
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"w29",
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"w30",
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"x0",
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"x1",
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"x2",
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"x3",
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"x4",
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"x5",
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"x6",
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"x7",
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"x8",
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"x9",
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"x10",
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"x11",
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"x12",
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"x13",
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"x14",
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"x15",
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"x16",
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"x17",
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"x18",
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"x19",
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"x20",
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"x21",
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"x22",
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"x23",
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"x24",
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"x25",
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"x26",
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"x27",
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"x28",
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"z0",
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"z1",
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"z2",
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"z3",
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"z4",
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"z5",
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"z6",
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"z7",
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"z8",
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"z9",
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"z10",
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"z11",
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"z12",
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"z13",
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"z14",
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"z15",
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"z16",
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"z17",
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"z18",
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"z19",
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"z20",
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"z21",
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"z22",
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"z23",
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"z24",
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"z25",
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"z26",
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"z27",
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"z28",
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"z29",
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"z30",
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"z31",
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"v0",
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"v1",
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"v2",
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"v3",
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"v4",
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"v5",
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"v6",
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"v7",
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"v8",
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"v9",
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"v10",
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"v11",
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"v12",
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"v13",
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"v14",
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"v15",
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"v16",
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"v17",
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"v18",
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"v19",
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"v20",
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"v21",
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"v22",
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"v23",
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"v24",
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"v25",
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"v26",
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"v27",
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"v28",
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"v29",
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"v30",
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"v31",
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};
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#endif
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const char *AArch64_reg_name(csh handle, unsigned int reg)
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{
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#ifndef CAPSTONE_DIET
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if (reg >= ARR_SIZE(reg_name_maps))
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return NULL;
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return reg_name_maps[reg];
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#else
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return NULL;
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#endif
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}
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static const insn_map insns[] = {
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// dummy item
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{
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0, 0,
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#ifndef CAPSTONE_DIET
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{ 0 }, { 0 }, { 0 }, 0, 0
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#endif
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},
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#include "AArch64MappingInsn.inc"
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};
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// given internal insn id, return public instruction info
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void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
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{
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int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
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if (i != 0) {
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insn->id = insns[i].mapid;
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if (h->detail) {
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#ifndef CAPSTONE_DIET
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cs_struct handle;
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handle.detail = h->detail;
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memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
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insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
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memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
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insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
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memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups));
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insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups);
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insn->detail->arm64.update_flags = cs_reg_write((csh)&handle, insn, ARM64_REG_NZCV);
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#endif
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}
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}
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}
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static const char *insn_name_maps[] = {
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NULL, // ARM64_INS_INVALID
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#include "AArch64MappingInsnName.inc"
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};
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const char *AArch64_insn_name(csh handle, unsigned int id)
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{
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#ifndef CAPSTONE_DIET
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if (id >= ARM64_INS_ENDING)
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return NULL;
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if (id < ARR_SIZE(insn_name_maps))
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return insn_name_maps[id];
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// not found
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return NULL;
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#else
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return NULL;
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#endif
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}
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#ifndef CAPSTONE_DIET
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static const name_map group_name_maps[] = {
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// generic groups
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{ ARM64_GRP_INVALID, NULL },
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{ ARM64_GRP_JUMP, "jump" },
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{ ARM64_GRP_CALL, "call" },
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{ ARM64_GRP_RET, "return" },
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{ ARM64_GRP_PRIVILEGE, "privilege" },
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{ ARM64_GRP_INT, "int" },
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{ ARM64_GRP_BRANCH_RELATIVE, "branch_relative" },
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// architecture-specific groups
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{ ARM64_GRP_CRYPTO, "crypto" },
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{ ARM64_GRP_FPARMV8, "fparmv8" },
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{ ARM64_GRP_NEON, "neon" },
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{ ARM64_GRP_CRC, "crc" },
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{ ARM64_GRP_AES, "aes" },
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{ ARM64_GRP_DOTPROD, "dotprod" },
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{ ARM64_GRP_FULLFP16, "fullfp16" },
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{ ARM64_GRP_LSE, "lse" },
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{ ARM64_GRP_RCPC, "rcpc" },
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{ ARM64_GRP_RDM, "rdm" },
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{ ARM64_GRP_SHA2, "sha2" },
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{ ARM64_GRP_SHA3, "sha3" },
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{ ARM64_GRP_SM4, "sm4" },
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{ ARM64_GRP_SVE, "sve" },
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{ ARM64_GRP_V8_1A, "v8_1a" },
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{ ARM64_GRP_V8_3A, "v8_3a" },
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{ ARM64_GRP_V8_4A, "v8_4a" },
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};
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#endif
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const char *AArch64_group_name(csh handle, unsigned int id)
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{
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#ifndef CAPSTONE_DIET
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return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
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#else
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return NULL;
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#endif
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}
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// map instruction name to public instruction ID
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arm64_insn AArch64_map_insn(const char *name)
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{
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unsigned int i;
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for(i = 1; i < ARR_SIZE(insn_name_maps); i++) {
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if (!strcmp(name, insn_name_maps[i]))
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return i;
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}
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// not found
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return ARM64_INS_INVALID;
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}
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// map internal raw vregister to 'public' register
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arm64_reg AArch64_map_vregister(unsigned int r)
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{
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static const unsigned short RegAsmOffsetvreg[] = {
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#include "AArch64GenRegisterV.inc"
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};
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if (r < ARR_SIZE(RegAsmOffsetvreg))
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return RegAsmOffsetvreg[r - 1];
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// cannot find this register
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return 0;
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}
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void arm64_op_addVectorArrSpecifier(MCInst * MI, int sp)
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{
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if (MI->csh->detail) {
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MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].vas = sp;
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}
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}
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void arm64_op_addFP(MCInst *MI, float fp)
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{
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if (MI->csh->detail) {
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MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_FP;
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MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].fp = fp;
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MI->flat_insn->detail->arm64.op_count++;
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}
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}
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void arm64_op_addImm(MCInst *MI, int64_t imm)
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{
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if (MI->csh->detail) {
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MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
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MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)imm;
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MI->flat_insn->detail->arm64.op_count++;
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}
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}
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#ifndef CAPSTONE_DIET
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// map instruction to its characteristics
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typedef struct insn_op {
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unsigned int eflags_update; // how this instruction update status flags
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uint8_t access[5];
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} insn_op;
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static insn_op insn_ops[] = {
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{
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/* NULL item */
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0, { 0 }
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},
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#include "AArch64MappingInsnOp.inc"
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};
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// given internal insn id, return operand access info
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uint8_t *AArch64_get_op_access(cs_struct *h, unsigned int id)
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{
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int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
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if (i != 0) {
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return insn_ops[i].access;
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}
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return NULL;
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}
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void AArch64_reg_access(const cs_insn *insn,
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cs_regs regs_read, uint8_t *regs_read_count,
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cs_regs regs_write, uint8_t *regs_write_count)
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{
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uint8_t i;
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uint8_t read_count, write_count;
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cs_arm64 *arm64 = &(insn->detail->arm64);
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read_count = insn->detail->regs_read_count;
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write_count = insn->detail->regs_write_count;
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// implicit registers
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memcpy(regs_read, insn->detail->regs_read, read_count * sizeof(insn->detail->regs_read[0]));
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memcpy(regs_write, insn->detail->regs_write, write_count * sizeof(insn->detail->regs_write[0]));
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// explicit registers
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for (i = 0; i < arm64->op_count; i++) {
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cs_arm64_op *op = &(arm64->operands[i]);
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switch((int)op->type) {
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case ARM64_OP_REG:
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if ((op->access & CS_AC_READ) && !arr_exist(regs_read, read_count, op->reg)) {
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regs_read[read_count] = (uint16_t)op->reg;
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read_count++;
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}
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if ((op->access & CS_AC_WRITE) && !arr_exist(regs_write, write_count, op->reg)) {
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regs_write[write_count] = (uint16_t)op->reg;
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write_count++;
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}
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break;
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case ARM_OP_MEM:
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// registers appeared in memory references always being read
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if ((op->mem.base != ARM64_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.base)) {
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regs_read[read_count] = (uint16_t)op->mem.base;
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read_count++;
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}
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if ((op->mem.index != ARM64_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.index)) {
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regs_read[read_count] = (uint16_t)op->mem.index;
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read_count++;
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}
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if ((arm64->writeback) && (op->mem.base != ARM64_REG_INVALID) && !arr_exist(regs_write, write_count, op->mem.base)) {
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regs_write[write_count] = (uint16_t)op->mem.base;
|
|
write_count++;
|
|
}
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
*regs_read_count = read_count;
|
|
*regs_write_count = write_count;
|
|
}
|
|
#endif
|
|
|
|
#endif
|