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capstone/arch
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Daniel Collin 83d817339e Fixed incorrect read of 32-bit imm for bsr (#1644)
2020-06-12 23:00:47 +08:00
..
AArch64
Add more cases for LD1 instruction immediate fixups (#1632)
2020-05-10 10:03:52 +08:00
ARM
fix: Remove wrong write in ARM_t2STMDB_UPD instruction (#1588)
2020-02-21 09:56:35 +08:00
BPF
Constify backends (#1549)
2019-12-23 20:30:57 +08:00
EVM
Constify backends (#1549)
2019-12-23 20:30:57 +08:00
M68K
Fixed incorrect read of 32-bit imm for bsr (#1644)
2020-06-12 23:00:47 +08:00
M680X
Constify backends (#1549)
2019-12-23 20:30:57 +08:00
Mips
Constify backends (#1549)
2019-12-23 20:30:57 +08:00
MOS65XX
Constify backends (#1549)
2019-12-23 20:30:57 +08:00
PowerPC
Constify backends (#1549)
2019-12-23 20:30:57 +08:00
RISCV
[RISCV] Use CS_ASSERT (#1493)
2019-05-23 08:25:36 +07:00
Sparc
Constify backends (#1549)
2019-12-23 20:30:57 +08:00
SystemZ
Constify backends (#1549)
2019-12-23 20:30:57 +08:00
TMS320C64x
Constify backends (#1549)
2019-12-23 20:30:57 +08:00
WASM
Constify backends (#1549)
2019-12-23 20:30:57 +08:00
X86
fix bug in displacement offset (#1600)
2020-05-11 02:20:13 +08:00
XCore
Constify backends (#1549)
2019-12-23 20:30:57 +08:00