mirror of
https://github.com/capstone-engine/capstone.git
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b227acc29c
* Basic changes of new arch - BPF * Define some constants * defined some API methods * Able to print MISC instruction * Follow Linux coding style * Ability to show ALU insn names * decode return * Add suite/MC/BPF * decode jump * decode store * decode load * print instruction done * try to implement BPF_reg_access * Implements explicit accessed registers and fix some tiny bugs * Fix unhandled ja case * Added BPF_REG_OFF do fix wrong display in jump class * Great I'm able to decode cBPF with eyes * Fix: misunderstood the 16-byte instruction's imm * Add ldxdw * Add extended-all.cs * Implements cstest/bpf_getdetail.c * Fix memory leak * Add BPF to fuzz * Implemented regs_read and regs_write * Fix missing write-access on ALU's dst * Updated cstool/, test_basic.c, test_detail.c, and test_iter.c * Updated docs * Fix type of cs_bpf#operands * Implements python bindings * Fix some bugs found by self code review * Remove dummy tests * remove typeof * Address comments * Fix MSVC's warnings and add test_bpf.py to bindings/python/Makefile * Fix: call is not offset
281 lines
7.1 KiB
C
281 lines
7.1 KiB
C
/* Capstone Disassembly Engine */
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/* BPF Backend by david942j <david942j@gmail.com>, 2019 */
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#include <capstone/platform.h>
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#include "BPFConstants.h"
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#include "BPFInstPrinter.h"
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#include "BPFMapping.h"
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static cs_bpf_op *expand_bpf_operands(cs_bpf *bpf)
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{
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/* assert(bpf->op_count < 3); */
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return &bpf->operands[bpf->op_count++];
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}
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static void push_op_reg(cs_bpf *bpf, bpf_op_type val, uint8_t ac_mode)
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{
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cs_bpf_op *op = expand_bpf_operands(bpf);
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op->type = BPF_OP_REG;
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op->reg = val;
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op->access = ac_mode;
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}
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static void push_op_imm(cs_bpf *bpf, uint64_t val)
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{
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cs_bpf_op *op = expand_bpf_operands(bpf);
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op->type = BPF_OP_IMM;
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op->imm = val;
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}
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static void push_op_off(cs_bpf *bpf, uint32_t val)
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{
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cs_bpf_op *op = expand_bpf_operands(bpf);
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op->type = BPF_OP_OFF;
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op->off = val;
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}
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static void push_op_mem(cs_bpf *bpf, bpf_reg reg, uint32_t val)
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{
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cs_bpf_op *op = expand_bpf_operands(bpf);
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op->type = BPF_OP_MEM;
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op->mem.base = reg;
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op->mem.disp = val;
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}
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static void push_op_mmem(cs_bpf *bpf, uint32_t val)
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{
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cs_bpf_op *op = expand_bpf_operands(bpf);
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op->type = BPF_OP_MMEM;
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op->mmem = val;
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}
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static void push_op_msh(cs_bpf *bpf, uint32_t val)
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{
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cs_bpf_op *op = expand_bpf_operands(bpf);
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op->type = BPF_OP_MSH;
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op->msh = val;
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}
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static void push_op_ext(cs_bpf *bpf, bpf_ext_type val)
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{
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cs_bpf_op *op = expand_bpf_operands(bpf);
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op->type = BPF_OP_EXT;
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op->ext = val;
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}
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static void convert_operands(MCInst *MI, cs_bpf *bpf)
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{
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unsigned opcode = MCInst_getOpcode(MI);
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unsigned mc_op_count = MCInst_getNumOperands(MI);
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MCOperand *op;
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MCOperand *op2;
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unsigned i;
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bpf->op_count = 0;
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if (BPF_CLASS(opcode) == BPF_CLASS_LD || BPF_CLASS(opcode) == BPF_CLASS_LDX) {
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switch (BPF_MODE(opcode)) {
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case BPF_MODE_IMM:
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push_op_imm(bpf, MCOperand_getImm(MCInst_getOperand(MI, 0)));
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break;
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case BPF_MODE_ABS:
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op = MCInst_getOperand(MI, 0);
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push_op_mem(bpf, BPF_REG_INVALID, (uint32_t)MCOperand_getImm(op));
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break;
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case BPF_MODE_IND:
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op = MCInst_getOperand(MI, 0);
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op2 = MCInst_getOperand(MI, 1);
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push_op_mem(bpf, MCOperand_getReg(op), (uint32_t)MCOperand_getImm(op2));
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break;
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case BPF_MODE_MEM:
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if (EBPF_MODE(MI->csh)) {
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/* ldx{w,h,b,dw} dst, [src+off] */
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push_op_reg(bpf, MCOperand_getReg(MCInst_getOperand(MI, 0)), CS_AC_WRITE);
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op = MCInst_getOperand(MI, 1);
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op2 = MCInst_getOperand(MI, 2);
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push_op_mem(bpf, MCOperand_getReg(op), (uint32_t)MCOperand_getImm(op2));
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}
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else {
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push_op_mmem(bpf, (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, 0)));
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}
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break;
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case BPF_MODE_LEN:
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push_op_ext(bpf, BPF_EXT_LEN);
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break;
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case BPF_MODE_MSH:
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op = MCInst_getOperand(MI, 0);
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push_op_msh(bpf, (uint32_t)MCOperand_getImm(op));
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break;
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/* case BPF_MODE_XADD: // not exists */
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}
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return;
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}
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if (BPF_CLASS(opcode) == BPF_CLASS_ST || BPF_CLASS(opcode) == BPF_CLASS_STX) {
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if (!EBPF_MODE(MI->csh)) {
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// cBPF has only one case - st* M[k]
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push_op_mmem(bpf, (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, 0)));
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return;
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}
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/* eBPF has two cases:
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* - st [dst + off], src
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* - xadd [dst + off], src
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* they have same form of operands.
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*/
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op = MCInst_getOperand(MI, 0);
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op2 = MCInst_getOperand(MI, 1);
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push_op_mem(bpf, MCOperand_getReg(op), (uint32_t)MCOperand_getImm(op2));
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op = MCInst_getOperand(MI, 2);
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if (MCOperand_isImm(op))
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push_op_imm(bpf, MCOperand_getImm(op));
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else if (MCOperand_isReg(op))
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push_op_reg(bpf, MCOperand_getReg(op), CS_AC_READ);
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return;
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}
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if (BPF_CLASS(opcode) == BPF_CLASS_JMP) {
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for (i = 0; i < mc_op_count; i++) {
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op = MCInst_getOperand(MI, i);
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if (MCOperand_isImm(op)) {
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/* decide the imm is BPF_OP_IMM or BPF_OP_OFF type here */
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/*
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* 1. ja +off
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* 2. j {x,k}, +jt, +jf // cBPF
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* 3. j dst_reg, {src_reg, k}, +off // eBPF
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*/
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if (BPF_OP(opcode) == BPF_JUMP_JA ||
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(!EBPF_MODE(MI->csh) && i >= 1) ||
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(EBPF_MODE(MI->csh) && i == 2))
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push_op_off(bpf, (uint32_t)MCOperand_getImm(op));
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else
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push_op_imm(bpf, MCOperand_getImm(op));
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}
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else if (MCOperand_isReg(op)) {
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push_op_reg(bpf, MCOperand_getReg(op), CS_AC_READ);
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}
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}
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return;
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}
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if (!EBPF_MODE(MI->csh)) {
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/* In cBPF mode, all registers in operands are accessed as read */
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for (i = 0; i < mc_op_count; i++) {
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op = MCInst_getOperand(MI, i);
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if (MCOperand_isImm(op))
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push_op_imm(bpf, MCOperand_getImm(op));
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else if (MCOperand_isReg(op))
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push_op_reg(bpf, MCOperand_getReg(op), CS_AC_READ);
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}
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return;
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}
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/* remain cases are: eBPF mode && ALU */
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/* if (BPF_CLASS(opcode) == BPF_CLASS_ALU || BPF_CLASS(opcode) == BPF_CLASS_ALU64) */
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/* We have three types:
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* 1. {l,b}e dst // dst = byteswap(dst)
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* 2. neg dst // dst = -dst
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* 3. <op> dst, {src_reg, imm} // dst = dst <op> src
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* so we can simply check the number of operands,
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* exactly one operand means we are in case 1. and 2.,
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* otherwise in case 3.
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*/
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if (mc_op_count == 1) {
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op = MCInst_getOperand(MI, 0);
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push_op_reg(bpf, MCOperand_getReg(op), CS_AC_READ | CS_AC_WRITE);
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}
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else { // if (mc_op_count == 2)
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op = MCInst_getOperand(MI, 0);
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push_op_reg(bpf, MCOperand_getReg(op), CS_AC_READ | CS_AC_WRITE);
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op = MCInst_getOperand(MI, 1);
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if (MCOperand_isImm(op))
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push_op_imm(bpf, MCOperand_getImm(op));
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else if (MCOperand_isReg(op))
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push_op_reg(bpf, MCOperand_getReg(op), CS_AC_READ);
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}
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}
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static void print_operand(MCInst *MI, struct SStream *O, const cs_bpf_op *op)
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{
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switch (op->type) {
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case BPF_OP_INVALID:
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SStream_concat(O, "invalid");
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break;
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case BPF_OP_REG:
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SStream_concat(O, BPF_reg_name((csh)MI->csh, op->reg));
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break;
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case BPF_OP_IMM:
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SStream_concat(O, "0x%" PRIx64, op->imm);
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break;
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case BPF_OP_OFF:
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SStream_concat(O, "+0x%x", op->off);
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break;
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case BPF_OP_MEM:
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SStream_concat(O, "[");
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if (op->mem.base != BPF_REG_INVALID)
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SStream_concat(O, BPF_reg_name((csh)MI->csh, op->mem.base));
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if (op->mem.disp != 0) {
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if (op->mem.base != BPF_REG_INVALID)
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SStream_concat(O, "+");
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SStream_concat(O, "0x%x", op->mem.disp);
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}
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if (op->mem.base == BPF_REG_INVALID && op->mem.disp == 0) // special case
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SStream_concat(O, "0x0");
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SStream_concat(O, "]");
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break;
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case BPF_OP_MMEM:
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SStream_concat(O, "m[0x%x]", op->mmem);
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break;
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case BPF_OP_MSH:
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SStream_concat(O, "4*([0x%x]&0xf)", op->msh);
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break;
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case BPF_OP_EXT:
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switch (op->ext) {
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case BPF_EXT_LEN:
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SStream_concat(O, "#len");
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break;
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}
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break;
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}
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}
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/*
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* 1. human readable mnemonic
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* 2. set pubOpcode (BPF_INSN_*)
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* 3. set detail->bpf.operands
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* */
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void BPF_printInst(MCInst *MI, struct SStream *O, void *PrinterInfo)
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{
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int i;
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cs_insn insn;
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cs_bpf bpf;
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insn.detail = NULL;
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/* set pubOpcode as instruction id */
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BPF_get_insn_id((cs_struct*)MI->csh, &insn, MCInst_getOpcode(MI));
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MCInst_setOpcodePub(MI, insn.id);
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SStream_concat(O, BPF_insn_name((csh)MI->csh, insn.id));
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convert_operands(MI, &bpf);
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for (i = 0; i < bpf.op_count; i++) {
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if (i == 0)
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SStream_concat(O, "\t");
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else
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SStream_concat(O, ", ");
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print_operand(MI, O, &bpf.operands[i]);
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}
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#ifndef CAPSTONE_DIET
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if (MI->flat_insn->detail) {
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MI->flat_insn->detail->bpf = bpf;
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}
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#endif
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}
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