mirror of
https://github.com/capstone-engine/capstone.git
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b8fcf27b22
* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h
* Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction
* Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h
* Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter
* Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h
* Backport it from: 0db412ce3b
* All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly.
* Add refactored cs.c for RISCV
* Testing all I instructions in test_riscv.c
* Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture
* Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c
* fixed bug related to incorrect initialization of memory after malloc
* fix compile bug
* Fix compile errors.
* move riscv.h to include/capstone
* fix indentation issues
* fix coding style issues
* Fix indentation issues
* fix coding style
* Move variable declaration to the top of the block
* Fix coding indentation
* Move some stuff into RISCVMappingInsn.inc
* Fix code sytle
* remove cs_mode support for RISCV
* update asmwriter-inc to LLVM upstream
* update the .inc files to riscv upstream
* update riscv disassembler function for suport 16bit instructions
* update printer & tablegen inc files which have fixed arguments mismatch
* update headers and mapping source
* add riscv architecture specific test code
* fix all RISCV tons of compiler errors
* pass final tests
* add riscv tablegen patchs
* merge with upstream/next
* fix cstool missing riscv file
* fix root Makefile
* add new TableGen patchs for riscv
* fix cmakefile.txt of missing one riscv file
* fix declaration conflict
* fix incompatible declaration type
* change riscvc from arch to mode
* fix test_riscv warnning
* fix code style and add riscv part of test_basic
* add RISCV64 mode
* add suite for riscv
* crack fuzz test
* fix getfeaturebits test add riscvc
* fix test missing const qualifier warnning
* fix testcase type mismatch
* fix return value missing
* change getfeaturebits test
* add test cs files
* using a winder type contain the decode string
* fix a copy typo
* remove useless mode for riscv
* change cs file blank type
* add repo for update_riscv & fix cstool missing riscv mode
* fix typo
* add riscv for cstool useage
* add TableGen patch for riscv asmwriter
* clean ctags file
* remove black comment line
* fix fuzz related something
* fix missing RISCV string of fuzz
* update readme, etc..
* add riscv *.s.cs file
* add riscv *.s.cs file & clear ctags
* clear useless array declarations at capstone_test
* update to 5e4069f
* update readme change name more formal
* change position of riscv after bpf and modify copyright more uniform
* clear useless ctags file
* change blank with tab in riscv.h
* add riscv python bindings
* add riscv in __init__.py
* fix riscv define value for python binding
* fix test_riscv.py typo
* add missing riscvc in __init__.py of python bindings
* fix alias-insn printer bug, remove useless newline
* change inst print delimter from tab to bankspace for travis
* add riscv tablegen patch
* fix inst output more consistency
* add TableGen patch which fix inst output formal
* crack the effective address output for detail and change register print function
* fix not detail crash bug
* change item declaration position at cs_riscv
* update riscv.py
* change function name more meaningfull
* update python binding makefile
* fix register enum sequence according to riscvgenreginfo.inc
* test function name
* add enum s0/fp in riscv.h & update riscv_const.py
* add register name enum
107 lines
2.7 KiB
C++
107 lines
2.7 KiB
C++
//===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains small standalone enum definitions for the RISCV target
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// useful for the compiler back-end and the MC libraries.
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//
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//===----------------------------------------------------------------------===//
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#ifndef CS_RISCVBASEINFO_H
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#define CS_RISCVBASEINFO_H
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#include <assert.h>
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//#include "RISCVMCTargetDesc.h"
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// RISCVII - This namespace holds all of the target specific flags that
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// instruction info tracks. All definitions must match RISCVInstrFormats.td.
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enum {
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IRISCVII_InstFormatPseudo = 0,
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IRISCVII_InstFormatR = 1,
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IRISCVII_InstFormatR4 = 2,
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IRISCVII_InstFormatI = 3,
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IRISCVII_InstFormatS = 4,
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IRISCVII_InstFormatB = 5,
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IRISCVII_InstFormatU = 6,
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IRISCVII_InstFormatJ = 7,
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IRISCVII_InstFormatCR = 8,
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IRISCVII_InstFormatCI = 9,
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IRISCVII_InstFormatCSS = 10,
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IRISCVII_InstFormatCIW = 11,
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IRISCVII_InstFormatCL = 12,
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IRISCVII_InstFormatCS = 13,
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IRISCVII_InstFormatCA = 14,
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IRISCVII_InstFormatCB = 15,
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IRISCVII_InstFormatCJ = 16,
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IRISCVII_InstFormatOther = 17,
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IRISCVII_InstFormatMask = 31
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};
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enum {
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RISCVII_MO_None,
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RISCVII_MO_LO,
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RISCVII_MO_HI,
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RISCVII_MO_PCREL_HI,
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};
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// Describes the predecessor/successor bits used in the FENCE instruction.
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enum FenceField {
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RISCVFenceField_I = 8,
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RISCVFenceField_O = 4,
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RISCVFenceField_R = 2,
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RISCVFenceField_W = 1
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};
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// Describes the supported floating point rounding mode encodings.
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enum RoundingMode {
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RISCVFPRndMode_RNE = 0,
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RISCVFPRndMode_RTZ = 1,
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RISCVFPRndMode_RDN = 2,
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RISCVFPRndMode_RUP = 3,
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RISCVFPRndMode_RMM = 4,
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RISCVFPRndMode_DYN = 7,
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RISCVFPRndMode_Invalid
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};
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inline static const char *roundingModeToString(enum RoundingMode RndMode)
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{
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switch (RndMode) {
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default:
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assert(0 && "Unknown floating point rounding mode");
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case RISCVFPRndMode_RNE:
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return "rne";
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case RISCVFPRndMode_RTZ:
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return "rtz";
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case RISCVFPRndMode_RDN:
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return "rdn";
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case RISCVFPRndMode_RUP:
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return "rup";
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case RISCVFPRndMode_RMM:
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return "rmm";
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case RISCVFPRndMode_DYN:
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return "dyn";
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}
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}
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inline static bool RISCVFPRndMode_isValidRoundingMode(unsigned Mode)
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{
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switch (Mode) {
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default:
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return false;
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case RISCVFPRndMode_RNE:
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case RISCVFPRndMode_RTZ:
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case RISCVFPRndMode_RDN:
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case RISCVFPRndMode_RUP:
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case RISCVFPRndMode_RMM:
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case RISCVFPRndMode_DYN:
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return true;
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}
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}
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#endif
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