mirror of
https://github.com/capstone-engine/capstone.git
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b8fcf27b22
* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h
* Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction
* Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h
* Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter
* Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h
* Backport it from: 0db412ce3b
* All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly.
* Add refactored cs.c for RISCV
* Testing all I instructions in test_riscv.c
* Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture
* Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c
* fixed bug related to incorrect initialization of memory after malloc
* fix compile bug
* Fix compile errors.
* move riscv.h to include/capstone
* fix indentation issues
* fix coding style issues
* Fix indentation issues
* fix coding style
* Move variable declaration to the top of the block
* Fix coding indentation
* Move some stuff into RISCVMappingInsn.inc
* Fix code sytle
* remove cs_mode support for RISCV
* update asmwriter-inc to LLVM upstream
* update the .inc files to riscv upstream
* update riscv disassembler function for suport 16bit instructions
* update printer & tablegen inc files which have fixed arguments mismatch
* update headers and mapping source
* add riscv architecture specific test code
* fix all RISCV tons of compiler errors
* pass final tests
* add riscv tablegen patchs
* merge with upstream/next
* fix cstool missing riscv file
* fix root Makefile
* add new TableGen patchs for riscv
* fix cmakefile.txt of missing one riscv file
* fix declaration conflict
* fix incompatible declaration type
* change riscvc from arch to mode
* fix test_riscv warnning
* fix code style and add riscv part of test_basic
* add RISCV64 mode
* add suite for riscv
* crack fuzz test
* fix getfeaturebits test add riscvc
* fix test missing const qualifier warnning
* fix testcase type mismatch
* fix return value missing
* change getfeaturebits test
* add test cs files
* using a winder type contain the decode string
* fix a copy typo
* remove useless mode for riscv
* change cs file blank type
* add repo for update_riscv & fix cstool missing riscv mode
* fix typo
* add riscv for cstool useage
* add TableGen patch for riscv asmwriter
* clean ctags file
* remove black comment line
* fix fuzz related something
* fix missing RISCV string of fuzz
* update readme, etc..
* add riscv *.s.cs file
* add riscv *.s.cs file & clear ctags
* clear useless array declarations at capstone_test
* update to 5e4069f
* update readme change name more formal
* change position of riscv after bpf and modify copyright more uniform
* clear useless ctags file
* change blank with tab in riscv.h
* add riscv python bindings
* add riscv in __init__.py
* fix riscv define value for python binding
* fix test_riscv.py typo
* add missing riscvc in __init__.py of python bindings
* fix alias-insn printer bug, remove useless newline
* change inst print delimter from tab to bankspace for travis
* add riscv tablegen patch
* fix inst output more consistency
* add TableGen patch which fix inst output formal
* crack the effective address output for detail and change register print function
* fix not detail crash bug
* change item declaration position at cs_riscv
* update riscv.py
* change function name more meaningfull
* update python binding makefile
* fix register enum sequence according to riscvgenreginfo.inc
* test function name
* add enum s0/fp in riscv.h & update riscv_const.py
* add register name enum
127 lines
3.9 KiB
Python
Executable File
127 lines
3.9 KiB
Python
Executable File
#!/usr/bin/python
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# Simple fuzzing tool by disassembling random code. By Nguyen Anh Quynh, 2014
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# Syntax:
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# ./suite/fuzz.py --> Fuzz all archs
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# ./suite/fuzz.py x86 --> Fuzz all X86 (all 16bit, 32bit, 64bit)
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# ./suite/fuzz.py x86-16 --> Fuzz X86-32 arch only
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# ./suite/fuzz.py x86-32 --> Fuzz X86-32 arch only
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# ./suite/fuzz.py x86-64 --> Fuzz X86-64 arch only
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# ./suite/fuzz.py arm --> Fuzz all ARM (arm, thumb)
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# ./suite/fuzz.py aarch64 --> Fuzz ARM-64
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# ./suite/fuzz.py mips --> Fuzz all Mips (32bit, 64bit)
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# ./suite/fuzz.py ppc --> Fuzz PPC
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from capstone import *
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from time import time
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from random import randint
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import sys
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# file providing code to disassemble
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FILE = '/usr/bin/python'
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TIMES = 64
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INTERVALS = (4, 5, 7, 9, 11, 13)
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all_tests = (
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(CS_ARCH_X86, CS_MODE_16, "X86-16bit (Intel syntax)", 0),
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(CS_ARCH_X86, CS_MODE_16, "X86-16bit (ATT syntax)", CS_OPT_SYNTAX_ATT),
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(CS_ARCH_X86, CS_MODE_32, "X86-32 (Intel syntax)", 0),
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(CS_ARCH_X86, CS_MODE_32, "X86-32 (ATT syntax)", CS_OPT_SYNTAX_ATT),
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(CS_ARCH_X86, CS_MODE_64, "X86-64 (Intel syntax)", 0),
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(CS_ARCH_X86, CS_MODE_64, "X86-64 (ATT syntax)", CS_OPT_SYNTAX_ATT),
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(CS_ARCH_ARM, CS_MODE_ARM, "ARM", 0),
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(CS_ARCH_ARM, CS_MODE_THUMB, "THUMB (ARM)", 0),
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(CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, "MIPS-32 (Big-endian)", 0),
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(CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, "MIPS-64-EL (Little-endian)", 0),
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(CS_ARCH_ARM64, CS_MODE_ARM, "ARM-64 (AArch64)", 0),
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(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, "PPC", 0),
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(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, "PPC, print register with number only", CS_OPT_SYNTAX_NOREGNAME),
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(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, "Sparc", 0),
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(CS_ARCH_SYSZ, 0, "SystemZ", 0),
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(CS_ARCH_XCORE, 0, "XCore", 0),
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(CS_ARCH_M68K, 0, "M68K", 0),
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(CS_ARCH_RISCV, CS_MODE_RISCV32, "riscv32", 0),
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(CS_ARCH_RISCV, CS_MODE_RISCV64, "riscv64", 0),
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)
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# for debugging
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def to_hex(s):
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return " ".join("0x" + "{0:x}".format(ord(c)).zfill(2) for c in s) # <-- Python 3 is OK
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# read @size bytes from @f & return data.
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# return None when there is not enough data
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def get_code(f, size):
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code = f.read(size)
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if len(code) != size: # reached end-of-file?
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# then reset file position to begin-of-file
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f.seek(0)
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return None
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return code
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def cs(md, code):
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insns = md.disasm(code, 0)
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for i in insns:
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if i.address == 0x100000:
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print i
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def cs_lite(md, code):
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insns = md.disasm_lite(code, 0)
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for (addr, size, mnem, ops) in insns:
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if addr == 0x100000:
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print i
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cfile = open(FILE)
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for (arch, mode, comment, syntax) in all_tests:
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try:
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request = sys.argv[1]
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if not request in comment.lower():
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continue
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except:
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pass
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try:
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md = Cs(arch, mode)
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md.detail = True
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if syntax != 0:
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md.syntax = syntax
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# test disasm()
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print("\nFuzzing disasm() @platform: %s" %comment)
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for ii in INTERVALS:
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print("Interval: %u" %ii)
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for j in xrange(1, TIMES):
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while (True):
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code = get_code(cfile, j * ii)
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if code is None:
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# EOF? break
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break
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#print to_hex(code)
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cs(md, code)
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# test disasm_lite()
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print("Fuzzing disasm_lite() @platform: %s" %comment)
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for ii in INTERVALS:
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print("Interval: %u" %ii)
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for j in xrange(1, TIMES):
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while (True):
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code = get_code(cfile, j * ii)
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if code is None:
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# EOF? break
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break
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#print to_hex(code)
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cs_lite(md, code)
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except CsError as e:
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print("ERROR: %s" %e)
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