capstone/arch/X86
Richard Henderson 936dca0e2d Constify backends (#1549)
* Constify registerinfo.py output

Remove two conditionals separating identical bits of code.
Add "const" markup to MCRegisterDesc and MCRegisterClass.

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify instrinfo-arch.py output

In this case, do not actively strip const.

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the AArch64 backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the EVM backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify M680X backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify M68K backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the Mips backend

The Mips backend has not been regenerated from LLVM recently,
and there are more fixups required than I'd like.  Just apply
the fixes to the tables by hand for now.

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the Sparc backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the TMS320C64x backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the X86 backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the XCore backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify systemregister.py output

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the ARM backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the PowerPC backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the MOS65XX backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the SystemZ backend

The mapping of system register to indexes is easy to
generate read-only.  Since we know the indexes are
between 0 and 31, use uint8_t instead of unsigned.

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the WASM backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify cs.c

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the BPF backend

Signed-off-by: Richard Henderson <rth@twiddle.net>
2019-12-23 20:30:57 +08:00
..
X86ATTInstPrinter.c Constify backends (#1549) 2019-12-23 20:30:57 +08:00
X86BaseInfo.h sync with LLVM 7.0.1. X86 is first 2019-02-26 15:19:51 +08:00
X86Disassembler.c x86: fix missing opcode byte in #1505 2019-06-08 12:21:50 +08:00
X86Disassembler.h sync with LLVM 7.0.1. X86 is first 2019-02-26 15:19:51 +08:00
X86DisassemblerDecoder.c Constify backends (#1549) 2019-12-23 20:30:57 +08:00
X86DisassemblerDecoder.h x86: recognize xrelease lock 2019-05-14 09:59:23 +08:00
X86DisassemblerDecoderCommon.h sync with LLVM 7.0.1. X86 is first 2019-02-26 15:19:51 +08:00
X86GenAsmWriter1_reduce.inc x86: update tablegen to fix MOV CRx/DRx, TEST & LOCK prefix in #1456 & #1472 2019-05-06 17:28:37 +08:00
X86GenAsmWriter1.inc fix some compilation issues when DIET mode is on 2019-06-24 12:52:38 +08:00
X86GenAsmWriter_reduce.inc x86: update tablegen to fix MOV CRx/DRx, TEST & LOCK prefix in #1456 & #1472 2019-05-06 17:28:37 +08:00
X86GenAsmWriter.inc x86: update tablegen to fix MOV CRx/DRx, TEST & LOCK prefix in #1456 & #1472 2019-05-06 17:28:37 +08:00
X86GenDisassemblerTables2.inc x86: update ISA & mapping tables 2019-03-01 01:05:52 +08:00
X86GenDisassemblerTables_reduce2.inc x86: update ISA & mapping tables 2019-03-01 01:05:52 +08:00
X86GenDisassemblerTables_reduce.inc x86: update tablegen to fix MOV CRx/DRx, TEST & LOCK prefix in #1456 & #1472 2019-05-06 17:28:37 +08:00
X86GenDisassemblerTables.inc x86: update tablegen to fix MOV CRx/DRx, TEST & LOCK prefix in #1456 & #1472 2019-05-06 17:28:37 +08:00
X86GenInstrInfo_reduce.inc x86: update tablegen to fix MOV CRx/DRx, TEST & LOCK prefix in #1456 & #1472 2019-05-06 17:28:37 +08:00
X86GenInstrInfo.inc x86: update tablegen to fix MOV CRx/DRx, TEST & LOCK prefix in #1456 & #1472 2019-05-06 17:28:37 +08:00
X86GenRegisterInfo.inc Constify backends (#1549) 2019-12-23 20:30:57 +08:00
X86GenRegisterName1.inc x86: new files X86GenRegisterName.inc & X86GenRegisterName1.inc 2019-03-04 00:56:07 +08:00
X86GenRegisterName.inc x86: new files X86GenRegisterName.inc & X86GenRegisterName1.inc 2019-03-04 00:56:07 +08:00
X86ImmSize.inc x86: update ISA & mapping tables 2019-03-01 01:05:52 +08:00
X86InstPrinter.h sync with LLVM 7.0.1. X86 is first 2019-02-26 15:19:51 +08:00
X86InstPrinterCommon.c sync with LLVM 7.0.1. X86 is first 2019-02-26 15:19:51 +08:00
X86InstPrinterCommon.h sync with LLVM 7.0.1. X86 is first 2019-02-26 15:19:51 +08:00
X86IntelInstPrinter.c Constify backends (#1549) 2019-12-23 20:30:57 +08:00
X86Lookup16_reduce.inc x86: update tablegen to fix MOV CRx/DRx, TEST & LOCK prefix in #1456 & #1472 2019-05-06 17:28:37 +08:00
X86Lookup16.inc x86: update tablegen to fix MOV CRx/DRx, TEST & LOCK prefix in #1456 & #1472 2019-05-06 17:28:37 +08:00
X86Mapping.c Constify backends (#1549) 2019-12-23 20:30:57 +08:00
X86Mapping.h Constify backends (#1549) 2019-12-23 20:30:57 +08:00
X86MappingInsn_reduce.inc x86: update tablegen to fix MOV CRx/DRx, TEST & LOCK prefix in #1456 & #1472 2019-05-06 17:28:37 +08:00
X86MappingInsn.inc x86: update tablegen to fix MOV CRx/DRx, TEST & LOCK prefix in #1456 & #1472 2019-05-06 17:28:37 +08:00
X86MappingInsnName_reduce.inc x86: update ISA & mapping tables 2019-03-01 01:05:52 +08:00
X86MappingInsnName.inc x86: update ISA & mapping tables 2019-03-01 01:05:52 +08:00
X86MappingInsnOp_reduce.inc Undo rollback of 3 movbe instruction's operand access fixes (#1512) 2019-07-01 10:36:51 +08:00
X86MappingInsnOp.inc Undo rollback of 3 movbe instruction's operand access fixes (#1512) 2019-07-01 10:36:51 +08:00
X86MappingReg.inc x86: add BND registers. this fixes OSS-fuzz issue 13467 2019-03-02 14:58:29 +08:00
X86Module.c Declare global arch arrays with contents (next branch) (#1186) 2018-06-24 21:05:04 +08:00
X86Module.h Declare global arch arrays with contents (next branch) (#1186) 2018-06-24 21:05:04 +08:00