mirror of
https://github.com/capstone-engine/capstone.git
synced 2025-01-05 20:58:32 +00:00
21f7bc85f9
* Fix leaks * Remove unnecessary new lines * Add checks for actual buffer length before attempting reading it. * Xtensa: add xtensa support * Xtensa fixes - fix MCExpr - fix Xtensa_add_cs_detail - add `add_cs_detail` - add `MCExpr *MCOperand_getExpr(const MCOperand *MC)` `void printExpr(const MCExpr *E, SStream *O)` autosync fix - fix StreamOperation.py - replace `report_fatal_error` with `CS_ASSERT` - fix patch StreamOperation.py - replace `assert` with `CS_ASSERT` - fix AddCSDetail.py - fix QualifiedIdentifier * Xtensa fix * Xtensa fix .py * add Xtensa to the fuzzer * Xtensa `LITBASE`: add a basic implementation * Xtensa `LITBASE`: add a integration test * Xtensa: fix cs_v6_release_guide.md * Xtensa: fix `XTENSA_OP_GROUP_MEMOPERAND` * Xtensa: fix * Xtensa: fix Targets.py * Use isUint and isInt all over Xtensa * Add documentation about LITBASE functionality * Fix typo * Replace hard with Capstone assert * Xtensa: fix arch_config.json * Xtensa: fix --------- Co-authored-by: Rot127 <unisono@quyllur.org>
427 lines
6.7 KiB
C
427 lines
6.7 KiB
C
#include "platform.h"
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struct platform platforms[] = {
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{
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// item 0
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CS_ARCH_X86,
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CS_MODE_32,
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"X86 32 (Intel syntax)",
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"x32"
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},
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{
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// item 1
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CS_ARCH_X86,
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CS_MODE_64,
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"X86 64 (Intel syntax)",
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"x64"
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},
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{
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// item 2
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CS_ARCH_ARM,
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CS_MODE_ARM,
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"ARM",
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"arm"
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},
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{
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// item 3
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CS_ARCH_ARM,
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CS_MODE_THUMB,
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"THUMB",
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"thumb"
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},
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{
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// item 4
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CS_ARCH_ARM,
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(cs_mode) (CS_MODE_ARM + CS_MODE_V8),
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"Arm-V8",
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"armv8"
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},
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{
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// item 5
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CS_ARCH_ARM,
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(cs_mode) (CS_MODE_THUMB + CS_MODE_V8),
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"THUMB+V8",
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"thumbv8"
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},
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{
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// item 6
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CS_ARCH_ARM,
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(cs_mode) (CS_MODE_THUMB + CS_MODE_MCLASS),
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"Thumb-MClass",
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"cortexm"
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},
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{
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// item 7
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CS_ARCH_AARCH64,
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(cs_mode) 0,
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"AARCH64",
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"aarch64"
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},
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{
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// item 8
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CS_ARCH_MIPS,
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(cs_mode) (CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN),
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"MIPS-32 (Big-endian)",
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"mipsbe"
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},
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{
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// item 9
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CS_ARCH_MIPS,
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(cs_mode) (CS_MODE_MIPS32 + CS_MODE_MICRO),
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"MIPS-32 (micro)",
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"mipsmicro"
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},
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{
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//item 10
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CS_ARCH_MIPS,
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CS_MODE_MIPS64,
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"MIPS-64-EL (Little-endian)",
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"mips64"
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},
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{
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//item 11
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CS_ARCH_MIPS,
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CS_MODE_MIPS32,
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"MIPS-32-EL (Little-endian)",
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"mips"
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},
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{
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//item 12
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CS_ARCH_MIPS,
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(cs_mode) (CS_MODE_MIPS64 + CS_MODE_BIG_ENDIAN),
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"MIPS-64 (Big-endian)",
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"mips64be"
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},
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{
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//item 13
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CS_ARCH_MIPS,
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(cs_mode) (CS_MODE_MIPS32 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
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"MIPS-32 | Micro (Big-endian)",
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"mipsbemicro"
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},
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{
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//item 14
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CS_ARCH_PPC,
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CS_MODE_64 | CS_MODE_BIG_ENDIAN,
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"PPC-64",
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"ppc64be"
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},
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{
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//item 15
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CS_ARCH_SPARC,
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CS_MODE_BIG_ENDIAN,
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"Sparc",
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"sparc"
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},
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{
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//item 16
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CS_ARCH_SPARC,
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(cs_mode) (CS_MODE_BIG_ENDIAN + CS_MODE_V9),
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"SparcV9",
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"sparcv9"
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},
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{
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//item 17
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CS_ARCH_SYSTEMZ,
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(cs_mode) CS_MODE_BIG_ENDIAN,
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"SystemZ",
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"systemz"
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},
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{
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//item 18
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CS_ARCH_XCORE,
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(cs_mode) 0,
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"XCore",
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"xcore"
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},
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{
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//item 19
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CS_ARCH_MIPS,
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(cs_mode) (CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN),
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"MIPS-32R6 (Big-endian)",
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"mipsbe32r6"
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},
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{
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//item 20
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CS_ARCH_MIPS,
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(cs_mode) (CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
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"MIPS-32R6 (Micro+Big-endian)",
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"mipsbe32r6micro"
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},
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{
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//item 21
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CS_ARCH_MIPS,
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CS_MODE_MIPS32R6,
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"MIPS-32R6 (Little-endian)",
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"mips32r6"
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},
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{
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//item 22
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CS_ARCH_MIPS,
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(cs_mode) (CS_MODE_MIPS32R6 + CS_MODE_MICRO),
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"MIPS-32R6 (Micro+Little-endian)",
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"mips32r6micro"
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},
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{
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//item 23
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CS_ARCH_M68K,
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(cs_mode) 0,
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"M68K",
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"m68k"
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},
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{
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//item 24
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CS_ARCH_M680X,
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(cs_mode) CS_MODE_M680X_6809,
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"M680X_M6809",
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"m6809"
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},
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{
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//item 25
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CS_ARCH_EVM,
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(cs_mode) 0,
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"EVM",
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"evm"
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},
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{
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//item 26
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CS_ARCH_MOS65XX,
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(cs_mode) 0,
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"MOS65XX",
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"mos65xx"
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},
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{
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//item 27
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CS_ARCH_TMS320C64X,
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CS_MODE_BIG_ENDIAN,
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"tms320c64x",
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"tms320c64x"
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},
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{
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//item 28
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CS_ARCH_WASM,
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(cs_mode) 0,
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"WASM",
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"wasm"
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},
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{
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//item 29
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CS_ARCH_BPF,
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CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_CLASSIC,
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"cBPF",
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"bpf"
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},
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{
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//item 30
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CS_ARCH_BPF,
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CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED,
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"eBPF",
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"ebpf"
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},
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{
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//item 31
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CS_ARCH_BPF,
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CS_MODE_BIG_ENDIAN | CS_MODE_BPF_CLASSIC,
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"cBPF",
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"bpfbe"
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},
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{
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//item 32
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CS_ARCH_BPF,
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CS_MODE_BIG_ENDIAN | CS_MODE_BPF_EXTENDED,
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"eBPF",
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"ebpfbe"
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},
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{
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// item 33
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CS_ARCH_X86,
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CS_MODE_16,
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"X86 16 (Intel syntax)",
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"x16"
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},
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{
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// item 34
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CS_ARCH_M68K,
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CS_MODE_M68K_040,
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"M68K mode 40",
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"m68k40"
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},
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{
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//item 35
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CS_ARCH_M680X,
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(cs_mode) CS_MODE_M680X_6800,
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"M680X_M6800",
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"m6800"
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},
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{
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//item 36
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CS_ARCH_M680X,
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(cs_mode) CS_MODE_M680X_6801,
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"M680X_M6801",
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"m6801"
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},
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{
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//item 37
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CS_ARCH_M680X,
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(cs_mode) CS_MODE_M680X_6805,
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"M680X_M6805",
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"m6805"
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},
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{
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//item 38
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CS_ARCH_M680X,
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(cs_mode) CS_MODE_M680X_6808,
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"M680X_M6808",
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"m6808"
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},
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{
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//item 39
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CS_ARCH_M680X,
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(cs_mode) CS_MODE_M680X_6811,
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"M680X_M6811",
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"m6811"
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},
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{
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//item 40
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CS_ARCH_M680X,
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(cs_mode) CS_MODE_M680X_CPU12,
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"M680X_cpu12",
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"cpu12"
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},
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{
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//item 41
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CS_ARCH_M680X,
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(cs_mode) CS_MODE_M680X_6301,
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"M680X_M6808",
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"hd6301"
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},
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{
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//item 42
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CS_ARCH_M680X,
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(cs_mode) CS_MODE_M680X_6309,
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"M680X_M6808",
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"hd6309"
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},
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{
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//item 43
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CS_ARCH_M680X,
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(cs_mode) CS_MODE_M680X_HCS08,
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"M680X_M6808",
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"hcs08"
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},
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{
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//item 44
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CS_ARCH_RISCV,
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CS_MODE_RISCV32,
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"RISCV",
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"riscv32"
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},
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{
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//item 45
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CS_ARCH_RISCV,
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CS_MODE_RISCV64,
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"RISCV",
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"riscv64"
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},
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{
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//item 46
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CS_ARCH_PPC,
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CS_MODE_64 | CS_MODE_BIG_ENDIAN | CS_MODE_QPX,
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"ppc+qpx",
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"ppc64beqpx"
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},
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{
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//item 46
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CS_ARCH_PPC,
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CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_PS,
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"ppc+ps",
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"ppc32beps"
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},
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{
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CS_ARCH_TRICORE,
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CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_110,
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"TRICORE",
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"tc110"
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},
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{
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CS_ARCH_TRICORE,
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CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_120,
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"TRICORE",
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"tc120"
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},
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{
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CS_ARCH_TRICORE,
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CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_130,
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"TRICORE",
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"tc130"
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},
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{
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CS_ARCH_TRICORE,
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CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_131,
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"TRICORE",
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"tc131"
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},
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{
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CS_ARCH_TRICORE,
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CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_160,
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"TRICORE",
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"tc160"
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},
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{
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CS_ARCH_TRICORE,
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CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_161,
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"TRICORE",
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"tc161"
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},
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{
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CS_ARCH_TRICORE,
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CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_162,
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"TRICORE",
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"tc162"
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},
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{
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CS_ARCH_XTENSA,
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CS_MODE_XTENSA,
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"XTENSA",
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"xtensa"
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},
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{
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CS_ARCH_XTENSA,
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CS_MODE_XTENSA + CS_MODE_BIG_ENDIAN,
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"XTENSA (Big-Endian)",
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"xtensabe"
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},
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// dummy entry to mark the end of this array.
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// DO NOT DELETE THIS
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{
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0,
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0,
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NULL,
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NULL,
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},
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};
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// get length of platforms[]
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unsigned int platform_len(void) {
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unsigned int c;
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for (c = 0; platforms[c].cstoolname; c++);
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return c;
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}
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// get platform entry encoded n (first byte for input data of OSS fuzz)
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unsigned int get_platform_entry(uint8_t n) {
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unsigned len = platform_len();
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if (len == 0) {
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return 0;
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}
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return n % len;
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}
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// get cstoolname from encoded n (first byte for input data of OSS fuzz)
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const char *get_platform_cstoolname(uint8_t n) {
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return platforms[get_platform_entry(n)].cstoolname;
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}
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