capstone/.gitignore
z b8fcf27b22 RISCV support ISRV32/ISRV64 (#1401)
* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h

* Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction

* Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h

* Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter

* Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h

* Backport it from: 0db412ce3b

* All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly.

* Add refactored cs.c for RISCV

* Testing all I instructions in test_riscv.c

* Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture

* Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c

* fixed bug related to incorrect initialization of memory after malloc

* fix compile bug

* Fix compile errors.

* move riscv.h to include/capstone

* fix indentation issues

* fix coding style issues

* Fix indentation issues

* fix coding style

* Move variable declaration to the top of the block

* Fix coding indentation

* Move some stuff into RISCVMappingInsn.inc

* Fix code sytle

* remove cs_mode support for RISCV

* update asmwriter-inc to LLVM upstream

* update the .inc files to riscv upstream

* update riscv disassembler function for suport 16bit instructions

* update printer & tablegen inc files which have fixed arguments mismatch

* update headers and mapping source

* add riscv architecture specific test code

* fix all RISCV tons of compiler errors

* pass final tests

* add riscv tablegen patchs

* merge with upstream/next

* fix cstool missing riscv file

* fix root Makefile

* add new TableGen patchs for riscv

* fix cmakefile.txt of missing one riscv file

* fix declaration conflict

* fix incompatible declaration type

* change riscvc from arch to mode

* fix test_riscv warnning

* fix code style and add riscv part of test_basic

* add RISCV64 mode

* add suite for riscv

* crack fuzz test

* fix getfeaturebits test add riscvc

* fix test missing const qualifier warnning

* fix testcase type mismatch

* fix return value missing

* change getfeaturebits test

* add test cs files

* using a winder type contain the decode string

* fix a copy typo

* remove useless mode for riscv

* change cs file blank type

* add repo for update_riscv & fix cstool missing riscv mode

* fix typo

* add riscv for cstool useage

* add TableGen patch for riscv asmwriter

* clean ctags file

* remove black comment line

* fix fuzz related something

* fix missing RISCV string of fuzz

* update readme, etc..

* add riscv *.s.cs file

* add riscv *.s.cs file & clear ctags

* clear useless array declarations at capstone_test

* update to 5e4069f

* update readme change name more formal

* change position of riscv after bpf and modify copyright more uniform

* clear useless ctags file

* change blank with tab in riscv.h

* add riscv python bindings

* add riscv in __init__.py

* fix riscv define value for python binding

* fix test_riscv.py typo

* add missing riscvc in __init__.py of python bindings

* fix alias-insn printer bug, remove useless newline

* change inst print delimter from tab to bankspace for travis

* add riscv tablegen patch

* fix inst output more consistency

* add TableGen patch which fix inst output formal

* crack the effective address output for detail and change register print function

* fix not detail crash bug

* change item declaration position at cs_riscv

* update riscv.py

* change function name more meaningfull

* update python binding makefile

* fix register enum sequence according to riscvgenreginfo.inc

* test function name

* add enum s0/fp in riscv.h & update riscv_const.py

* add register name enum
2019-03-09 08:41:12 +08:00

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.DS_Store
# Object files
*.o
*.ko
# Gcc dependency-tracking files
*.d
# Libraries
*.lib
*.a
# Shared objects (inc. Windows DLLs)
*.dll
*.so
*.so.*
*.dylib
# Executables
*.exe
*.out
*.app
# python
bindings/python/build/
bindings/python/capstone.egg-info/
*.pyc
# java
bindings/java/capstone.jar
# ocaml
bindings/ocaml/*.cmi
bindings/ocaml/*.cmx
bindings/ocaml/*.cmxa
bindings/ocaml/*.mli
bindings/ocaml/test
bindings/ocaml/test_arm
bindings/ocaml/test_arm64
bindings/ocaml/test_basic
bindings/ocaml/test_mips
bindings/ocaml/test_x86
bindings/ocaml/test_detail
bindings/ocaml/test_ppc
bindings/ocaml/test_sparc
bindings/ocaml/test_systemz
bindings/ocaml/test_xcore
bindings/ocaml/test_m680x
# test binaries
tests/test_basic
tests/test_detail
tests/test_iter
tests/test_arm
tests/test_arm64
tests/test_mips
tests/test_x86
tests/test_ppc
tests/test_skipdata
tests/test_sparc
tests/test_systemz
tests/test_xcore
tests/*.static
tests/test_customized_mnem
tests/test_m68k
tests/test_tms320c64x
tests/test_m680x
tests/test_evm
tests/test_wasm
tests/test_mos65xx
tests/test_bpf
tests/test_riscv
# regress binaries
suite/regress/invalid_read_in_print_operand
# vim tmp file
*.swp
*~
capstone.pc
# local files
_*
# freebsd ports: generated file with "make makesum" command
packages/freebsd/ports/devel/capstone/distinfo
# VisualStudio
ProjectUpgradeLog.log
Debug/
Release/
ipch/
build*/
*.sdf
*.opensdf
*.suo
*.user
*.backup
*.VC.db
*.VC.opendb
.vscode/
# CMake build directories
build*/
# Xcode
xcode/Capstone.xcodeproj/xcuserdata
xcode/Capstone.xcodeproj/project.xcworkspace/xcuserdata
# suite/
test_arm_regression
test_arm_regression.o
fuzz_harness
test_iter_benchmark
fuzz_bindisasm
fuzz_disasm
capstone_get_setup
*.s
cstool/cstool