mirror of
https://github.com/capstone-engine/capstone.git
synced 2024-11-27 07:20:33 +00:00
b8fcf27b22
* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h
* Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction
* Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h
* Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter
* Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h
* Backport it from: 0db412ce3b
* All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly.
* Add refactored cs.c for RISCV
* Testing all I instructions in test_riscv.c
* Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture
* Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c
* fixed bug related to incorrect initialization of memory after malloc
* fix compile bug
* Fix compile errors.
* move riscv.h to include/capstone
* fix indentation issues
* fix coding style issues
* Fix indentation issues
* fix coding style
* Move variable declaration to the top of the block
* Fix coding indentation
* Move some stuff into RISCVMappingInsn.inc
* Fix code sytle
* remove cs_mode support for RISCV
* update asmwriter-inc to LLVM upstream
* update the .inc files to riscv upstream
* update riscv disassembler function for suport 16bit instructions
* update printer & tablegen inc files which have fixed arguments mismatch
* update headers and mapping source
* add riscv architecture specific test code
* fix all RISCV tons of compiler errors
* pass final tests
* add riscv tablegen patchs
* merge with upstream/next
* fix cstool missing riscv file
* fix root Makefile
* add new TableGen patchs for riscv
* fix cmakefile.txt of missing one riscv file
* fix declaration conflict
* fix incompatible declaration type
* change riscvc from arch to mode
* fix test_riscv warnning
* fix code style and add riscv part of test_basic
* add RISCV64 mode
* add suite for riscv
* crack fuzz test
* fix getfeaturebits test add riscvc
* fix test missing const qualifier warnning
* fix testcase type mismatch
* fix return value missing
* change getfeaturebits test
* add test cs files
* using a winder type contain the decode string
* fix a copy typo
* remove useless mode for riscv
* change cs file blank type
* add repo for update_riscv & fix cstool missing riscv mode
* fix typo
* add riscv for cstool useage
* add TableGen patch for riscv asmwriter
* clean ctags file
* remove black comment line
* fix fuzz related something
* fix missing RISCV string of fuzz
* update readme, etc..
* add riscv *.s.cs file
* add riscv *.s.cs file & clear ctags
* clear useless array declarations at capstone_test
* update to 5e4069f
* update readme change name more formal
* change position of riscv after bpf and modify copyright more uniform
* clear useless ctags file
* change blank with tab in riscv.h
* add riscv python bindings
* add riscv in __init__.py
* fix riscv define value for python binding
* fix test_riscv.py typo
* add missing riscvc in __init__.py of python bindings
* fix alias-insn printer bug, remove useless newline
* change inst print delimter from tab to bankspace for travis
* add riscv tablegen patch
* fix inst output more consistency
* add TableGen patch which fix inst output formal
* crack the effective address output for detail and change register print function
* fix not detail crash bug
* change item declaration position at cs_riscv
* update riscv.py
* change function name more meaningfull
* update python binding makefile
* fix register enum sequence according to riscvgenreginfo.inc
* test function name
* add enum s0/fp in riscv.h & update riscv_const.py
* add register name enum
126 lines
1.7 KiB
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126 lines
1.7 KiB
Plaintext
.DS_Store
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# Object files
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*.o
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*.ko
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# Gcc dependency-tracking files
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*.d
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# Libraries
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*.lib
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*.a
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# Shared objects (inc. Windows DLLs)
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*.dll
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*.so
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*.so.*
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*.dylib
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# Executables
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*.exe
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*.out
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*.app
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# python
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bindings/python/build/
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bindings/python/capstone.egg-info/
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*.pyc
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# java
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bindings/java/capstone.jar
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# ocaml
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bindings/ocaml/*.cmi
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bindings/ocaml/*.cmx
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bindings/ocaml/*.cmxa
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bindings/ocaml/*.mli
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bindings/ocaml/test
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bindings/ocaml/test_arm
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bindings/ocaml/test_arm64
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bindings/ocaml/test_basic
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bindings/ocaml/test_mips
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bindings/ocaml/test_x86
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bindings/ocaml/test_detail
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bindings/ocaml/test_ppc
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bindings/ocaml/test_sparc
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bindings/ocaml/test_systemz
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bindings/ocaml/test_xcore
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bindings/ocaml/test_m680x
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# test binaries
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tests/test_basic
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tests/test_detail
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tests/test_iter
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tests/test_arm
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tests/test_arm64
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tests/test_mips
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tests/test_x86
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tests/test_ppc
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tests/test_skipdata
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tests/test_sparc
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tests/test_systemz
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tests/test_xcore
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tests/*.static
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tests/test_customized_mnem
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tests/test_m68k
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tests/test_tms320c64x
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tests/test_m680x
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tests/test_evm
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tests/test_wasm
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tests/test_mos65xx
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tests/test_bpf
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tests/test_riscv
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# regress binaries
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suite/regress/invalid_read_in_print_operand
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# vim tmp file
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*.swp
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*~
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capstone.pc
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# local files
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_*
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# freebsd ports: generated file with "make makesum" command
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packages/freebsd/ports/devel/capstone/distinfo
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# VisualStudio
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ProjectUpgradeLog.log
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Debug/
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Release/
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ipch/
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build*/
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*.sdf
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*.opensdf
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*.suo
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*.user
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*.backup
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*.VC.db
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*.VC.opendb
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.vscode/
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# CMake build directories
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build*/
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# Xcode
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xcode/Capstone.xcodeproj/xcuserdata
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xcode/Capstone.xcodeproj/project.xcworkspace/xcuserdata
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# suite/
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test_arm_regression
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test_arm_regression.o
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fuzz_harness
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test_iter_benchmark
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fuzz_bindisasm
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fuzz_disasm
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capstone_get_setup
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*.s
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cstool/cstool
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