mirror of
https://github.com/capstone-engine/capstone.git
synced 2024-11-27 07:20:33 +00:00
b8fcf27b22
* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h
* Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction
* Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h
* Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter
* Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h
* Backport it from: 0db412ce3b
* All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly.
* Add refactored cs.c for RISCV
* Testing all I instructions in test_riscv.c
* Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture
* Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c
* fixed bug related to incorrect initialization of memory after malloc
* fix compile bug
* Fix compile errors.
* move riscv.h to include/capstone
* fix indentation issues
* fix coding style issues
* Fix indentation issues
* fix coding style
* Move variable declaration to the top of the block
* Fix coding indentation
* Move some stuff into RISCVMappingInsn.inc
* Fix code sytle
* remove cs_mode support for RISCV
* update asmwriter-inc to LLVM upstream
* update the .inc files to riscv upstream
* update riscv disassembler function for suport 16bit instructions
* update printer & tablegen inc files which have fixed arguments mismatch
* update headers and mapping source
* add riscv architecture specific test code
* fix all RISCV tons of compiler errors
* pass final tests
* add riscv tablegen patchs
* merge with upstream/next
* fix cstool missing riscv file
* fix root Makefile
* add new TableGen patchs for riscv
* fix cmakefile.txt of missing one riscv file
* fix declaration conflict
* fix incompatible declaration type
* change riscvc from arch to mode
* fix test_riscv warnning
* fix code style and add riscv part of test_basic
* add RISCV64 mode
* add suite for riscv
* crack fuzz test
* fix getfeaturebits test add riscvc
* fix test missing const qualifier warnning
* fix testcase type mismatch
* fix return value missing
* change getfeaturebits test
* add test cs files
* using a winder type contain the decode string
* fix a copy typo
* remove useless mode for riscv
* change cs file blank type
* add repo for update_riscv & fix cstool missing riscv mode
* fix typo
* add riscv for cstool useage
* add TableGen patch for riscv asmwriter
* clean ctags file
* remove black comment line
* fix fuzz related something
* fix missing RISCV string of fuzz
* update readme, etc..
* add riscv *.s.cs file
* add riscv *.s.cs file & clear ctags
* clear useless array declarations at capstone_test
* update to 5e4069f
* update readme change name more formal
* change position of riscv after bpf and modify copyright more uniform
* clear useless ctags file
* change blank with tab in riscv.h
* add riscv python bindings
* add riscv in __init__.py
* fix riscv define value for python binding
* fix test_riscv.py typo
* add missing riscvc in __init__.py of python bindings
* fix alias-insn printer bug, remove useless newline
* change inst print delimter from tab to bankspace for travis
* add riscv tablegen patch
* fix inst output more consistency
* add TableGen patch which fix inst output formal
* crack the effective address output for detail and change register print function
* fix not detail crash bug
* change item declaration position at cs_riscv
* update riscv.py
* change function name more meaningfull
* update python binding makefile
* fix register enum sequence according to riscvgenreginfo.inc
* test function name
* add enum s0/fp in riscv.h & update riscv_const.py
* add register name enum
86 lines
2.9 KiB
Plaintext
86 lines
2.9 KiB
Plaintext
This file credits all the contributors of the Capstone engine project.
|
|
|
|
Key developers
|
|
==============
|
|
1. Nguyen Anh Quynh <aquynh -at- gmail.com>
|
|
- Core engine
|
|
- Bindings: Python, Ruby, OCaml, Java, C#
|
|
|
|
2. Tan Sheng Di <shengdi -at- coseinc.com>
|
|
- Bindings: Ruby
|
|
|
|
3. Ben Nagy <ben -at- coseinc.com>
|
|
- Bindings: Ruby, Go
|
|
|
|
4. Dang Hoang Vu <dang.hvu -at- gmail.com>
|
|
- Bindings: Java
|
|
|
|
|
|
Beta testers (in random order)
|
|
==============================
|
|
Pancake
|
|
Van Hauser
|
|
FX of Phenoelit
|
|
The Grugq, The Grugq <-- our hero for submitting the first ever patch!
|
|
Isaac Dawson, Veracode Inc
|
|
Patroklos Argyroudis, Census Inc. (http://census-labs.com)
|
|
Attila Suszter
|
|
Le Dinh Long
|
|
Nicolas Ruff
|
|
Gunther
|
|
Alex Ionescu, Winsider Seminars & Solutions Inc.
|
|
Snare
|
|
Daniel Godas-Lopez
|
|
Joshua J. Drake
|
|
Edgar Barbosa
|
|
Ralf-Philipp Weinmann
|
|
Hugo Fortier
|
|
Joxean Koret
|
|
Bruce Dang
|
|
Andrew Dunham
|
|
|
|
|
|
Contributors (in no particular order)
|
|
=====================================
|
|
(Please let us know if you want to have your name here)
|
|
|
|
Ole André Vadla Ravnås (author of the 100th Pull-Request in our Github repo, thanks!)
|
|
Axel "0vercl0k" Souchet (@0vercl0k) & Alex Ionescu: port to MSVC.
|
|
Daniel Pistelli: Cmake support.
|
|
Peter Hlavaty: integrate Capstone for Windows kernel drivers.
|
|
Guillaume Jeanne: Ocaml binding.
|
|
Martin Tofall, Obsidium Software: Optimize X86 performance & size + x86 encoding features.
|
|
David Martínez Moreno & Hilko Bengen: Debian package.
|
|
Félix Cloutier: Xcode project.
|
|
Benoit Lecocq: OpenBSD package.
|
|
Christophe Avoinne (Hlide): Improve memory management for better performance.
|
|
Michael Cohen & Nguyen Tan Cong: Python module installer.
|
|
Adel Gadllah, Francisco Alonso & Stefan Cornelius: RPM package.
|
|
Felix Gröbert (Google): fuzz testing harness.
|
|
Xipiter LLC: Capstone logo redesigned.
|
|
Satoshi Tanda: Support Windows kernel driver.
|
|
Tang Yuhang: cstool.
|
|
Andrew Dutcher: better Python setup.
|
|
Ruben Boonen: PowerShell binding.
|
|
David Zimmer: VB6 binding.
|
|
Philippe Antoine: Integration with oss-fuzz and various fixes.
|
|
Bui Dinh Cuong: Explicit registers accessed for Arm64.
|
|
Vincent Bénony: Explicit registers accessed for X86.
|
|
Adel Gadllah, Francisco Alonso & Stefan Cornelius: RPM package.
|
|
Felix Gröbert (Google): fuzz testing harness.
|
|
Daniel Collin & Nicolas Planel: M68K architecture.
|
|
Pranith Kumar: Explicit registers accessed for Arm64.
|
|
Xipiter LLC: Capstone logo redesigned.
|
|
Satoshi Tanda: Support Windows kernel driver.
|
|
Koutheir Attouchi: Support for Windows CE.
|
|
Fotis Loukos: TMS320C64x architecture.
|
|
Wolfgang Schwotzer: M680X architecture.
|
|
Philippe Antoine: Integration with oss-fuzz and various fixes.
|
|
Stephen Eckels (stevemk14ebr): x86 encoding features
|
|
Tong Yu(Spike) & Kai Jern, Lau (xwings): WASM architecture.
|
|
Sebastian Macke: MOS65XX architecture
|
|
Ilya Leoshkevich: SystemZ architecture improvements.
|
|
Do Minh Tuan: Regression testing tool (cstest)
|
|
david942j: BPF (both classic and extended) architecture.
|
|
fanfuqiang & citypw & porto703 : RISCV architecture.
|