billow a076fdeb0a refactor: Refactor TriCore instruction decoding and register definition. ...

- Update TriCore processor register definitions with auto-generated file `TriCoreGenCSRegEnum.inc`
- Add several new TriCore processor instructions with auto-generated file `TriCoreGenCSInsnEnum.inc`
- Update TriCore_OP_GROUP enumeration with auto-generated file `TriCoreGenCSOpGroup.inc`
- Rename and restructure TriCore processor register classes
- Remove unused register class definitions and related code

2023-04-14 00:35:32 +08:00

..

AArch64

Merge pull request #1974 from thomasdangl/next

2023-03-19 17:35:46 +08:00

ARM

correct register accesses for ARM's sxtb/uxtb and similar instructions

2023-03-07 18:59:06 +01:00

BPF

Merge pull request #1886 from terorie/ebpf-callx

2022-06-09 21:37:40 +08:00

EVM

Dont format sstreams when there's nothing to format

2021-12-10 10:59:16 +01:00

M68K

m68k: Add support for the FNOP instruction (fixes #1916)

2022-10-02 08:07:33 +02:00

M680X

Dont format sstreams when there's nothing to format

2021-12-10 10:59:16 +01:00

Mips

Constify backends (#1549)

2019-12-23 20:30:57 +08:00

MOS65XX

Dont format sstreams when there's nothing to format

2021-12-10 10:59:16 +01:00

PowerPC

PPC: fix out of bound memory access

2022-09-07 17:27:54 +02:00

RISCV

Fix potential array out of bounds

2022-11-26 15:59:18 +01:00

SH

Remove unused variable

2023-04-06 03:57:28 -05:00

Sparc

Constify backends (#1549)

2019-12-23 20:30:57 +08:00

SystemZ

Constify backends (#1549)

2019-12-23 20:30:57 +08:00

TMS320C64x

Fix potential array out of bounds

2022-11-26 15:59:18 +01:00

TriCore

refactor: Refactor TriCore instruction decoding and register definition.

2023-04-14 00:35:32 +08:00

WASM

Constify backends (#1549)

2019-12-23 20:30:57 +08:00

X86

One semicolon is enough in C (#1892)

2022-07-08 07:06:38 +08:00

XCore

Constify backends (#1549)

2019-12-23 20:30:57 +08:00