mirror of
https://github.com/capstone-engine/capstone.git
synced 2024-11-24 14:09:56 +00:00
b8fcf27b22
* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h
* Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction
* Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h
* Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter
* Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h
* Backport it from: 0db412ce3b
* All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly.
* Add refactored cs.c for RISCV
* Testing all I instructions in test_riscv.c
* Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture
* Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c
* fixed bug related to incorrect initialization of memory after malloc
* fix compile bug
* Fix compile errors.
* move riscv.h to include/capstone
* fix indentation issues
* fix coding style issues
* Fix indentation issues
* fix coding style
* Move variable declaration to the top of the block
* Fix coding indentation
* Move some stuff into RISCVMappingInsn.inc
* Fix code sytle
* remove cs_mode support for RISCV
* update asmwriter-inc to LLVM upstream
* update the .inc files to riscv upstream
* update riscv disassembler function for suport 16bit instructions
* update printer & tablegen inc files which have fixed arguments mismatch
* update headers and mapping source
* add riscv architecture specific test code
* fix all RISCV tons of compiler errors
* pass final tests
* add riscv tablegen patchs
* merge with upstream/next
* fix cstool missing riscv file
* fix root Makefile
* add new TableGen patchs for riscv
* fix cmakefile.txt of missing one riscv file
* fix declaration conflict
* fix incompatible declaration type
* change riscvc from arch to mode
* fix test_riscv warnning
* fix code style and add riscv part of test_basic
* add RISCV64 mode
* add suite for riscv
* crack fuzz test
* fix getfeaturebits test add riscvc
* fix test missing const qualifier warnning
* fix testcase type mismatch
* fix return value missing
* change getfeaturebits test
* add test cs files
* using a winder type contain the decode string
* fix a copy typo
* remove useless mode for riscv
* change cs file blank type
* add repo for update_riscv & fix cstool missing riscv mode
* fix typo
* add riscv for cstool useage
* add TableGen patch for riscv asmwriter
* clean ctags file
* remove black comment line
* fix fuzz related something
* fix missing RISCV string of fuzz
* update readme, etc..
* add riscv *.s.cs file
* add riscv *.s.cs file & clear ctags
* clear useless array declarations at capstone_test
* update to 5e4069f
* update readme change name more formal
* change position of riscv after bpf and modify copyright more uniform
* clear useless ctags file
* change blank with tab in riscv.h
* add riscv python bindings
* add riscv in __init__.py
* fix riscv define value for python binding
* fix test_riscv.py typo
* add missing riscvc in __init__.py of python bindings
* fix alias-insn printer bug, remove useless newline
* change inst print delimter from tab to bankspace for travis
* add riscv tablegen patch
* fix inst output more consistency
* add TableGen patch which fix inst output formal
* crack the effective address output for detail and change register print function
* fix not detail crash bug
* change item declaration position at cs_riscv
* update riscv.py
* change function name more meaningfull
* update python binding makefile
* fix register enum sequence according to riscvgenreginfo.inc
* test function name
* add enum s0/fp in riscv.h & update riscv_const.py
* add register name enum
271 lines
7.2 KiB
Python
Executable File
271 lines
7.2 KiB
Python
Executable File
#!/usr/bin/python
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from capstone import *
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from capstone.arm import *
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from capstone.arm64 import *
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from capstone.mips import *
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from capstone.ppc import *
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from capstone.sparc import *
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from capstone.systemz import *
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from capstone.x86 import *
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from capstone.xcore import *
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from capstone.riscv import *
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import sys
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class GroupTest:
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def __init__(self, name, arch, mode, data):
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self.name = name
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self.arch = arch
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self.mode = mode
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self.data = data
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def run(self):
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print('Testing %s' %self.name)
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cap = Cs(self.arch, self.mode)
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for group_id in xrange(0,255):
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name = self.data.get(group_id)
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res = cap.group_name(group_id)
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if res != name:
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print("ERROR: id = %u expected '%s', but got '%s'" %(group_id, name, res))
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print("")
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arm_dict = {
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ARM_GRP_JUMP: "jump",
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ARM_GRP_CALL: "call",
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ARM_GRP_INT: "int",
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ARM_GRP_PRIVILEGE: "privilege",
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ARM_GRP_CRYPTO: "crypto",
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ARM_GRP_DATABARRIER: "databarrier",
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ARM_GRP_DIVIDE: "divide",
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ARM_GRP_FPARMV8: "fparmv8",
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ARM_GRP_MULTPRO: "multpro",
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ARM_GRP_NEON: "neon",
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ARM_GRP_T2EXTRACTPACK: "T2EXTRACTPACK",
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ARM_GRP_THUMB2DSP: "THUMB2DSP",
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ARM_GRP_TRUSTZONE: "TRUSTZONE",
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ARM_GRP_V4T: "v4t",
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ARM_GRP_V5T: "v5t",
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ARM_GRP_V5TE: "v5te",
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ARM_GRP_V6: "v6",
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ARM_GRP_V6T2: "v6t2",
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ARM_GRP_V7: "v7",
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ARM_GRP_V8: "v8",
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ARM_GRP_VFP2: "vfp2",
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ARM_GRP_VFP3: "vfp3",
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ARM_GRP_VFP4: "vfp4",
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ARM_GRP_ARM: "arm",
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ARM_GRP_MCLASS: "mclass",
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ARM_GRP_NOTMCLASS: "notmclass",
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ARM_GRP_THUMB: "thumb",
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ARM_GRP_THUMB1ONLY: "thumb1only",
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ARM_GRP_THUMB2: "thumb2",
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ARM_GRP_PREV8: "prev8",
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ARM_GRP_FPVMLX: "fpvmlx",
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ARM_GRP_MULOPS: "mulops",
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ARM_GRP_CRC: "crc",
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ARM_GRP_DPVFP: "dpvfp",
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ARM_GRP_V6M: "v6m",
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ARM_GRP_VIRTUALIZATION: "virtualization",
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}
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arm64_dict = {
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ARM64_GRP_JUMP: "jump",
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ARM64_GRP_CALL: "call",
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ARM64_GRP_RET: "return",
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ARM64_GRP_INT: "int",
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ARM64_GRP_PRIVILEGE: "privilege",
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ARM64_GRP_CRYPTO: "crypto",
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ARM64_GRP_FPARMV8: "fparmv8",
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ARM64_GRP_NEON: "neon",
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ARM64_GRP_CRC: "crc"
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}
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mips_dict = {
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MIPS_GRP_JUMP: "jump",
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MIPS_GRP_CALL: "call",
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MIPS_GRP_RET: "ret",
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MIPS_GRP_INT: "int",
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MIPS_GRP_IRET: "iret",
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MIPS_GRP_PRIVILEGE: "privilege",
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MIPS_GRP_BITCOUNT: "bitcount",
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MIPS_GRP_DSP: "dsp",
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MIPS_GRP_DSPR2: "dspr2",
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MIPS_GRP_FPIDX: "fpidx",
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MIPS_GRP_MSA: "msa",
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MIPS_GRP_MIPS32R2: "mips32r2",
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MIPS_GRP_MIPS64: "mips64",
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MIPS_GRP_MIPS64R2: "mips64r2",
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MIPS_GRP_SEINREG: "seinreg",
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MIPS_GRP_STDENC: "stdenc",
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MIPS_GRP_SWAP: "swap",
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MIPS_GRP_MICROMIPS: "micromips",
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MIPS_GRP_MIPS16MODE: "mips16mode",
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MIPS_GRP_FP64BIT: "fp64bit",
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MIPS_GRP_NONANSFPMATH: "nonansfpmath",
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MIPS_GRP_NOTFP64BIT: "notfp64bit",
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MIPS_GRP_NOTINMICROMIPS: "notinmicromips",
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MIPS_GRP_NOTNACL: "notnacl",
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MIPS_GRP_NOTMIPS32R6: "notmips32r6",
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MIPS_GRP_NOTMIPS64R6: "notmips64r6",
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MIPS_GRP_CNMIPS: "cnmips",
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MIPS_GRP_MIPS32: "mips32",
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MIPS_GRP_MIPS32R6: "mips32r6",
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MIPS_GRP_MIPS64R6: "mips64r6",
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MIPS_GRP_MIPS2: "mips2",
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MIPS_GRP_MIPS3: "mips3",
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MIPS_GRP_MIPS3_32: "mips3_32",
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MIPS_GRP_MIPS3_32R2: "mips3_32r2",
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MIPS_GRP_MIPS4_32: "mips4_32",
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MIPS_GRP_MIPS4_32R2: "mips4_32r2",
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MIPS_GRP_MIPS5_32R2: "mips5_32r2",
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MIPS_GRP_GP32BIT: "gp32bit",
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MIPS_GRP_GP64BIT: "gp64bit",
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}
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ppc_dict = {
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PPC_GRP_JUMP: "jump",
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PPC_GRP_ALTIVEC: "altivec",
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PPC_GRP_MODE32: "mode32",
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PPC_GRP_MODE64: "mode64",
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PPC_GRP_BOOKE: "booke",
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PPC_GRP_NOTBOOKE: "notbooke",
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PPC_GRP_SPE: "spe",
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PPC_GRP_VSX: "vsx",
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PPC_GRP_E500: "e500",
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PPC_GRP_PPC4XX: "ppc4xx",
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PPC_GRP_PPC6XX: "ppc6xx",
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PPC_GRP_ICBT: "icbt",
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PPC_GRP_P8ALTIVEC: "p8altivec",
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PPC_GRP_P8VECTOR: "p8vector",
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PPC_GRP_QPX: "qpx",
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}
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sparc_dict = {
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SPARC_GRP_JUMP: "jump",
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SPARC_GRP_HARDQUAD: "hardquad",
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SPARC_GRP_V9: "v9",
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SPARC_GRP_VIS: "vis",
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SPARC_GRP_VIS2: "vis2",
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SPARC_GRP_VIS3: "vis3",
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SPARC_GRP_32BIT: "32bit",
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SPARC_GRP_64BIT: "64bit",
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}
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sysz_dict = {
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SYSZ_GRP_JUMP: "jump",
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SYSZ_GRP_DISTINCTOPS: "distinctops",
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SYSZ_GRP_FPEXTENSION: "fpextension",
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SYSZ_GRP_HIGHWORD: "highword",
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SYSZ_GRP_INTERLOCKEDACCESS1: "interlockedaccess1",
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SYSZ_GRP_LOADSTOREONCOND: "loadstoreoncond",
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}
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x86_dict = {
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X86_GRP_JUMP: "jump",
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X86_GRP_CALL: "call",
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X86_GRP_RET: "ret",
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X86_GRP_INT: "int",
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X86_GRP_IRET: "iret",
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X86_GRP_PRIVILEGE: "privilege",
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X86_GRP_VM: "vm",
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X86_GRP_3DNOW: "3dnow",
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X86_GRP_AES: "aes",
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X86_GRP_ADX: "adx",
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X86_GRP_AVX: "avx",
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X86_GRP_AVX2: "avx2",
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X86_GRP_AVX512: "avx512",
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X86_GRP_BMI: "bmi",
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X86_GRP_BMI2: "bmi2",
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X86_GRP_CMOV: "cmov",
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X86_GRP_F16C: "fc16",
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X86_GRP_FMA: "fma",
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X86_GRP_FMA4: "fma4",
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X86_GRP_FSGSBASE: "fsgsbase",
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X86_GRP_HLE: "hle",
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X86_GRP_MMX: "mmx",
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X86_GRP_MODE32: "mode32",
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X86_GRP_MODE64: "mode64",
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X86_GRP_RTM: "rtm",
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X86_GRP_SHA: "sha",
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X86_GRP_SSE1: "sse1",
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X86_GRP_SSE2: "sse2",
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X86_GRP_SSE3: "sse3",
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X86_GRP_SSE41: "sse41",
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X86_GRP_SSE42: "sse42",
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X86_GRP_SSE4A: "sse4a",
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X86_GRP_SSSE3: "ssse3",
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X86_GRP_PCLMUL: "pclmul",
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X86_GRP_XOP: "xop",
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X86_GRP_CDI: "cdi",
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X86_GRP_ERI: "eri",
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X86_GRP_TBM: "tbm",
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X86_GRP_16BITMODE: "16bitmode",
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X86_GRP_NOT64BITMODE: "not64bitmode",
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X86_GRP_SGX: "sgx",
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X86_GRP_DQI: "dqi",
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X86_GRP_BWI: "bwi",
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X86_GRP_PFI: "pfi",
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X86_GRP_VLX: "vlx",
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X86_GRP_SMAP: "smap",
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X86_GRP_NOVLX: "novlx",
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}
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xcore_dict = {
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XCORE_GRP_JUMP: "jump",
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}
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riscv32_dict = {
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RISCV_GRP_JUMP : "jump",
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RISCV_GRP_ISRV32 : "isrv32",
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RISCV_GRP_HASSTDEXTA : "hasstdexta",
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RISCV_GRP_HASSTDEXTC : "hasstdextc",
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RISCV_GRP_HASSTDEXTD : "hasstdextd",
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RISCV_GRP_HASSTDEXTF : "hasstdextf",
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RISCV_GRP_HASSTDEXTM : "hasstdextm",
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}
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riscv64_dict = {
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RISCV_GRP_JUMP : "jump",
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RISCV_GRP_ISRV64 : "isrv64",
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RISCV_GRP_HASSTDEXTA : "hasstdexta",
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RISCV_GRP_HASSTDEXTC : "hasstdextc",
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RISCV_GRP_HASSTDEXTD : "hasstdextd",
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RISCV_GRP_HASSTDEXTF : "hasstdextf",
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RISCV_GRP_HASSTDEXTM : "hasstdextm",
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}
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tests = [
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GroupTest('arm', CS_ARCH_ARM, CS_MODE_THUMB, arm_dict),
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GroupTest('arm64', CS_ARCH_ARM64, CS_MODE_ARM, arm64_dict),
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GroupTest('mips', CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_BIG_ENDIAN, mips_dict),
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GroupTest('ppc', CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, ppc_dict),
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GroupTest('sparc', CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, sparc_dict),
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GroupTest('sysz', CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN, sysz_dict),
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GroupTest('x86', CS_ARCH_X86, CS_MODE_32, x86_dict),
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GroupTest('xcore', CS_ARCH_XCORE, CS_MODE_BIG_ENDIAN, xcore_dict),
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GroupTest('m68k', CS_ARCH_M68K, CS_MODE_BIG_ENDIAN, xcore_dict),
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GroupTest('riscv32', CS_ARCH_RISCV, CS_MODE_RISCV32, riscv32_dict),
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GroupTest('riscv64', CS_ARCH_RISCV, CS_MODE_RISCV64, riscv64_dict),
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]
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if __name__ == '__main__':
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args = sys.argv[1:]
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all = len(args) == 0 or 'all' in args
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for t in tests:
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if all or t.name in args:
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t.run()
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else:
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print('Skipping %s' %t.name)
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