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capstone/arch/XCore/XCoreGenInstrInfo.inc
Nguyen Anh Quynh c80d840ffc add XCore architecture
2014-05-26 23:02:48 +08:00

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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|*Target Instruction Enum Values *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM
enum {
XCore_PHI = 0,
XCore_INLINEASM = 1,
XCore_CFI_INSTRUCTION = 2,
XCore_EH_LABEL = 3,
XCore_GC_LABEL = 4,
XCore_KILL = 5,
XCore_EXTRACT_SUBREG = 6,
XCore_INSERT_SUBREG = 7,
XCore_IMPLICIT_DEF = 8,
XCore_SUBREG_TO_REG = 9,
XCore_COPY_TO_REGCLASS = 10,
XCore_DBG_VALUE = 11,
XCore_REG_SEQUENCE = 12,
XCore_COPY = 13,
XCore_BUNDLE = 14,
XCore_LIFETIME_START = 15,
XCore_LIFETIME_END = 16,
XCore_STACKMAP = 17,
XCore_PATCHPOINT = 18,
XCore_ADD_2rus = 19,
XCore_ADD_3r = 20,
XCore_ADJCALLSTACKDOWN = 21,
XCore_ADJCALLSTACKUP = 22,
XCore_ANDNOT_2r = 23,
XCore_AND_3r = 24,
XCore_ASHR_l2rus = 25,
XCore_ASHR_l3r = 26,
XCore_BAU_1r = 27,
XCore_BITREV_l2r = 28,
XCore_BLACP_lu10 = 29,
XCore_BLACP_u10 = 30,
XCore_BLAT_lu6 = 31,
XCore_BLAT_u6 = 32,
XCore_BLA_1r = 33,
XCore_BLRB_lu10 = 34,
XCore_BLRB_u10 = 35,
XCore_BLRF_lu10 = 36,
XCore_BLRF_u10 = 37,
XCore_BRBF_lru6 = 38,
XCore_BRBF_ru6 = 39,
XCore_BRBT_lru6 = 40,
XCore_BRBT_ru6 = 41,
XCore_BRBU_lu6 = 42,
XCore_BRBU_u6 = 43,
XCore_BRFF_lru6 = 44,
XCore_BRFF_ru6 = 45,
XCore_BRFT_lru6 = 46,
XCore_BRFT_ru6 = 47,
XCore_BRFU_lu6 = 48,
XCore_BRFU_u6 = 49,
XCore_BRU_1r = 50,
XCore_BR_JT = 51,
XCore_BR_JT32 = 52,
XCore_BYTEREV_l2r = 53,
XCore_CHKCT_2r = 54,
XCore_CHKCT_rus = 55,
XCore_CLRE_0R = 56,
XCore_CLRPT_1R = 57,
XCore_CLRSR_branch_lu6 = 58,
XCore_CLRSR_branch_u6 = 59,
XCore_CLRSR_lu6 = 60,
XCore_CLRSR_u6 = 61,
XCore_CLZ_l2r = 62,
XCore_CRC8_l4r = 63,
XCore_CRC_l3r = 64,
XCore_DCALL_0R = 65,
XCore_DENTSP_0R = 66,
XCore_DGETREG_1r = 67,
XCore_DIVS_l3r = 68,
XCore_DIVU_l3r = 69,
XCore_DRESTSP_0R = 70,
XCore_DRET_0R = 71,
XCore_ECALLF_1r = 72,
XCore_ECALLT_1r = 73,
XCore_EDU_1r = 74,
XCore_EEF_2r = 75,
XCore_EET_2r = 76,
XCore_EEU_1r = 77,
XCore_EH_RETURN = 78,
XCore_ENDIN_2r = 79,
XCore_ENTSP_lu6 = 80,
XCore_ENTSP_u6 = 81,
XCore_EQ_2rus = 82,
XCore_EQ_3r = 83,
XCore_EXTDP_lu6 = 84,
XCore_EXTDP_u6 = 85,
XCore_EXTSP_lu6 = 86,
XCore_EXTSP_u6 = 87,
XCore_FRAME_TO_ARGS_OFFSET = 88,
XCore_FREER_1r = 89,
XCore_FREET_0R = 90,
XCore_GETD_l2r = 91,
XCore_GETED_0R = 92,
XCore_GETET_0R = 93,
XCore_GETID_0R = 94,
XCore_GETKEP_0R = 95,
XCore_GETKSP_0R = 96,
XCore_GETN_l2r = 97,
XCore_GETPS_l2r = 98,
XCore_GETR_rus = 99,
XCore_GETSR_lu6 = 100,
XCore_GETSR_u6 = 101,
XCore_GETST_2r = 102,
XCore_GETTS_2r = 103,
XCore_INCT_2r = 104,
XCore_INITCP_2r = 105,
XCore_INITDP_2r = 106,
XCore_INITLR_l2r = 107,
XCore_INITPC_2r = 108,
XCore_INITSP_2r = 109,
XCore_INPW_l2rus = 110,
XCore_INSHR_2r = 111,
XCore_INT_2r = 112,
XCore_IN_2r = 113,
XCore_Int_MemBarrier = 114,
XCore_KCALL_1r = 115,
XCore_KCALL_lu6 = 116,
XCore_KCALL_u6 = 117,
XCore_KENTSP_lu6 = 118,
XCore_KENTSP_u6 = 119,
XCore_KRESTSP_lu6 = 120,
XCore_KRESTSP_u6 = 121,
XCore_KRET_0R = 122,
XCore_LADD_l5r = 123,
XCore_LD16S_3r = 124,
XCore_LD8U_3r = 125,
XCore_LDA16B_l3r = 126,
XCore_LDA16F_l3r = 127,
XCore_LDAPB_lu10 = 128,
XCore_LDAPB_u10 = 129,
XCore_LDAPF_lu10 = 130,
XCore_LDAPF_lu10_ba = 131,
XCore_LDAPF_u10 = 132,
XCore_LDAWB_l2rus = 133,
XCore_LDAWB_l3r = 134,
XCore_LDAWCP_lu6 = 135,
XCore_LDAWCP_u6 = 136,
XCore_LDAWDP_lru6 = 137,
XCore_LDAWDP_ru6 = 138,
XCore_LDAWFI = 139,
XCore_LDAWF_l2rus = 140,
XCore_LDAWF_l3r = 141,
XCore_LDAWSP_lru6 = 142,
XCore_LDAWSP_ru6 = 143,
XCore_LDC_lru6 = 144,
XCore_LDC_ru6 = 145,
XCore_LDET_0R = 146,
XCore_LDIVU_l5r = 147,
XCore_LDSED_0R = 148,
XCore_LDSPC_0R = 149,
XCore_LDSSR_0R = 150,
XCore_LDWCP_lru6 = 151,
XCore_LDWCP_lu10 = 152,
XCore_LDWCP_ru6 = 153,
XCore_LDWCP_u10 = 154,
XCore_LDWDP_lru6 = 155,
XCore_LDWDP_ru6 = 156,
XCore_LDWFI = 157,
XCore_LDWSP_lru6 = 158,
XCore_LDWSP_ru6 = 159,
XCore_LDW_2rus = 160,
XCore_LDW_3r = 161,
XCore_LMUL_l6r = 162,
XCore_LSS_3r = 163,
XCore_LSUB_l5r = 164,
XCore_LSU_3r = 165,
XCore_MACCS_l4r = 166,
XCore_MACCU_l4r = 167,
XCore_MJOIN_1r = 168,
XCore_MKMSK_2r = 169,
XCore_MKMSK_rus = 170,
XCore_MSYNC_1r = 171,
XCore_MUL_l3r = 172,
XCore_NEG = 173,
XCore_NOT = 174,
XCore_OR_3r = 175,
XCore_OUTCT_2r = 176,
XCore_OUTCT_rus = 177,
XCore_OUTPW_l2rus = 178,
XCore_OUTSHR_2r = 179,
XCore_OUTT_2r = 180,
XCore_OUT_2r = 181,
XCore_PEEK_2r = 182,
XCore_REMS_l3r = 183,
XCore_REMU_l3r = 184,
XCore_RETSP_lu6 = 185,
XCore_RETSP_u6 = 186,
XCore_SELECT_CC = 187,
XCore_SETCLK_l2r = 188,
XCore_SETCP_1r = 189,
XCore_SETC_l2r = 190,
XCore_SETC_lru6 = 191,
XCore_SETC_ru6 = 192,
XCore_SETDP_1r = 193,
XCore_SETD_2r = 194,
XCore_SETEV_1r = 195,
XCore_SETKEP_0R = 196,
XCore_SETN_l2r = 197,
XCore_SETPSC_2r = 198,
XCore_SETPS_l2r = 199,
XCore_SETPT_2r = 200,
XCore_SETRDY_l2r = 201,
XCore_SETSP_1r = 202,
XCore_SETSR_branch_lu6 = 203,
XCore_SETSR_branch_u6 = 204,
XCore_SETSR_lu6 = 205,
XCore_SETSR_u6 = 206,
XCore_SETTW_l2r = 207,
XCore_SETV_1r = 208,
XCore_SEXT_2r = 209,
XCore_SEXT_rus = 210,
XCore_SHL_2rus = 211,
XCore_SHL_3r = 212,
XCore_SHR_2rus = 213,
XCore_SHR_3r = 214,
XCore_SSYNC_0r = 215,
XCore_ST16_l3r = 216,
XCore_ST8_l3r = 217,
XCore_STET_0R = 218,
XCore_STSED_0R = 219,
XCore_STSPC_0R = 220,
XCore_STSSR_0R = 221,
XCore_STWDP_lru6 = 222,
XCore_STWDP_ru6 = 223,
XCore_STWFI = 224,
XCore_STWSP_lru6 = 225,
XCore_STWSP_ru6 = 226,
XCore_STW_2rus = 227,
XCore_STW_l3r = 228,
XCore_SUB_2rus = 229,
XCore_SUB_3r = 230,
XCore_SYNCR_1r = 231,
XCore_TESTCT_2r = 232,
XCore_TESTLCL_l2r = 233,
XCore_TESTWCT_2r = 234,
XCore_TSETMR_2r = 235,
XCore_TSETR_3r = 236,
XCore_TSTART_1R = 237,
XCore_WAITEF_1R = 238,
XCore_WAITET_1R = 239,
XCore_WAITEU_0R = 240,
XCore_XOR_l3r = 241,
XCore_ZEXT_2r = 242,
XCore_ZEXT_rus = 243,
XCore_INSTRUCTION_LIST_END = 244
};
#endif // GET_INSTRINFO_ENUM
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