capstone/suite
Richard Henderson aaffb38c44 Constify backends (#1549)
* Constify registerinfo.py output

Remove two conditionals separating identical bits of code.
Add "const" markup to MCRegisterDesc and MCRegisterClass.

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify instrinfo-arch.py output

In this case, do not actively strip const.

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the AArch64 backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the EVM backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify M680X backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify M68K backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the Mips backend

The Mips backend has not been regenerated from LLVM recently,
and there are more fixups required than I'd like.  Just apply
the fixes to the tables by hand for now.

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the Sparc backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the TMS320C64x backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the X86 backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the XCore backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify systemregister.py output

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the ARM backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the PowerPC backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the MOS65XX backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the SystemZ backend

The mapping of system register to indexes is easy to
generate read-only.  Since we know the indexes are
between 0 and 31, use uint8_t instead of unsigned.

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the WASM backend

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify cs.c

Signed-off-by: Richard Henderson <rth@twiddle.net>

* Constify the BPF backend

Signed-off-by: Richard Henderson <rth@twiddle.net>
2019-12-23 20:30:57 +08:00
..
arm fixed issue #726 (snprintf undefined in test_arm_regression) 2016-09-15 23:30:24 +07:00
benchmark port Windows driver support 2016-05-11 21:48:32 -07:00
cstest x86: printf64m should print qword ptr by default. TODO: fix related cases in tablegen instead 2019-06-09 01:58:03 +08:00
fuzz Fixed 47 missing dependencies and 51 excessive dependencies in Makefile (#1522) 2019-07-29 14:15:05 +08:00
MC cstest: fix xmmword ptr case in intel-syntax-encoding.s.cs 2019-06-09 02:05:31 +08:00
regress merge next to master 2018-07-20 12:36:50 +08:00
synctools Constify backends (#1549) 2019-12-23 20:30:57 +08:00
x86 suite: add some tools to verify X86 machine code 2015-01-06 13:11:04 +07:00
autogen_x86imm.py fix autogen_x86imm.py to handle some special instructions. this fixed issue #411 reported by @pancake 2015-06-30 20:49:55 +08:00
benchmark.py RISCV support ISRV32/ISRV64 (#1401) 2019-03-09 08:41:12 +08:00
capstone_get_setup.c RISCV support ISRV32/ISRV64 (#1401) 2019-03-09 08:41:12 +08:00
compile_all.sh last change to support BSD broke cross-comple. fix Makefile so cross-compile work again 2014-01-16 21:07:59 +08:00
disasm_mc.py RISCV support ISRV32/ISRV64 (#1401) 2019-03-09 08:41:12 +08:00
disasm_mc.sh suite: add disasm_mc.{py,sh} 2017-05-16 18:15:02 +07:00
fuzz.py RISCV support ISRV32/ISRV64 (#1401) 2019-03-09 08:41:12 +08:00
patch_major_os_version.py suite: correct authors of patch_major_os_version.py 2015-05-06 10:40:20 +08:00
ppcbranch.py suite: chmod +x ppcbranch.py 2014-10-01 18:17:37 +08:00
python_capstone_setup.py suite: add python_capstone_setup.py 2015-06-07 15:55:05 +08:00
README suite: add testsuite tool 'test_mc.sh' to compare output of Capstone & LLVM 2014-11-07 17:24:01 +08:00
regress.py Test suite update (#926) 2017-05-12 07:05:11 +07:00
test_all.sh suite: add test_all.sh 2014-01-21 12:02:30 +08:00
test_c.sh RISCV support ISRV32/ISRV64 (#1401) 2019-03-09 08:41:12 +08:00
test_corpus.py Corpus generation is more robust (#1419) 2019-03-11 13:12:54 +08:00
test_group_name.py RISCV support ISRV32/ISRV64 (#1401) 2019-03-09 08:41:12 +08:00
test_mc.py Add missing comma (#1458) 2019-04-12 01:15:11 +08:00
test_mc.sh suite: add testsuite tool 'test_mc.sh' to compare output of Capstone & LLVM 2014-11-07 17:24:01 +08:00
test_python.sh suite: add Sparc support 2014-03-10 15:44:48 +08:00
x86odd.py suite: add crc32 instruction to x86odd.py 2014-11-16 19:48:41 +08:00

This directory contains some tools used by developers of Capstone project.
Average users should ignore all the contents here.


- arm/
	Test some ARM's special input.

- MC/
	Input used to test various architectures & modes.

- benchmark.py
	This script benchmarks Python binding by disassembling some random code.

- test_*.sh
	Run all the tests and send the output to external file to be compared later.
	This is useful when we want to verify if a commit (wrongly) changes
	the disassemble result.

- compile_all.sh
	Compile Capstone for all platforms (*nix32, clang, cygwin, cross-compile) &
	report the result as pass or fail.

- fuzz.py
	This simple script disassembles random code for all archs (or selected arch)
	in order to find segfaults.

- test_mc.sh
    This script compares the output of Capstone with LLVM's llvm-mc with the
	input coming from MC/. This relies on test_mc.py to do all the hard works.

- x86odd.py
	Test some tricky X86 instructions.

- ppcbranch.py
	Test some tricky branch PPC instructions.