mirror of
https://github.com/capstone-engine/capstone.git
synced 2024-12-18 02:47:48 +00:00
b8fcf27b22
* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h
* Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction
* Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h
* Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter
* Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h
* Backport it from: 0db412ce3b
* All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly.
* Add refactored cs.c for RISCV
* Testing all I instructions in test_riscv.c
* Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture
* Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c
* fixed bug related to incorrect initialization of memory after malloc
* fix compile bug
* Fix compile errors.
* move riscv.h to include/capstone
* fix indentation issues
* fix coding style issues
* Fix indentation issues
* fix coding style
* Move variable declaration to the top of the block
* Fix coding indentation
* Move some stuff into RISCVMappingInsn.inc
* Fix code sytle
* remove cs_mode support for RISCV
* update asmwriter-inc to LLVM upstream
* update the .inc files to riscv upstream
* update riscv disassembler function for suport 16bit instructions
* update printer & tablegen inc files which have fixed arguments mismatch
* update headers and mapping source
* add riscv architecture specific test code
* fix all RISCV tons of compiler errors
* pass final tests
* add riscv tablegen patchs
* merge with upstream/next
* fix cstool missing riscv file
* fix root Makefile
* add new TableGen patchs for riscv
* fix cmakefile.txt of missing one riscv file
* fix declaration conflict
* fix incompatible declaration type
* change riscvc from arch to mode
* fix test_riscv warnning
* fix code style and add riscv part of test_basic
* add RISCV64 mode
* add suite for riscv
* crack fuzz test
* fix getfeaturebits test add riscvc
* fix test missing const qualifier warnning
* fix testcase type mismatch
* fix return value missing
* change getfeaturebits test
* add test cs files
* using a winder type contain the decode string
* fix a copy typo
* remove useless mode for riscv
* change cs file blank type
* add repo for update_riscv & fix cstool missing riscv mode
* fix typo
* add riscv for cstool useage
* add TableGen patch for riscv asmwriter
* clean ctags file
* remove black comment line
* fix fuzz related something
* fix missing RISCV string of fuzz
* update readme, etc..
* add riscv *.s.cs file
* add riscv *.s.cs file & clear ctags
* clear useless array declarations at capstone_test
* update to 5e4069f
* update readme change name more formal
* change position of riscv after bpf and modify copyright more uniform
* clear useless ctags file
* change blank with tab in riscv.h
* add riscv python bindings
* add riscv in __init__.py
* fix riscv define value for python binding
* fix test_riscv.py typo
* add missing riscvc in __init__.py of python bindings
* fix alias-insn printer bug, remove useless newline
* change inst print delimter from tab to bankspace for travis
* add riscv tablegen patch
* fix inst output more consistency
* add TableGen patch which fix inst output formal
* crack the effective address output for detail and change register print function
* fix not detail crash bug
* change item declaration position at cs_riscv
* update riscv.py
* change function name more meaningfull
* update python binding makefile
* fix register enum sequence according to riscvgenreginfo.inc
* test function name
* add enum s0/fp in riscv.h & update riscv_const.py
* add register name enum
83 lines
3.3 KiB
Makefile
83 lines
3.3 KiB
Makefile
# This file contains all customized compile options for Capstone.
|
|
# Consult COMPILE.TXT & docs/README for details.
|
|
|
|
################################################################################
|
|
# Specify which archs you want to compile in. By default, we build all archs.
|
|
|
|
CAPSTONE_ARCHS ?= arm aarch64 m68k mips powerpc sparc systemz x86 xcore tms320c64x m680x evm riscv mos65xx wasm bpf
|
|
|
|
|
|
################################################################################
|
|
# Comment out the line below ('CAPSTONE_USE_SYS_DYN_MEM = yes'), or change it to
|
|
# 'CAPSTONE_USE_SYS_DYN_MEM = no' if do NOT use malloc/calloc/realloc/free/
|
|
# vsnprintf() provided by system for internal dynamic memory management.
|
|
#
|
|
# NOTE: in that case, specify your own malloc/calloc/realloc/free/vsnprintf()
|
|
# functions in your program via API cs_option(), using CS_OPT_MEM option type.
|
|
|
|
CAPSTONE_USE_SYS_DYN_MEM ?= yes
|
|
|
|
|
|
################################################################################
|
|
# Change 'CAPSTONE_DIET = no' to 'CAPSTONE_DIET = yes' to make the library
|
|
# more compact: use less memory & smaller in binary size.
|
|
# This setup will remove the @mnemonic & @op_str data, plus semantic information
|
|
# such as @regs_read/write & @group. The amount of binary size reduced is
|
|
# up to 50% in some individual archs.
|
|
#
|
|
# NOTE: we still keep all those related fileds @mnemonic, @op_str, @regs_read,
|
|
# @regs_write, @groups, etc in fields in cs_insn structure regardless, but they
|
|
# will not be updated (i.e empty), thus become irrelevant.
|
|
|
|
CAPSTONE_DIET ?= no
|
|
|
|
|
|
################################################################################
|
|
# Change 'CAPSTONE_X86_REDUCE = no' to 'CAPSTONE_X86_REDUCE = yes' to remove
|
|
# non-critical instruction sets of X86, making the binary size smaller by ~60%.
|
|
# This is desired in special cases, such as OS kernel, where these kind of
|
|
# instructions are not used.
|
|
#
|
|
# The list of instruction sets to be removed includes:
|
|
# - Floating Point Unit (FPU)
|
|
# - MultiMedia eXtension (MMX)
|
|
# - Streaming SIMD Extensions (SSE)
|
|
# - 3DNow
|
|
# - Advanced Vector Extensions (AVX)
|
|
# - Fused Multiply Add Operations (FMA)
|
|
# - eXtended Operations (XOP)
|
|
# - Transactional Synchronization Extensions (TSX)
|
|
#
|
|
# Due to this removal, the related instructions are nolonger supported.
|
|
#
|
|
# By default, Capstone is compiled with 'CAPSTONE_X86_REDUCE = no',
|
|
# thus supports complete X86 instructions.
|
|
|
|
CAPSTONE_X86_REDUCE ?= no
|
|
|
|
################################################################################
|
|
# Change 'CAPSTONE_X86_ATT_DISABLE = no' to 'CAPSTONE_X86_ATT_DISABLE = yes' to
|
|
# disable AT&T syntax on x86 to reduce library size.
|
|
|
|
CAPSTONE_X86_ATT_DISABLE ?= no
|
|
|
|
################################################################################
|
|
# Change 'CAPSTONE_STATIC = yes' to 'CAPSTONE_STATIC = no' to avoid building
|
|
# a static library.
|
|
|
|
CAPSTONE_STATIC ?= yes
|
|
|
|
|
|
################################################################################
|
|
# Change 'CAPSTONE_SHARED = yes' to 'CAPSTONE_SHARED = no' to avoid building
|
|
# a shared library.
|
|
|
|
CAPSTONE_SHARED ?= yes
|
|
|
|
################################################################################
|
|
# Change 'CAPSTONE_HAS_OSXKERNEL = no' to 'CAPSTONE_HAS_OSXKERNEL = yes' to
|
|
# enable OS X kernel embedding support. If 'CAPSTONE_USE_SYS_DYN_MEM = yes',
|
|
# then kern_os_* functions are used for memory management.
|
|
|
|
CAPSTONE_HAS_OSXKERNEL ?= no
|