mirror of
https://github.com/capstone-engine/capstone.git
synced 2024-11-23 05:29:53 +00:00
ef89b18a88
* Update sysop inc file
* Fix missing braces warning
* Handle new system operands
* Fix build errors by renaming.
* Fix segfault
* Fix segfault
* Add custom MCOperand valiadtors
* Add AArch64 case for getFeatureBits
* Fix infinite loop
* Fix braces warning.
* Implement loopuo by name for sys operands
* Fix incorrect translation which remove else if statements.
* Fix several segfaults
* Rename GetRegFromClass patch
* Fix segfaults and asserts
* Fix segfault
* Move MRI setting to Mapping
* Remove unused code
* Add add_op_X functinos for AArch64.
* Add fill detail functins
* Handle RegWithShiftExtend operands
* Handle TypedVectorList operands.
* Handle ComplexRoatation operands
* Handle MemExtend operands
* Handle ImmRangeScale operands
* Handle ExactFPImm operands
* Handle GPRSeqPairsClass operands
* Handle Imm8OptLsl operands
* Handle ImmScale operands
* Handle LogicalImm operands
* Handle Matrix operands
* Handle SME Matrix tiles and vectors.
* Handle normal operands.
* Fix segfault.
* Handle PostInc operands.
* Reorder VecLayout enum to have no duplicate enum value.
* Handle PredicateAsCounter operands
* Handle ZPRasFPR operands
* Handle VectorIndex operands
* Handle UImm12Offset operands.
* Move reg suffix to enum val to single function.
* Handle SVERegOp operands
* Handle SVELogicalImm operands
* Handle SImm operand
* Handle PrefetchOp operands
* Handle Imm and ImmHex operands
* Handle GPR64as32 and GPR64x8 operands
* Add missing break
* Handle FPImm operand
* Handle ExtendedRegister opreand
* Handle CondCode operands
* Handle BTIHintOp operands
* Handle BarrierOption operands
* Handle BarrierXSOption
* Add not implemeted case again
* Handle ArithExtend operands
* Handle AdrpLabel and AlignedLabel operands
* Handle AMNoIndex operands
* Handle AddSubImm operands
* Handle MSRSystemRegisters and MRSSystemRegister operands
* Handle PSBHntOp and RPRFMOperand operands
* Remove unused variables
* Handle InverseCondCode operands
* Handle ImplicityTypedVectorList operands
* Handle ShiftedRegister operands
* Handle Shifter operands
* Handle SIMDType10Operand operands
* Handle SVCROp operands
* Handle SVEPattern operands
* Handle SVEVecLenSpecifier operands
* Handle SysCROperands
* Handle SysXzrPair operands
* Handle PState operands
* Handle VRegOperands
* Primt SME oeprands.
* Fix cs_operand.h include
* Rename arm64 -> aarch64 in python bindings.
* Add Python bindings for SH
* Fix ARM Python bindings (#2127)
* Restructure auto-sync update scripts.
* Move Helper functions to Updater dir
* Move requirements.txt
* Add basic ASUpdater.py
* Run black.
* Add inc file generater to updater
* Add option to select certain inc files fore generation.
* Enable clean build and implement patcher for inc files.
* Format config
* Patch main header files after inc generation.
* Implement clang-format function (unused yet, because it takes forever.)
* Copy generated inc files to arch dir
* Invert clean option (noramlly we need to clean the build dir.)
* Clearify arg doc
* Rename SystemRegister file for AArch64
* Centralize handling of path variables.
* Check if SystemOperands had to be generated before renaming on of its files.
* Replace class parameters by calling get_path
* Remove updater config which only contained paths.
* Add refactor option.
* Remove more path handling in the Configurator.
* Add translation step to updater.
* Fix includes after CppTranslator was moved into the Updater
* Remove updater config
* Fix several issue in the Configurator
* Fix file operations
* Remove addition argument from translator.
* Add Differ step to updater.
* Add path variable for arch_config
* Add diff step.
* Fix typo
* Introduce .clang-format path variable.
* Remove duplicate functions
* Add option to select update steps to execute.
* Check in write functions for write flag.
* Rename PatchMainHeader -> HeaderPatcher
* Move .gitignore
* Add README to vendor dir.
* Add all system operands to cstool output
* Update cstest with aarch64 changes
* Remove wb flag of aarch64 detail struct
* Set updates_flag after decoding
* Set writeback after decoding.
* Rename ARM64 -> AArch64
* Update printer and op mapping
* Exit normally
* Add AArch64 alias
* Fix some tmeplate function calls
* Fix flag check after rebase.
* Fix build by commentig unnused code.
* Add memory operand flag
* Handle memory operands printed via generic printOperand function.
* Handle UImm memory offsets
* Introduce MEM_REG and MEM_IMM op types
* Handle scaled memory immediates
* Check for op_count before checking for mem op at -1 index.
* Update memory operand flags.
* Pass imm/reg memory ops in set_imm/reg to set_mem.
* Add missing set_sme_operand call and fix assert.
* Remove CS_OP_MEM flag before entering switch.
* Preidcates are registers.
* Add shift info always to the previous operand
* Check for generic system regs
* Handle NumLanes = 0 LaneKind = q case
* Replace printImm call with normal print logic. Otherwise ops get added twice to detail.
* Handle FP operands in printOperand.
* Add access information to float operands.
* Rewrite SME matrix handling.
* Set correct SME layouts and allow for immediate range sme offsets.
* Handle cases of unknown system alias by setting their raw values
* Update cstool and header file with new SME offset handling
* Handle SME Tile lists.
* Fix build error in cstest
* Update MC tests for AArch64
* Handle TLBI operands and fix printing bug.
* Fix: Print signed value as signed.
* Add more system alias to detail.
* Remove duplicate hex prefix
* Set correct values for the register info
* Replace tabs with white spaces
* Move string append logic to own function.
* Set DecodeComplete = true before decoding (as originally in the LLVM code).
* Change type of feature argument, since only LLVM features are passed, not CS groups.
* Imitate lower_bound for the index table binary search.
* Remove trailing comments from test files.
* Print shift amount in decimal
* Save detail of shift alias instructions.
* Add extension details fot ext instruction alias
* Print LSB and width in decimal
* Fix LLVM bug. The feature check for V8_2a doesn't check if all features are enabled.
* Fix lower_bounds check.
For m == 0 we wrap around 0 of cause.
* Fix feature check. Add check for FeatureAll since it includes XS
* Operate on temporary MCInst when trying decoding.
* Add lower_bound behavior to IndexTypeStr binsearch.
* Fix MC tests which were incorrect because of missing FeatureAll check
* Add Alias handling for AArch64
* Update system operands with SYSIMM types and add additional sysop category.
* Add macros for meta programming (ARM64 <-> AArch64 selection).
* Fix union/struct confusion and add raw_value member to uninions.
* Allow to set Syntax and mode options for AArch64
* Fix build warning by using correct type
* Print shift value in decimal
* Add missing call to add_cs_detail.
* Update name map files with normalized names.
* Remove unused function
* Add check if detail should be filled.
* Fill detail for real instructions if only real detail is requested.
* Add always the extension.
* Make dir creation log message debug level
* Implement ADR immediate operand printer.
See: c3484b1fdc
* Check for flag registers beeing written and update flag.
* Move multiple CondCode helpers to aarch64.h because they are so freaking useful.
+ Print CC if it is EQ
* Fix incorrectly initialized CC and VectorLayout.
* Add LSL shift type for extensions.
* Fix case when shift amount is 0
* Fix post-index memory instructions.
* Pass raw immediate through getShiftValue to extract actual shift amount
* Setup AArch64 detail ops.
* Add flag for operands part of a list.
* Set vector indices for all relevant registers.
* Add missing call to add_cs_detail for postIncOperands
* Add ugly yet reliable way to determine post-index addressing mode
* Add support for old Capstone register alias.
* Remove leading space before some alias mnemonics.
* add AARCH64 to `cmake.sh`
* add HAS_AARCH64 to `cs.c`
* should probably just reference `cs_operand.h` in `aarch64.h`
* hint compiler at `AArch64_SYSREG` enum type for casting purposes
* update `Makefile` for AARCH64
leaves `CAPSTONE_HAS_ARM64` supported
* `testFeatureBits` platform function check
`testFeatureBits` should check if the platform function is visible first
* update tests to use AARCH64 convention
* hack: avoid enum casts for `MCInst` Values
Apple compiler really hates typecasting a enum, even if bounded from a unsigned. Lets set the raw_value directly
is a hack and needs proper review
* Check for present detail before accessing it.
* Add CS only groups
* Use general map ins_op type
* Fix build warning about str size computation.
* Disable warning about unitialized value for GCC 11.
Imm is initialized and the warning does not appear
in later versions.
* Use correct include guard for PPC
* Add missing requirements
* Update SystemOperand enums.
* Fix overlapping comparison warning
* Fix reachable assert where OpNum is not of type IMM
* Handle 0.0 operand for fcmp
* Fix incorrect variable passed.
* Fix for MacOS which doesn't know the warning and throws another one.
* Make getExtendEncoding static to fix build warning on MSVC.
* Fix build error: 'missing binary operator before token' by checking __GNUC__
* Add string search to add vector layout info.
* Add missing mem disponents of several ldr and str instructions.
* Add 0 immediates to several instructions.
* Rename v regs to q and d variant.
The cs_regname API can not pass the variant name of the register requested.
So we simply emit the default variant name.
* Fix incorrect enum value.
* Fix tests for system operands.
* Fix syntax issues in tests.
* Rename Arm64 -> AArch64 Python bindings.
* Fix Python bindings C structs.
* Fix generation of constants (ARMCC skipped because it starts with ARM)
* Update const files
* Remove -Wmaybe-uninitialized warning since it fails fuzz build
* Add missing comma
* Fix case
* Fix AArch64 Python bindings:
- Do not generate constants automatically (dscript is way too buggy).
- Update printing of details.
* Rename ARM64 -> AArch64 in test_corpus.py
* Rename test_arm64 -> test_aarch64
* Rename ARM-64 -> AArch64
* Fix diff CI test by disassembling AArch64 at former ARM64 place
* Fix several wrong types and remove unnecessary memebers from Python binding
* Fix: Same printing format of detail for cstool, test_ and test_*.py
* Fix: pass correct op index for mov alias with op[1] == reg wzr.
* Set prfm op manuall in case of unnown sysop. set_imm would add it to an memory operand wihtout base.
* Fix: If barrier ops are not set an assert is reached.
We fix it here by simply getting the immediate as the printing code does.
---------
Co-authored-by: Peace-Maker <peace-maker@wcfan.de>
Co-authored-by: Dayton <5340801+watbulb@users.noreply.github.com>
253 lines
7.5 KiB
C
253 lines
7.5 KiB
C
/* Capstone Disassembly Engine */
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/* By Rot127 <unisono@quyllur.org>, 2023 */
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#include "MCInstPrinter.h"
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#include "cs_priv.h"
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#include <capstone/platform.h>
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extern bool ARM_getFeatureBits(unsigned int mode, unsigned int feature);
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extern bool PPC_getFeatureBits(unsigned int mode, unsigned int feature);
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extern bool AArch64_getFeatureBits(unsigned int mode, unsigned int feature);
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static bool testFeatureBits(const MCInst *MI, uint32_t Value)
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{
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assert(MI && MI->csh);
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switch (MI->csh->arch) {
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default:
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assert(0 && "Not implemented for current arch.");
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return false;
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#ifdef CAPSTONE_HAS_ARM
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case CS_ARCH_ARM:
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return ARM_getFeatureBits(MI->csh->mode, Value);
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#endif
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#ifdef CAPSTONE_HAS_POWERPC
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case CS_ARCH_PPC:
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return PPC_getFeatureBits(MI->csh->mode, Value);
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#endif
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#ifdef CAPSTONE_HAS_AARCH64
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case CS_ARCH_AARCH64:
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return AArch64_getFeatureBits(MI->csh->mode, Value);
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#endif
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}
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}
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static bool matchAliasCondition(MCInst *MI, const MCRegisterInfo *MRI,
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unsigned *OpIdx, const AliasMatchingData *M,
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const AliasPatternCond *C,
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bool *OrPredicateResult)
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{
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// Feature tests are special, they don't consume operands.
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if (C->Kind == AliasPatternCond_K_Feature)
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return testFeatureBits(MI, C->Value);
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if (C->Kind == AliasPatternCond_K_NegFeature)
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return !testFeatureBits(MI, C->Value);
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// For feature tests where just one feature is required in a list, set the
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// predicate result bit to whether the expression will return true, and only
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// return the real result at the end of list marker.
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if (C->Kind == AliasPatternCond_K_OrFeature) {
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*OrPredicateResult |= testFeatureBits(MI, C->Value);
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return true;
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}
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if (C->Kind == AliasPatternCond_K_OrNegFeature) {
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*OrPredicateResult |= !(testFeatureBits(MI, C->Value));
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return true;
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}
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if (C->Kind == AliasPatternCond_K_EndOrFeatures) {
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bool Res = *OrPredicateResult;
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*OrPredicateResult = false;
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return Res;
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}
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// Get and consume an operand.
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MCOperand *Opnd = MCInst_getOperand(MI, *OpIdx);
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++(*OpIdx);
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// Check the specific condition for the operand.
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switch (C->Kind) {
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default:
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assert(0 && "invalid kind");
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case AliasPatternCond_K_Imm:
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// Operand must be a specific immediate.
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return MCOperand_isImm(Opnd) &&
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MCOperand_getImm(Opnd) == (int32_t)C->Value;
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case AliasPatternCond_K_Reg:
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// Operand must be a specific register.
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return MCOperand_isReg(Opnd) && MCOperand_getReg(Opnd) == C->Value;
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case AliasPatternCond_K_TiedReg:
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// Operand must match the register of another operand.
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return MCOperand_isReg(Opnd) &&
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MCOperand_getReg(Opnd) ==
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MCOperand_getReg(MCInst_getOperand(MI, C->Value));
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case AliasPatternCond_K_RegClass:
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// Operand must be a register in this class. Value is a register class
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// id.
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return MCOperand_isReg(Opnd) &&
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MCRegisterClass_contains(
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MCRegisterInfo_getRegClass(MRI, C->Value),
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MCOperand_getReg(Opnd));
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case AliasPatternCond_K_Custom:
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// Operand must match some custom criteria.
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assert(M->ValidateMCOperand && "A custom validator should be set but isn't.");
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return M->ValidateMCOperand(Opnd, C->Value);
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case AliasPatternCond_K_Ignore:
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// Operand can be anything.
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return true;
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case AliasPatternCond_K_Feature:
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case AliasPatternCond_K_NegFeature:
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case AliasPatternCond_K_OrFeature:
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case AliasPatternCond_K_OrNegFeature:
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case AliasPatternCond_K_EndOrFeatures:
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assert(0 && "handled earlier");
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}
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return false;
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}
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/// Check if PatternsForOpcode is all zero.
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static inline bool validOpToPatter(const PatternsForOpcode *P)
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{
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return !(P->Opcode == 0 && P->PatternStart == 0 && P->NumPatterns == 0);
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}
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const char *matchAliasPatterns(MCInst *MI, const AliasMatchingData *M)
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{
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// TODO Rewrite to C
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// auto It = lower_bound(M.OpToPatterns, MI->getOpcode(),
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// [](const PatternsForOpcode &L, unsigned Opcode) {
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// return L.Opcode < Opcode;
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// });
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// if (It == M.OpToPatterns.end() || It->Opcode != MI->getOpcode())
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// return nullptr;
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// Binary search by opcode. Return false if there are no aliases for this
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// opcode.
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unsigned MIOpcode = MI->Opcode;
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size_t i = 0;
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uint32_t PatternOpcode = M->OpToPatterns[i].Opcode;
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while (PatternOpcode < MIOpcode && validOpToPatter(&M->OpToPatterns[i]))
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PatternOpcode = M->OpToPatterns[++i].Opcode;
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if (PatternOpcode != MI->Opcode || !validOpToPatter(&M->OpToPatterns[i]))
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return NULL;
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// // Try all patterns for this opcode.
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uint32_t AsmStrOffset = ~0U;
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const AliasPattern *Patterns = M->Patterns + M->OpToPatterns[i].PatternStart;
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for (const AliasPattern *P = Patterns;
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P != Patterns + M->OpToPatterns[i].NumPatterns; ++P) {
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// Check operand count first.
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if (MCInst_getNumOperands(MI) != P->NumOperands)
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return NULL;
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// Test all conditions for this pattern.
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const AliasPatternCond *Conds = M->PatternConds + P->AliasCondStart;
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unsigned OpIdx = 0;
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bool OrPredicateResult = false;
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bool allMatch = true;
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for (const AliasPatternCond *C = Conds; C != Conds + P->NumConds; ++C) {
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if (!matchAliasCondition(MI, MI->MRI, &OpIdx, M, C, &OrPredicateResult)) {
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allMatch = false;
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break;
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}
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}
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if (allMatch) {
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AsmStrOffset = P->AsmStrOffset;
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break;
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}
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}
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// If no alias matched, don't print an alias.
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if (AsmStrOffset == ~0U)
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return NULL;
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// Go to offset AsmStrOffset and use the null terminated string there. The
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// offset should point to the beginning of an alias string, so it should
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// either be zero or be preceded by a null byte.
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return M->AsmStrings + AsmStrOffset;
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}
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// TODO Add functionality to toggle the flag.
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bool getUseMarkup(void) { return false; }
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/// Utility functions to make adding mark ups simpler.
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const char *markup(const char *s)
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{
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static const char *no_markup = "";
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if (getUseMarkup())
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return s;
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else
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return no_markup;
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}
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// binary search for encoding in IndexType array
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// return -1 if not found, or index if found
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unsigned int binsearch_IndexTypeEncoding(const struct IndexType *index, size_t size, uint16_t encoding)
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{
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// binary searching since the index is sorted in encoding order
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size_t left, right, m;
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right = size - 1;
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if (encoding < index[0].encoding || encoding > index[right].encoding)
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// not found
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return -1;
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left = 0;
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while(left <= right) {
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m = (left + right) / 2;
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if (encoding == index[m].encoding) {
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// LLVM actually uses lower_bound for the index table search
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// Here we need to check if a previous entry is of the same encoding
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// and return the first one.
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while (m > 0 && encoding == index[m - 1].encoding)
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--m;
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return m;
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}
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if (encoding < index[m].encoding)
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right = m - 1;
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else
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left = m + 1;
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}
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// not found
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return -1;
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}
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// binary search for encoding in IndexTypeStr array
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// return -1 if not found, or index if found
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unsigned int binsearch_IndexTypeStrEncoding(const struct IndexTypeStr *index, size_t size, const char *name)
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{
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// binary searching since the index is sorted in encoding order
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size_t left, right, m;
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right = size - 1;
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size_t str_left_cmp = strcmp(name, index[0].name);
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size_t str_right_cmp = strcmp(name, index[right].name);
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if (str_left_cmp < 0 || str_right_cmp > 0)
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// not found
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return -1;
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left = 0;
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while(left <= right) {
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m = (left + right) / 2;
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if (strcmp(name, index[m].name) == 0) {
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// LLVM actually uses lower_bound for the index table search
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// Here we need to check if a previous entry is of the same encoding
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// and return the first one.
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while (m > 0 && (strcmp(name, index[m - 1].name) == 0))
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--m;
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return m;
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}
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if (strcmp(name, index[m].name) < 0)
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right = m - 1;
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else
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left = m + 1;
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}
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// not found
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return -1;
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}
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