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* Added new M680X target. Supports M6800/1/2/3/9, HD6301 * M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT * M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec > k cpu type, no default. * M680X: Add python bindings. Added python tests. * M680X: Added cpu types to usage message. * cstool: Avoid segfault for invalid <arch+mode>. * Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched. * M680X: Update CMake/make for m680x support. Update .gitignore. * M680X: Reduce compiler warnings. * M680X: Reduce compiler warnings. * M680X: Reduce compiler warnings. * M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). * M680X: Add ocaml bindings and tests. * M680X: Add java bindings and tests. * M680X: Added tests for all indexed addressing modes. C/Python/Ocaml * M680X: Naming, use page1 for PAGE1 instructions (without prefix). * M680X: Naming, use page1 for PAGE1 instructions (without prefix). * M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml. * M680X: Added access property to cs_m680x_op. * M680X: Added operand size. * M680X: Remove compiler warnings. * M680X: Added READ/WRITE access property per operator. * M680X: Make reg_inherent_hdlr independent of CPU type. * M680X: Add HD6309 support + bug fixes * M680X: Remove errors and warning. * M680X: Add Bcc/LBcc to group BRAREL (relative branch). * M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN. * M680X: Remove LBRN from group BRAREL. * M680X: Refactored cpu_type initialization for better readability. * M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX. * M680X: Remove typo in cstool.c * M680X: Some format improvements in changed_regs. * M680X: Remove insn id string list from tests (C/python/java/ocaml). * M680X: SEXW, set access of reg. D to WRITE. * M680X: Sort changed_regs in increasing m680x_insn order. * M680X: Add M68HC11 support + Reduced from two to one INDEXED operand. * M680X: cstool, also write '(in mnemonic)' for second reg. operand. * M680X: Add BRN/LBRN to group JUMP and BRAREL. * M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access. * M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED. * M680X: Rename some instruction handlers. * M680X: Add M68HC05 support. * M680X: Dont print prefix '<' for direct addr. mode. * M680X: Add M68HC08 support + resorted tables + bug fixes. * M680X: Add Freescale HCS08 support. * M680X: Changed group names, avoid spaces. * M680X: Refactoring, rename addessing mode handlers. * M680X: indexed addr. mode, changed pre/post inc-/decrement representation. * M680X: Rename some M6809/HD6309 specific functions. * M680X: Add CPU12 (68HC12/HCS12) support. * M680X: Correctly display illegal instruction as FCB . * M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg. * M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing. * M680X: Better support for changing insn id within handler for addessing mode. * M680X: Remove warnings. * M680X: In set_changed_regs_read_write_counts use own access_mode. * M680X: Split cpu specific tables into separate *.inc files. * M680X: Remove warnings. * M680X: Removed address_mode. Addressing mode is available in operand.type * M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg. * M680X: Remove register TMP1. It is first visible in CPU12X. * M680X: Performance improvement + bug fixes. * M680X: Performance improvement, make cpu_tables const static. * M680X: Simplify operand decoding by using two handlers. * M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings. * M680X: Format with astyle. * M680X: Update documentation. * M680X: Corrected author for m680x specific files. * M680X: Make max. number of architectures single source.
70 lines
2.1 KiB
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70 lines
2.1 KiB
Plaintext
This file credits all the contributors of the Capstone engine project.
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Key developers
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==============
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1. Nguyen Anh Quynh <aquynh -at- gmail.com>
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- Core engine
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- Bindings: Python, Ruby, OCaml, Java, C#
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2. Tan Sheng Di <shengdi -at- coseinc.com>
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- Bindings: Ruby
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3. Ben Nagy <ben -at- coseinc.com>
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- Bindings: Ruby, Go
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4. Dang Hoang Vu <dang.hvu -at- gmail.com>
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- Bindings: Java
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Beta testers (in random order)
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==============================
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Pancake
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Van Hauser
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FX of Phenoelit
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The Grugq, The Grugq <-- our hero for submitting the first ever patch!
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Isaac Dawson, Veracode Inc
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Patroklos Argyroudis, Census Inc. (http://census-labs.com)
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Attila Suszter
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Le Dinh Long
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Nicolas Ruff
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Gunther
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Alex Ionescu, Winsider Seminars & Solutions Inc.
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Snare
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Daniel Godas-Lopez
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Joshua J. Drake
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Edgar Barbosa
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Ralf-Philipp Weinmann
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Hugo Fortier
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Joxean Koret
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Bruce Dang
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Andrew Dunham
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Contributors (in no particular order)
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=====================================
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(Please let us know if you want to have your name here)
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Ole André Vadla Ravnås (author of the 100th Pull-Request in our Github repo, thanks!)
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Axel "0vercl0k" Souchet (@0vercl0k) & Alex Ionescu: port to MSVC.
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Daniel Pistelli: Cmake support.
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Peter Hlavaty: integrate Capstone for Windows kernel drivers.
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Guillaume Jeanne: Ocaml binding.
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Martin Tofall, Obsidium Software: Optimize X86 performance & size.
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David Martínez Moreno & Hilko Bengen: Debian package.
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Félix Cloutier: Xcode project.
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Benoit Lecocq: OpenBSD package.
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Christophe Avoinne (Hlide): Improve memory management for better performance.
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Michael Cohen & Nguyen Tan Cong: Python module installer.
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Bui Dinh Cuong: Explicit registers accessed for Arm64.
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Vincent Bénony: Explicit registers accessed for X86.
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Adel Gadllah, Francisco Alonso & Stefan Cornelius: RPM package.
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Felix Gröbert (Google): fuzz testing harness.
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Daniel Collin & Nicolas Planel: M68K architecture.
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Pranith Kumar: Explicit registers accessed for Arm64.
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Xipiter LLC: Capstone logo redesigned.
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Satoshi Tanda: Support Windows kernel driver.
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Koutheir Attouchi: Support for Windows CE.
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Fotis Loukos: TMS320C64x architecture.
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Wolfgang Schwotzer: M680X architecture.
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