mirror of
https://github.com/capstone-engine/capstone.git
synced 2025-03-04 12:27:12 +00:00
22b4d0eb41
* Added new M680X target. Supports M6800/1/2/3/9, HD6301 * M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT * M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec > k cpu type, no default. * M680X: Add python bindings. Added python tests. * M680X: Added cpu types to usage message. * cstool: Avoid segfault for invalid <arch+mode>. * Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched. * M680X: Update CMake/make for m680x support. Update .gitignore. * M680X: Reduce compiler warnings. * M680X: Reduce compiler warnings. * M680X: Reduce compiler warnings. * M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). * M680X: Add ocaml bindings and tests. * M680X: Add java bindings and tests. * M680X: Added tests for all indexed addressing modes. C/Python/Ocaml * M680X: Naming, use page1 for PAGE1 instructions (without prefix). * M680X: Naming, use page1 for PAGE1 instructions (without prefix). * M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml. * M680X: Added access property to cs_m680x_op. * M680X: Added operand size. * M680X: Remove compiler warnings. * M680X: Added READ/WRITE access property per operator. * M680X: Make reg_inherent_hdlr independent of CPU type. * M680X: Add HD6309 support + bug fixes * M680X: Remove errors and warning. * M680X: Add Bcc/LBcc to group BRAREL (relative branch). * M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN. * M680X: Remove LBRN from group BRAREL. * M680X: Refactored cpu_type initialization for better readability. * M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX. * M680X: Remove typo in cstool.c * M680X: Some format improvements in changed_regs. * M680X: Remove insn id string list from tests (C/python/java/ocaml). * M680X: SEXW, set access of reg. D to WRITE. * M680X: Sort changed_regs in increasing m680x_insn order. * M680X: Add M68HC11 support + Reduced from two to one INDEXED operand. * M680X: cstool, also write '(in mnemonic)' for second reg. operand. * M680X: Add BRN/LBRN to group JUMP and BRAREL. * M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access. * M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED. * M680X: Rename some instruction handlers. * M680X: Add M68HC05 support. * M680X: Dont print prefix '<' for direct addr. mode. * M680X: Add M68HC08 support + resorted tables + bug fixes. * M680X: Add Freescale HCS08 support. * M680X: Changed group names, avoid spaces. * M680X: Refactoring, rename addessing mode handlers. * M680X: indexed addr. mode, changed pre/post inc-/decrement representation. * M680X: Rename some M6809/HD6309 specific functions. * M680X: Add CPU12 (68HC12/HCS12) support. * M680X: Correctly display illegal instruction as FCB . * M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg. * M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing. * M680X: Better support for changing insn id within handler for addessing mode. * M680X: Remove warnings. * M680X: In set_changed_regs_read_write_counts use own access_mode. * M680X: Split cpu specific tables into separate *.inc files. * M680X: Remove warnings. * M680X: Removed address_mode. Addressing mode is available in operand.type * M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg. * M680X: Remove register TMP1. It is first visible in CPU12X. * M680X: Performance improvement + bug fixes. * M680X: Performance improvement, make cpu_tables const static. * M680X: Simplify operand decoding by using two handlers. * M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings. * M680X: Format with astyle. * M680X: Update documentation. * M680X: Corrected author for m680x specific files. * M680X: Make max. number of architectures single source.
96 lines
2.9 KiB
C
96 lines
2.9 KiB
C
/* Capstone Disassembly Engine */
|
|
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
|
|
|
|
#ifndef CS_PRIV_H
|
|
#define CS_PRIV_H
|
|
|
|
#include <capstone/capstone.h>
|
|
|
|
#include "MCInst.h"
|
|
#include "SStream.h"
|
|
|
|
typedef void (*Printer_t)(MCInst *MI, SStream *OS, void *info);
|
|
|
|
// function to be called after Printer_t
|
|
// this is the best time to gather insn's characteristics
|
|
typedef void (*PostPrinter_t)(csh handle, cs_insn *, char *mnem, MCInst *mci);
|
|
|
|
typedef bool (*Disasm_t)(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info);
|
|
|
|
typedef const char *(*GetName_t)(csh handle, unsigned int id);
|
|
|
|
typedef void (*GetID_t)(cs_struct *h, cs_insn *insn, unsigned int id);
|
|
|
|
// return register name, given register ID
|
|
typedef char *(*GetRegisterName_t)(unsigned RegNo);
|
|
|
|
// return registers accessed by instruction
|
|
typedef void (*GetRegisterAccess_t)(const cs_insn *insn,
|
|
cs_regs regs_read, uint8_t *regs_read_count,
|
|
cs_regs regs_write, uint8_t *regs_write_count);
|
|
|
|
// for ARM only
|
|
typedef struct ARM_ITStatus {
|
|
unsigned char ITStates[8];
|
|
unsigned int size;
|
|
} ARM_ITStatus;
|
|
|
|
// Customize mnemonic for instructions with alternative name.
|
|
struct customized_mnem {
|
|
// ID of instruction to be customized.
|
|
unsigned int id;
|
|
// Customized instruction mnemonic.
|
|
char mnemonic[CS_MNEMONIC_SIZE];
|
|
};
|
|
|
|
struct insn_mnem {
|
|
struct customized_mnem insn;
|
|
struct insn_mnem *next; // linked list of customized mnemonics
|
|
};
|
|
|
|
struct cs_struct {
|
|
cs_arch arch;
|
|
cs_mode mode;
|
|
Printer_t printer; // asm printer
|
|
void *printer_info; // aux info for printer
|
|
Disasm_t disasm; // disassembler
|
|
void *getinsn_info; // auxiliary info for printer
|
|
bool big_endian;
|
|
GetName_t reg_name;
|
|
GetName_t insn_name;
|
|
GetName_t group_name;
|
|
GetID_t insn_id;
|
|
PostPrinter_t post_printer;
|
|
cs_err errnum;
|
|
ARM_ITStatus ITBlock; // for Arm only
|
|
cs_opt_value detail, imm_unsigned;
|
|
int syntax; // asm syntax for simple printer such as ARM, Mips & PPC
|
|
bool doing_mem; // handling memory operand in InstPrinter code
|
|
unsigned short *insn_cache; // index caching for mapping.c
|
|
GetRegisterName_t get_regname;
|
|
bool skipdata; // set this to True if we skip data when disassembling
|
|
uint8_t skipdata_size; // how many bytes to skip
|
|
cs_opt_skipdata skipdata_setup; // user-defined skipdata setup
|
|
uint8_t *regsize_map; // map to register size (x86-only for now)
|
|
GetRegisterAccess_t reg_access;
|
|
struct insn_mnem *mnem_list; // linked list of customized instruction mnemonic
|
|
};
|
|
|
|
#define MAX_ARCH CS_ARCH_MAX
|
|
|
|
// constructor initialization for all archs
|
|
extern cs_err (*arch_init[MAX_ARCH]) (cs_struct *);
|
|
|
|
// support cs_option() for all archs
|
|
extern cs_err (*arch_option[MAX_ARCH]) (cs_struct*, cs_opt_type, size_t value);
|
|
|
|
extern unsigned int all_arch;
|
|
|
|
extern cs_malloc_t cs_mem_malloc;
|
|
extern cs_calloc_t cs_mem_calloc;
|
|
extern cs_realloc_t cs_mem_realloc;
|
|
extern cs_free_t cs_mem_free;
|
|
extern cs_vsnprintf_t cs_vsnprintf;
|
|
|
|
#endif
|