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capstone/arch
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Richard Henderson e34cd5475b Two RISC-V fixes (#1682) 
* RISCV: Check CS_MODE_RISCVC in getFeatureBits

Enable compressed instruction extension with RISCVC.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

* RISCV: Fix skipdata_size for CS_MODE_RISCVC

RISC-V compressed instructions are 2 bytes, not 1.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-09-16 17:04:18 +08:00
..
AArch64
Add more cases for LD1 instruction immediate fixups (#1632)
2020-05-10 10:03:52 +08:00
ARM
fix: Remove wrong write in ARM_t2STMDB_UPD instruction (#1588)
2020-02-21 09:56:35 +08:00
BPF
Constify backends (#1549)
2019-12-23 20:30:57 +08:00
EVM
Constify backends (#1549)
2019-12-23 20:30:57 +08:00
M68K
M68K: fix MOVEC operand transfer direction. (#1663)
2020-07-19 17:06:08 +08:00
M680X
Constify backends (#1549)
2019-12-23 20:30:57 +08:00
Mips
Constify backends (#1549)
2019-12-23 20:30:57 +08:00
MOS65XX
Constify backends (#1549)
2019-12-23 20:30:57 +08:00
PowerPC
Constify backends (#1549)
2019-12-23 20:30:57 +08:00
RISCV
Two RISC-V fixes (#1682)
2020-09-16 17:04:18 +08:00
Sparc
Constify backends (#1549)
2019-12-23 20:30:57 +08:00
SystemZ
Constify backends (#1549)
2019-12-23 20:30:57 +08:00
TMS320C64x
Constify backends (#1549)
2019-12-23 20:30:57 +08:00
WASM
Constify backends (#1549)
2019-12-23 20:30:57 +08:00
X86
fix bug in displacement offset (#1600)
2020-05-11 02:20:13 +08:00
XCore
Constify backends (#1549)
2019-12-23 20:30:57 +08:00