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e8d1f1d4d2
* Added new M680X target. Supports M6800/1/2/3/9, HD6301 * M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT * M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec > k cpu type, no default. * M680X: Add python bindings. Added python tests. * M680X: Added cpu types to usage message. * cstool: Avoid segfault for invalid <arch+mode>. * Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched. * M680X: Update CMake/make for m680x support. Update .gitignore. * M680X: Reduce compiler warnings. * M680X: Reduce compiler warnings. * M680X: Reduce compiler warnings. * M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). * M680X: Add ocaml bindings and tests. * M680X: Add java bindings and tests. * M680X: Added tests for all indexed addressing modes. C/Python/Ocaml * M680X: Naming, use page1 for PAGE1 instructions (without prefix). * M680X: Naming, use page1 for PAGE1 instructions (without prefix). * M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml. * M680X: Added access property to cs_m680x_op. * M680X: Added operand size. * M680X: Remove compiler warnings. * M680X: Added READ/WRITE access property per operator. * M680X: Make reg_inherent_hdlr independent of CPU type. * M680X: Add HD6309 support + bug fixes * M680X: Remove errors and warning. * M680X: Add Bcc/LBcc to group BRAREL (relative branch). * M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN. * M680X: Remove LBRN from group BRAREL. * M680X: Refactored cpu_type initialization for better readability. * M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX. * M680X: Remove typo in cstool.c * M680X: Some format improvements in changed_regs. * M680X: Remove insn id string list from tests (C/python/java/ocaml). * M680X: SEXW, set access of reg. D to WRITE. * M680X: Sort changed_regs in increasing m680x_insn order. * M680X: Add M68HC11 support + Reduced from two to one INDEXED operand. * M680X: cstool, also write '(in mnemonic)' for second reg. operand. * M680X: Add BRN/LBRN to group JUMP and BRAREL. * M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access. * M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED. * M680X: Rename some instruction handlers. * M680X: Add M68HC05 support. * M680X: Dont print prefix '<' for direct addr. mode. * M680X: Add M68HC08 support + resorted tables + bug fixes. * M680X: Add Freescale HCS08 support. * M680X: Changed group names, avoid spaces. * M680X: Refactoring, rename addessing mode handlers. * M680X: indexed addr. mode, changed pre/post inc-/decrement representation. * M680X: Rename some M6809/HD6309 specific functions. * M680X: Add CPU12 (68HC12/HCS12) support. * M680X: Correctly display illegal instruction as FCB . * M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg. * M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing. * M680X: Better support for changing insn id within handler for addessing mode. * M680X: Remove warnings. * M680X: In set_changed_regs_read_write_counts use own access_mode. * M680X: Split cpu specific tables into separate *.inc files. * M680X: Remove warnings. * M680X: Removed address_mode. Addressing mode is available in operand.type * M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg. * M680X: Remove register TMP1. It is first visible in CPU12X. * M680X: Performance improvement + bug fixes. * M680X: Performance improvement, make cpu_tables const static. * M680X: Simplify operand decoding by using two handlers. * M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings. * M680X: Format with astyle. * M680X: Update documentation. * M680X: Corrected author for m680x specific files. * M680X: Make max. number of architectures single source.
83 lines
3.3 KiB
Makefile
83 lines
3.3 KiB
Makefile
# This file contains all customized compile options for Capstone.
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# Consult COMPILE.TXT & docs/README for details.
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################################################################################
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# Specify which archs you want to compile in. By default, we build all archs.
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CAPSTONE_ARCHS ?= arm aarch64 m68k mips powerpc sparc systemz x86 xcore tms320c64x m680x
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################################################################################
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# Comment out the line below ('CAPSTONE_USE_SYS_DYN_MEM = yes'), or change it to
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# 'CAPSTONE_USE_SYS_DYN_MEM = no' if do NOT use malloc/calloc/realloc/free/
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# vsnprintf() provided by system for internal dynamic memory management.
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#
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# NOTE: in that case, specify your own malloc/calloc/realloc/free/vsnprintf()
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# functions in your program via API cs_option(), using CS_OPT_MEM option type.
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CAPSTONE_USE_SYS_DYN_MEM ?= yes
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################################################################################
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# Change 'CAPSTONE_DIET = no' to 'CAPSTONE_DIET = yes' to make the library
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# more compact: use less memory & smaller in binary size.
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# This setup will remove the @mnemonic & @op_str data, plus semantic information
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# such as @regs_read/write & @group. The amount of binary size reduced is
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# up to 50% in some individual archs.
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#
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# NOTE: we still keep all those related fileds @mnemonic, @op_str, @regs_read,
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# @regs_write, @groups, etc in fields in cs_insn structure regardless, but they
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# will not be updated (i.e empty), thus become irrelevant.
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CAPSTONE_DIET ?= no
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################################################################################
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# Change 'CAPSTONE_X86_REDUCE = no' to 'CAPSTONE_X86_REDUCE = yes' to remove
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# non-critical instruction sets of X86, making the binary size smaller by ~60%.
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# This is desired in special cases, such as OS kernel, where these kind of
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# instructions are not used.
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#
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# The list of instruction sets to be removed includes:
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# - Floating Point Unit (FPU)
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# - MultiMedia eXtension (MMX)
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# - Streaming SIMD Extensions (SSE)
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# - 3DNow
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# - Advanced Vector Extensions (AVX)
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# - Fused Multiply Add Operations (FMA)
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# - eXtended Operations (XOP)
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# - Transactional Synchronization Extensions (TSX)
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#
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# Due to this removal, the related instructions are nolonger supported.
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#
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# By default, Capstone is compiled with 'CAPSTONE_X86_REDUCE = no',
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# thus supports complete X86 instructions.
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CAPSTONE_X86_REDUCE ?= no
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################################################################################
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# Change 'CAPSTONE_X86_ATT_DISABLE = no' to 'CAPSTONE_X86_ATT_DISABLE = yes' to
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# disable AT&T syntax on x86 to reduce library size.
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CAPSTONE_X86_ATT_DISABLE ?= no
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################################################################################
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# Change 'CAPSTONE_STATIC = yes' to 'CAPSTONE_STATIC = no' to avoid building
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# a static library.
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CAPSTONE_STATIC ?= yes
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################################################################################
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# Change 'CAPSTONE_SHARED = yes' to 'CAPSTONE_SHARED = no' to avoid building
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# a shared library.
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CAPSTONE_SHARED ?= yes
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################################################################################
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# Change 'CAPSTONE_HAS_OSXKERNEL = no' to 'CAPSTONE_HAS_OSXKERNEL = yes' to
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# enable OS X kernel embedding support. If 'CAPSTONE_USE_SYS_DYN_MEM = yes',
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# then kern_os_* functions are used for memory management.
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CAPSTONE_HAS_OSXKERNEL ?= no
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