mirror of
https://github.com/capstone-engine/capstone.git
synced 2024-11-27 15:30:33 +00:00
11343 lines
357 KiB
C++
11343 lines
357 KiB
C++
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|* *|
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|*Assembly Writer Source Fragment *|
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|* *|
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|* Automatically generated file, do not edit! *|
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|* *|
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\*===----------------------------------------------------------------------===*/
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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
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/// printInstruction - This method is automatically generated by tablegen
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/// from the instruction set description.
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static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
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{
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static const uint32_t OpInfo[] = {
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0U, // PHI
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0U, // INLINEASM
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0U, // PROLOG_LABEL
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0U, // EH_LABEL
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0U, // GC_LABEL
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0U, // KILL
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0U, // EXTRACT_SUBREG
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0U, // INSERT_SUBREG
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0U, // IMPLICIT_DEF
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0U, // SUBREG_TO_REG
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0U, // COPY_TO_REGCLASS
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2780U, // DBG_VALUE
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0U, // REG_SEQUENCE
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0U, // COPY
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2773U, // BUNDLE
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2790U, // LIFETIME_START
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2760U, // LIFETIME_END
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0U, // STACKMAP
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0U, // PATCHPOINT
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6229U, // ABS16b
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1074796629U, // ABS2d
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2149587029U, // ABS2s
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3224377429U, // ABS4h
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4200533U, // ABS4s
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1078990933U, // ABS8b
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2153781333U, // ABS8h
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3262130261U, // ABSdd
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40904813U, // ADCSwww
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40904813U, // ADCSxxx
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40903414U, // ADCwww
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40903414U, // ADCxxx
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1140855066U, // ADDHN2vvv_16b8h
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2218791194U, // ADDHN2vvv_4s2d
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3294630170U, // ADDHN2vvv_8h4s
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2149586505U, // ADDHNvvv_2s2d
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3224376905U, // ADDHNvvv_4h4s
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1078990409U, // ADDHNvvv_8b8h
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5863U, // ADDP_16B
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2148538087U, // ADDP_2D
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1075844839U, // ADDP_2S
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2150635239U, // ADDP_4H
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3225425639U, // ADDP_4S
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3226474215U, // ADDP_8B
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1080039143U, // ADDP_8H
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1081091815U, // ADDPvv_D_2D
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40904825U, // ADDSwww_asr
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40904825U, // ADDSwww_lsl
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40904825U, // ADDSwww_lsr
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40904825U, // ADDSwww_sxtb
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40904825U, // ADDSwww_sxth
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40904825U, // ADDSwww_sxtw
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40904825U, // ADDSwww_sxtx
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40904825U, // ADDSwww_uxtb
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40904825U, // ADDSwww_uxth
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40904825U, // ADDSwww_uxtw
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40904825U, // ADDSwww_uxtx
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40904825U, // ADDSxxw_sxtb
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40904825U, // ADDSxxw_sxth
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40904825U, // ADDSxxw_sxtw
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40904825U, // ADDSxxw_uxtb
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40904825U, // ADDSxxw_uxth
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40904825U, // ADDSxxw_uxtw
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40904825U, // ADDSxxx_asr
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40904825U, // ADDSxxx_lsl
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40904825U, // ADDSxxx_lsr
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40904825U, // ADDSxxx_sxtx
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40904825U, // ADDSxxx_uxtx
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7350616U, // ADDV_1b16b
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1081092440U, // ADDV_1b8b
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3228576088U, // ADDV_1h4h
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2154834264U, // ADDV_1h8h
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7350616U, // ADDV_1s4s
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40903475U, // ADDddd
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4915U, // ADDvvv_16B
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2148537139U, // ADDvvv_2D
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1075843891U, // ADDvvv_2S
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2150634291U, // ADDvvv_4H
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3225424691U, // ADDvvv_4S
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3226473267U, // ADDvvv_8B
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1080038195U, // ADDvvv_8H
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40904825U, // ADDwwi_lsl0_S
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108014267U, // ADDwwi_lsl0_cmp
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40903475U, // ADDwwi_lsl0_s
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40904825U, // ADDwwi_lsl12_S
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141568699U, // ADDwwi_lsl12_cmp
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40903475U, // ADDwwi_lsl12_s
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40903475U, // ADDwww_asr
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40903475U, // ADDwww_lsl
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40903475U, // ADDwww_lsr
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40903475U, // ADDwww_sxtb
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40903475U, // ADDwww_sxth
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40903475U, // ADDwww_sxtw
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40903475U, // ADDwww_sxtx
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40903475U, // ADDwww_uxtb
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40903475U, // ADDwww_uxth
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40903475U, // ADDwww_uxtw
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40903475U, // ADDwww_uxtx
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40904825U, // ADDxxi_lsl0_S
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108014267U, // ADDxxi_lsl0_cmp
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40903475U, // ADDxxi_lsl0_s
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40904825U, // ADDxxi_lsl12_S
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141568699U, // ADDxxi_lsl12_cmp
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40903475U, // ADDxxi_lsl12_s
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40903475U, // ADDxxw_sxtb
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40903475U, // ADDxxw_sxth
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40903475U, // ADDxxw_sxtw
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40903475U, // ADDxxw_uxtb
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40903475U, // ADDxxw_uxth
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40903475U, // ADDxxw_uxtw
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40903475U, // ADDxxx_asr
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40903475U, // ADDxxx_lsl
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40903475U, // ADDxxx_lsr
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40903475U, // ADDxxx_sxtx
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40903475U, // ADDxxx_uxtx
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0U, // ADJCALLSTACKDOWN
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0U, // ADJCALLSTACKUP
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175122258U, // ADRPxi
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208676802U, // ADRxi
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67113850U, // AESD
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67113908U, // AESE
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4864U, // AESIMC
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4872U, // AESMC
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40904831U, // ANDSwwi
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40904831U, // ANDSwww_asr
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40904831U, // ANDSwww_lsl
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40904831U, // ANDSwww_lsr
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40904831U, // ANDSwww_ror
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40904831U, // ANDSxxi
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40904831U, // ANDSxxx_asr
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40904831U, // ANDSxxx_lsl
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40904831U, // ANDSxxx_lsr
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40904831U, // ANDSxxx_ror
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4981U, // ANDvvv_16B
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3226473333U, // ANDvvv_8B
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40903541U, // ANDwwi
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40903541U, // ANDwww_asr
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40903541U, // ANDwww_lsl
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40903541U, // ANDwww_lsr
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40903541U, // ANDwww_ror
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40903541U, // ANDxxi
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40903541U, // ANDxxx_asr
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40903541U, // ANDxxx_lsl
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40903541U, // ANDxxx_lsr
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40903541U, // ANDxxx_ror
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40904704U, // ASRVwww
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40904704U, // ASRVxxx
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40904704U, // ASRwwi
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40904704U, // ASRxxi
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0U, // ATOMIC_CMP_SWAP_I16
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0U, // ATOMIC_CMP_SWAP_I32
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0U, // ATOMIC_CMP_SWAP_I64
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0U, // ATOMIC_CMP_SWAP_I8
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0U, // ATOMIC_LOAD_ADD_I16
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0U, // ATOMIC_LOAD_ADD_I32
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0U, // ATOMIC_LOAD_ADD_I64
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0U, // ATOMIC_LOAD_ADD_I8
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0U, // ATOMIC_LOAD_AND_I16
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0U, // ATOMIC_LOAD_AND_I32
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0U, // ATOMIC_LOAD_AND_I64
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0U, // ATOMIC_LOAD_AND_I8
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0U, // ATOMIC_LOAD_MAX_I16
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0U, // ATOMIC_LOAD_MAX_I32
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0U, // ATOMIC_LOAD_MAX_I64
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0U, // ATOMIC_LOAD_MAX_I8
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0U, // ATOMIC_LOAD_MIN_I16
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0U, // ATOMIC_LOAD_MIN_I32
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0U, // ATOMIC_LOAD_MIN_I64
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0U, // ATOMIC_LOAD_MIN_I8
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0U, // ATOMIC_LOAD_NAND_I16
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0U, // ATOMIC_LOAD_NAND_I32
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0U, // ATOMIC_LOAD_NAND_I64
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0U, // ATOMIC_LOAD_NAND_I8
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0U, // ATOMIC_LOAD_OR_I16
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0U, // ATOMIC_LOAD_OR_I32
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0U, // ATOMIC_LOAD_OR_I64
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0U, // ATOMIC_LOAD_OR_I8
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0U, // ATOMIC_LOAD_SUB_I16
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0U, // ATOMIC_LOAD_SUB_I32
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0U, // ATOMIC_LOAD_SUB_I64
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0U, // ATOMIC_LOAD_SUB_I8
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0U, // ATOMIC_LOAD_UMAX_I16
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0U, // ATOMIC_LOAD_UMAX_I32
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0U, // ATOMIC_LOAD_UMAX_I64
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0U, // ATOMIC_LOAD_UMAX_I8
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0U, // ATOMIC_LOAD_UMIN_I16
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0U, // ATOMIC_LOAD_UMIN_I32
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0U, // ATOMIC_LOAD_UMIN_I64
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0U, // ATOMIC_LOAD_UMIN_I8
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0U, // ATOMIC_LOAD_XOR_I16
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0U, // ATOMIC_LOAD_XOR_I32
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0U, // ATOMIC_LOAD_XOR_I64
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0U, // ATOMIC_LOAD_XOR_I8
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0U, // ATOMIC_SWAP_I16
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0U, // ATOMIC_SWAP_I32
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0U, // ATOMIC_SWAP_I64
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0U, // ATOMIC_SWAP_I8
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14550U, // ATix
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242230450U, // BFIwwii
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242230450U, // BFIxxii
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242230800U, // BFMwwii
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242230800U, // BFMxxii
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242230681U, // BFXILwwii
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242230681U, // BFXILxxii
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40904819U, // BICSwww_asr
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40904819U, // BICSwww_lsl
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40904819U, // BICSwww_lsr
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40904819U, // BICSwww_ror
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40904819U, // BICSxxx_asr
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40904819U, // BICSxxx_lsl
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40904819U, // BICSxxx_lsr
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40904819U, // BICSxxx_ror
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270537467U, // BICvi_lsl_2S
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1345327867U, // BICvi_lsl_4H
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272634619U, // BICvi_lsl_4S
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1348473595U, // BICvi_lsl_8H
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4859U, // BICvvv_16B
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3226473211U, // BICvvv_8B
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40903419U, // BICwww_asr
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40903419U, // BICwww_lsl
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40903419U, // BICwww_lsr
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40903419U, // BICwww_ror
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40903419U, // BICxxx_asr
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40903419U, // BICxxx_lsl
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40903419U, // BICxxx_lsr
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40903419U, // BICxxx_ror
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67113932U, // BIFvvv_16B
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3293582284U, // BIFvvv_8B
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67115246U, // BITvvv_16B
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3293583598U, // BITvvv_8B
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8398822U, // BLRx
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17676U, // BLimm
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8398043U, // BRKi
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8398782U, // BRx
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67114444U, // BSLvvv_16B
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3293582796U, // BSLvvv_8B
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23237U, // Bcc
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16935U, // Bimm
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309340826U, // CBNZw
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309340826U, // CBNZx
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309340797U, // CBZw
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309340797U, // CBZx
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40904290U, // CCMNwi
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40904290U, // CCMNww
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40904290U, // CCMNxi
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40904290U, // CCMNxx
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40904467U, // CCMPwi
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40904467U, // CCMPww
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40904467U, // CCMPxi
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40904467U, // CCMPxx
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8399443U, // CLREXi
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6283U, // CLS16b
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2149587083U, // CLS2s
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3224377483U, // CLS4h
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4200587U, // CLS4s
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1078990987U, // CLS8b
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2153781387U, // CLS8h
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3262130315U, // CLSww
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3262130315U, // CLSxx
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6805U, // CLZ16b
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2149587605U, // CLZ2s
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3224378005U, // CLZ4h
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4201109U, // CLZ4s
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1078991509U, // CLZ8b
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2153781909U, // CLZ8h
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3262130837U, // CLZww
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3262130837U, // CLZxx
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40904602U, // CMEQddd
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40904602U, // CMEQddi
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6042U, // CMEQvvi_16B
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2148538266U, // CMEQvvi_2D
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1075845018U, // CMEQvvi_2S
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2150635418U, // CMEQvvi_4H
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3225425818U, // CMEQvvi_4S
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3226474394U, // CMEQvvi_8B
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1080039322U, // CMEQvvi_8H
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6042U, // CMEQvvv_16B
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2148538266U, // CMEQvvv_2D
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1075845018U, // CMEQvvv_2S
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2150635418U, // CMEQvvv_4H
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3225425818U, // CMEQvvv_4S
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3226474394U, // CMEQvvv_8B
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1080039322U, // CMEQvvv_8H
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40903560U, // CMGEddd
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40903560U, // CMGEddi
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5000U, // CMGEvvi_16B
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2148537224U, // CMGEvvi_2D
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1075843976U, // CMGEvvi_2S
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2150634376U, // CMGEvvi_4H
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3225424776U, // CMGEvvi_4S
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3226473352U, // CMGEvvi_8B
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1080038280U, // CMGEvvi_8H
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5000U, // CMGEvvv_16B
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2148537224U, // CMGEvvv_2D
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1075843976U, // CMGEvvv_2S
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2150634376U, // CMGEvvv_4H
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3225424776U, // CMGEvvv_4S
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3226473352U, // CMGEvvv_8B
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1080038280U, // CMGEvvv_8H
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40904935U, // CMGTddd
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40904935U, // CMGTddi
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6375U, // CMGTvvi_16B
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2148538599U, // CMGTvvi_2D
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1075845351U, // CMGTvvi_2S
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2150635751U, // CMGTvvi_4H
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3225426151U, // CMGTvvi_4S
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3226474727U, // CMGTvvi_8B
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1080039655U, // CMGTvvi_8H
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6375U, // CMGTvvv_16B
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2148538599U, // CMGTvvv_2D
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1075845351U, // CMGTvvv_2S
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2150635751U, // CMGTvvv_4H
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3225426151U, // CMGTvvv_4S
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3226474727U, // CMGTvvv_8B
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1080039655U, // CMGTvvv_8H
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40903863U, // CMHIddd
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5303U, // CMHIvvv_16B
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2148537527U, // CMHIvvv_2D
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1075844279U, // CMHIvvv_2S
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2150634679U, // CMHIvvv_4H
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3225425079U, // CMHIvvv_4S
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3226473655U, // CMHIvvv_8B
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1080038583U, // CMHIvvv_8H
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40904837U, // CMHSddd
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6277U, // CMHSvvv_16B
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2148538501U, // CMHSvvv_2D
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1075845253U, // CMHSvvv_2S
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2150635653U, // CMHSvvv_4H
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3225426053U, // CMHSvvv_4S
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3226474629U, // CMHSvvv_8B
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1080039557U, // CMHSvvv_8H
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40903567U, // CMLEddi
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5007U, // CMLEvvi_16B
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2148537231U, // CMLEvvi_2D
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1075843983U, // CMLEvvi_2S
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2150634383U, // CMLEvvi_4H
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3225424783U, // CMLEvvi_4S
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3226473359U, // CMLEvvi_8B
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1080038287U, // CMLEvvi_8H
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40904953U, // CMLTddi
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6393U, // CMLTvvi_16B
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2148538617U, // CMLTvvi_2D
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1075845369U, // CMLTvvi_2S
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2150635769U, // CMLTvvi_4H
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3225426169U, // CMLTvvi_4S
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3226474745U, // CMLTvvi_8B
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1080039673U, // CMLTvvi_8H
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40904291U, // CMNww_asr
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40904291U, // CMNww_lsl
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40904291U, // CMNww_lsr
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40904291U, // CMNww_sxtb
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40904291U, // CMNww_sxth
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40904291U, // CMNww_sxtw
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40904291U, // CMNww_sxtx
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40904291U, // CMNww_uxtb
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40904291U, // CMNww_uxth
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40904291U, // CMNww_uxtw
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40904291U, // CMNww_uxtx
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40904291U, // CMNxw_sxtb
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40904291U, // CMNxw_sxth
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40904291U, // CMNxw_sxtw
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40904291U, // CMNxw_uxtb
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40904291U, // CMNxw_uxth
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40904291U, // CMNxw_uxtw
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40904291U, // CMNxx_asr
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40904291U, // CMNxx_lsl
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40904291U, // CMNxx_lsr
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40904291U, // CMNxx_sxtx
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40904291U, // CMNxx_uxtx
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40904468U, // CMPww_asr
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40904468U, // CMPww_lsl
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40904468U, // CMPww_lsr
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40904468U, // CMPww_sxtb
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40904468U, // CMPww_sxth
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40904468U, // CMPww_sxtw
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40904468U, // CMPww_sxtx
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40904468U, // CMPww_uxtb
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40904468U, // CMPww_uxth
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40904468U, // CMPww_uxtw
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40904468U, // CMPww_uxtx
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40904468U, // CMPxw_sxtb
|
|
40904468U, // CMPxw_sxth
|
|
40904468U, // CMPxw_sxtw
|
|
40904468U, // CMPxw_uxtb
|
|
40904468U, // CMPxw_uxth
|
|
40904468U, // CMPxw_uxtw
|
|
40904468U, // CMPxx_asr
|
|
40904468U, // CMPxx_lsl
|
|
40904468U, // CMPxx_lsr
|
|
40904468U, // CMPxx_sxtx
|
|
40904468U, // CMPxx_uxtx
|
|
40904982U, // CMTSTddd
|
|
6422U, // CMTSTvvv_16B
|
|
2148538646U, // CMTSTvvv_2D
|
|
1075845398U, // CMTSTvvv_2S
|
|
2150635798U, // CMTSTvvv_4H
|
|
3225426198U, // CMTSTvvv_4S
|
|
3226474774U, // CMTSTvvv_8B
|
|
1080039702U, // CMTSTvvv_8H
|
|
6399U, // CNT16b
|
|
1078991103U, // CNT8b
|
|
40903202U, // CRC32B_www
|
|
40903210U, // CRC32CB_www
|
|
40903691U, // CRC32CH_www
|
|
40905200U, // CRC32CW_www
|
|
40905290U, // CRC32CX_wwx
|
|
40903674U, // CRC32H_www
|
|
40905178U, // CRC32W_www
|
|
40905259U, // CRC32X_wwx
|
|
40904027U, // CSELwwwc
|
|
40904027U, // CSELxxxc
|
|
40903439U, // CSINCwwwc
|
|
40903439U, // CSINCxxxc
|
|
40905132U, // CSINVwwwc
|
|
40905132U, // CSINVxxxc
|
|
40903660U, // CSNEGwwwc
|
|
40903660U, // CSNEGxxxc
|
|
8396844U, // DCPS1i
|
|
8397209U, // DCPS2i
|
|
8397258U, // DCPS3i
|
|
25335U, // DCix
|
|
29235U, // DMBi
|
|
2805U, // DRPS
|
|
29324U, // DSBi
|
|
3254785893U, // DUP16b
|
|
3255834469U, // DUP2d
|
|
3256883045U, // DUP2s
|
|
3257931621U, // DUP4h
|
|
3258980197U, // DUP4s
|
|
3260028773U, // DUP8b
|
|
3261077349U, // DUP8h
|
|
2147489637U, // DUPELT16b
|
|
3222280037U, // DUPELT2d
|
|
2103141U, // DUPELT2s
|
|
1076893541U, // DUPELT4h
|
|
4200293U, // DUPELT4s
|
|
2152732517U, // DUPELT8b
|
|
1080039269U, // DUPELT8h
|
|
2154833765U, // DUPbv_B
|
|
3228575589U, // DUPdv_D
|
|
1081091941U, // DUPhv_H
|
|
7350117U, // DUPsv_S
|
|
40904296U, // EONwww_asr
|
|
40904296U, // EONwww_lsl
|
|
40904296U, // EONwww_lsr
|
|
40904296U, // EONwww_ror
|
|
40904296U, // EONxxx_asr
|
|
40904296U, // EONxxx_lsl
|
|
40904296U, // EONxxx_lsr
|
|
40904296U, // EONxxx_ror
|
|
6129U, // EORvvv_16B
|
|
3226474481U, // EORvvv_8B
|
|
40904689U, // EORwwi
|
|
40904689U, // EORwww_asr
|
|
40904689U, // EORwww_lsl
|
|
40904689U, // EORwww_lsr
|
|
40904689U, // EORwww_ror
|
|
40904689U, // EORxxi
|
|
40904689U, // EORxxx_asr
|
|
40904689U, // EORxxx_lsl
|
|
40904689U, // EORxxx_lsr
|
|
40904689U, // EORxxx_ror
|
|
2810U, // ERET
|
|
40904736U, // EXTRwwwi
|
|
40904736U, // EXTRxxxi
|
|
6435U, // EXTvvvi_16b
|
|
3226474787U, // EXTvvvi_8b
|
|
0U, // F128CSEL
|
|
40903456U, // FABDddd
|
|
40903456U, // FABDsss
|
|
2148537120U, // FABDvvv_2D
|
|
1075843872U, // FABDvvv_2S
|
|
3225424672U, // FABDvvv_4S
|
|
1074796628U, // FABS2d
|
|
2149587028U, // FABS2s
|
|
4200532U, // FABS4s
|
|
3262130260U, // FABSdd
|
|
3262130260U, // FABSss
|
|
40903552U, // FACGEddd
|
|
40903552U, // FACGEsss
|
|
2148537216U, // FACGEvvv_2D
|
|
1075843968U, // FACGEvvv_2S
|
|
3225424768U, // FACGEvvv_4S
|
|
40904927U, // FACGTddd
|
|
40904927U, // FACGTsss
|
|
2148538591U, // FACGTvvv_2D
|
|
1075845343U, // FACGTvvv_2S
|
|
3225426143U, // FACGTvvv_4S
|
|
2148538086U, // FADDP_2D
|
|
1075844838U, // FADDP_2S
|
|
3225425638U, // FADDP_4S
|
|
1081091814U, // FADDPvv_D_2D
|
|
2154833638U, // FADDPvv_S_2S
|
|
40903474U, // FADDddd
|
|
40903474U, // FADDsss
|
|
2148537138U, // FADDvvv_2D
|
|
1075843890U, // FADDvvv_2S
|
|
3225424690U, // FADDvvv_4S
|
|
40903589U, // FCCMPEdd
|
|
40903589U, // FCCMPEss
|
|
40904466U, // FCCMPdd
|
|
40904466U, // FCCMPss
|
|
40904601U, // FCMEQZddi
|
|
40904601U, // FCMEQZssi
|
|
40904601U, // FCMEQddd
|
|
40904601U, // FCMEQsss
|
|
2148538265U, // FCMEQvvi_2D
|
|
1075845017U, // FCMEQvvi_2S
|
|
3225425817U, // FCMEQvvi_4S
|
|
2148538265U, // FCMEQvvv_2D
|
|
1075845017U, // FCMEQvvv_2S
|
|
3225425817U, // FCMEQvvv_4S
|
|
40903559U, // FCMGEZddi
|
|
40903559U, // FCMGEZssi
|
|
40903559U, // FCMGEddd
|
|
40903559U, // FCMGEsss
|
|
2148537223U, // FCMGEvvi_2D
|
|
1075843975U, // FCMGEvvi_2S
|
|
3225424775U, // FCMGEvvi_4S
|
|
2148537223U, // FCMGEvvv_2D
|
|
1075843975U, // FCMGEvvv_2S
|
|
3225424775U, // FCMGEvvv_4S
|
|
40904934U, // FCMGTZddi
|
|
40904934U, // FCMGTZssi
|
|
40904934U, // FCMGTddd
|
|
40904934U, // FCMGTsss
|
|
2148538598U, // FCMGTvvi_2D
|
|
1075845350U, // FCMGTvvi_2S
|
|
3225426150U, // FCMGTvvi_4S
|
|
2148538598U, // FCMGTvvv_2D
|
|
1075845350U, // FCMGTvvv_2S
|
|
3225426150U, // FCMGTvvv_4S
|
|
40903566U, // FCMLEZddi
|
|
40903566U, // FCMLEZssi
|
|
2148537230U, // FCMLEvvi_2D
|
|
1075843982U, // FCMLEvvi_2S
|
|
3225424782U, // FCMLEvvi_4S
|
|
40904952U, // FCMLTZddi
|
|
40904952U, // FCMLTZssi
|
|
2148538616U, // FCMLTvvi_2D
|
|
1075845368U, // FCMLTvvi_2S
|
|
3225426168U, // FCMLTvvi_4S
|
|
3262129945U, // FCMPdd_quiet
|
|
3262129069U, // FCMPdd_sig
|
|
342894361U, // FCMPdi_quiet
|
|
342893485U, // FCMPdi_sig
|
|
342894361U, // FCMPsi_quiet
|
|
342893485U, // FCMPsi_sig
|
|
3262129945U, // FCMPss_quiet
|
|
3262129069U, // FCMPss_sig
|
|
40904026U, // FCSELdddc
|
|
40904026U, // FCSELsssc
|
|
1074796620U, // FCVTAS_2d
|
|
2149587020U, // FCVTAS_2s
|
|
4200524U, // FCVTAS_4s
|
|
3262130252U, // FCVTASdd
|
|
3262130252U, // FCVTASss
|
|
3262130252U, // FCVTASwd
|
|
3262130252U, // FCVTASws
|
|
3262130252U, // FCVTASxd
|
|
3262130252U, // FCVTASxs
|
|
1074796840U, // FCVTAU_2d
|
|
2149587240U, // FCVTAU_2s
|
|
4200744U, // FCVTAU_4s
|
|
3262130472U, // FCVTAUdd
|
|
3262130472U, // FCVTAUss
|
|
3262130472U, // FCVTAUwd
|
|
3262130472U, // FCVTAUws
|
|
3262130472U, // FCVTAUxd
|
|
3262130472U, // FCVTAUxs
|
|
2148537838U, // FCVTL2s2d
|
|
3225425390U, // FCVTL4h4s
|
|
1052936U, // FCVTL4s2d
|
|
2151682312U, // FCVTL8h4s
|
|
1074796694U, // FCVTMS_2d
|
|
2149587094U, // FCVTMS_2s
|
|
4200598U, // FCVTMS_4s
|
|
3262130326U, // FCVTMSdd
|
|
3262130326U, // FCVTMSss
|
|
3262130326U, // FCVTMSwd
|
|
3262130326U, // FCVTMSws
|
|
3262130326U, // FCVTMSxd
|
|
3262130326U, // FCVTMSxs
|
|
1074796856U, // FCVTMU_2d
|
|
2149587256U, // FCVTMU_2s
|
|
4200760U, // FCVTMU_4s
|
|
3262130488U, // FCVTMUdd
|
|
3262130488U, // FCVTMUss
|
|
3262130488U, // FCVTMUwd
|
|
3262130488U, // FCVTMUws
|
|
3262130488U, // FCVTMUxd
|
|
3262130488U, // FCVTMUxs
|
|
1075844764U, // FCVTN2d2s
|
|
1145049422U, // FCVTN2d4s
|
|
3151516U, // FCVTN4s4h
|
|
73404750U, // FCVTN4s8h
|
|
1074796707U, // FCVTNS_2d
|
|
2149587107U, // FCVTNS_2s
|
|
4200611U, // FCVTNS_4s
|
|
3262130339U, // FCVTNSdd
|
|
3262130339U, // FCVTNSss
|
|
3262130339U, // FCVTNSwd
|
|
3262130339U, // FCVTNSws
|
|
3262130339U, // FCVTNSxd
|
|
3262130339U, // FCVTNSxs
|
|
1074796864U, // FCVTNU_2d
|
|
2149587264U, // FCVTNU_2s
|
|
4200768U, // FCVTNU_4s
|
|
3262130496U, // FCVTNUdd
|
|
3262130496U, // FCVTNUss
|
|
3262130496U, // FCVTNUwd
|
|
3262130496U, // FCVTNUws
|
|
3262130496U, // FCVTNUxd
|
|
3262130496U, // FCVTNUxs
|
|
1074796723U, // FCVTPS_2d
|
|
2149587123U, // FCVTPS_2s
|
|
4200627U, // FCVTPS_4s
|
|
3262130355U, // FCVTPSdd
|
|
3262130355U, // FCVTPSss
|
|
3262130355U, // FCVTPSwd
|
|
3262130355U, // FCVTPSws
|
|
3262130355U, // FCVTPSxd
|
|
3262130355U, // FCVTPSxs
|
|
1074796872U, // FCVTPU_2d
|
|
2149587272U, // FCVTPU_2s
|
|
4200776U, // FCVTPU_4s
|
|
3262130504U, // FCVTPUdd
|
|
3262130504U, // FCVTPUss
|
|
3262130504U, // FCVTPUwd
|
|
3262130504U, // FCVTPUws
|
|
3262130504U, // FCVTPUxd
|
|
3262130504U, // FCVTPUxs
|
|
3262129879U, // FCVTXN
|
|
1075844823U, // FCVTXN2d2s
|
|
1145049476U, // FCVTXN2d4s
|
|
1074796750U, // FCVTZS_2d
|
|
2149587150U, // FCVTZS_2s
|
|
4200654U, // FCVTZS_4s
|
|
40904910U, // FCVTZS_Nddi
|
|
40904910U, // FCVTZS_Nssi
|
|
3262130382U, // FCVTZSdd
|
|
3262130382U, // FCVTZSss
|
|
3262130382U, // FCVTZSwd
|
|
40904910U, // FCVTZSwdi
|
|
3262130382U, // FCVTZSws
|
|
40904910U, // FCVTZSwsi
|
|
3262130382U, // FCVTZSxd
|
|
40904910U, // FCVTZSxdi
|
|
3262130382U, // FCVTZSxs
|
|
40904910U, // FCVTZSxsi
|
|
1074796880U, // FCVTZU_2d
|
|
2149587280U, // FCVTZU_2s
|
|
4200784U, // FCVTZU_4s
|
|
40905040U, // FCVTZU_Nddi
|
|
40905040U, // FCVTZU_Nssi
|
|
3262130512U, // FCVTZUdd
|
|
3262130512U, // FCVTZUss
|
|
3262130512U, // FCVTZUwd
|
|
40905040U, // FCVTZUwdi
|
|
3262130512U, // FCVTZUws
|
|
40905040U, // FCVTZUwsi
|
|
3262130512U, // FCVTZUxd
|
|
40905040U, // FCVTZUxdi
|
|
3262130512U, // FCVTZUxs
|
|
40905040U, // FCVTZUxsi
|
|
3262130461U, // FCVTdh
|
|
3262130461U, // FCVTds
|
|
3262130461U, // FCVThd
|
|
3262130461U, // FCVThs
|
|
3262130461U, // FCVTsd
|
|
3262130461U, // FCVTsh
|
|
40905059U, // FDIVddd
|
|
40905059U, // FDIVsss
|
|
2148538723U, // FDIVvvv_2D
|
|
1075845475U, // FDIVvvv_2S
|
|
3225426275U, // FDIVvvv_4S
|
|
40903510U, // FMADDdddd
|
|
40903510U, // FMADDssss
|
|
1081091880U, // FMAXNMPvv_D_2D
|
|
2154833704U, // FMAXNMPvv_S_2S
|
|
2148538152U, // FMAXNMPvvv_2D
|
|
1075844904U, // FMAXNMPvvv_2S
|
|
3225425704U, // FMAXNMPvvv_4S
|
|
7350670U, // FMAXNMV_1s4s
|
|
40904233U, // FMAXNMddd
|
|
40904233U, // FMAXNMsss
|
|
2148537897U, // FMAXNMvvv_2D
|
|
1075844649U, // FMAXNMvvv_2S
|
|
3225425449U, // FMAXNMvvv_4S
|
|
1081091953U, // FMAXPvv_D_2D
|
|
2154833777U, // FMAXPvv_S_2S
|
|
2148538225U, // FMAXPvvv_2D
|
|
1075844977U, // FMAXPvvv_2S
|
|
3225425777U, // FMAXPvvv_4S
|
|
7350725U, // FMAXV_1s4s
|
|
40905267U, // FMAXddd
|
|
40905267U, // FMAXsss
|
|
2148538931U, // FMAXvvv_2D
|
|
1075845683U, // FMAXvvv_2S
|
|
3225426483U, // FMAXvvv_4S
|
|
1081091871U, // FMINNMPvv_D_2D
|
|
2154833695U, // FMINNMPvv_S_2S
|
|
2148538143U, // FMINNMPvvv_2D
|
|
1075844895U, // FMINNMPvvv_2S
|
|
3225425695U, // FMINNMPvvv_4S
|
|
7350661U, // FMINNMV_1s4s
|
|
40904225U, // FMINNMddd
|
|
40904225U, // FMINNMsss
|
|
2148537889U, // FMINNMvvv_2D
|
|
1075844641U, // FMINNMvvv_2S
|
|
3225425441U, // FMINNMvvv_4S
|
|
1081091895U, // FMINPvv_D_2D
|
|
2154833719U, // FMINPvv_S_2S
|
|
2148538167U, // FMINPvvv_2D
|
|
1075844919U, // FMINPvvv_2S
|
|
3225425719U, // FMINPvvv_4S
|
|
7350679U, // FMINV_1s4s
|
|
40904272U, // FMINddd
|
|
40904272U, // FMINsss
|
|
2148537936U, // FMINvvv_2D
|
|
1075844688U, // FMINvvv_2S
|
|
3225425488U, // FMINvvv_4S
|
|
242229754U, // FMLAddv_2D
|
|
242229754U, // FMLAssv_4S
|
|
2215645690U, // FMLAvve_2d2d
|
|
1142952442U, // FMLAvve_2s4s
|
|
3292533242U, // FMLAvve_4s4s
|
|
2215645690U, // FMLAvvv_2D
|
|
1142952442U, // FMLAvvv_2S
|
|
3292533242U, // FMLAvvv_4S
|
|
242231440U, // FMLSddv_2D
|
|
242231440U, // FMLSssv_4S
|
|
2215647376U, // FMLSvve_2d2d
|
|
1142954128U, // FMLSvve_2s4s
|
|
3292534928U, // FMLSvve_4s4s
|
|
2215647376U, // FMLSvvv_2D
|
|
1142954128U, // FMLSvvv_2S
|
|
3292534928U, // FMLSvvv_4S
|
|
3262130611U, // FMOVdd
|
|
376449459U, // FMOVdi
|
|
3262130611U, // FMOVdx
|
|
376449459U, // FMOVsi
|
|
3262130611U, // FMOVss
|
|
3262130611U, // FMOVsw
|
|
370153907U, // FMOVvi_2D
|
|
371202483U, // FMOVvi_2S
|
|
373299635U, // FMOVvi_4S
|
|
412096947U, // FMOVvx
|
|
3262130611U, // FMOVws
|
|
3262130611U, // FMOVxd
|
|
3228576179U, // FMOVxv
|
|
40903373U, // FMSUBdddd
|
|
40903373U, // FMSUBssss
|
|
40905318U, // FMULXddd
|
|
40905318U, // FMULXddv_2D
|
|
40905318U, // FMULXsss
|
|
40905318U, // FMULXssv_4S
|
|
2148538982U, // FMULXve_2d2d
|
|
1075845734U, // FMULXve_2s4s
|
|
3225426534U, // FMULXve_4s4s
|
|
2148538982U, // FMULXvvv_2D
|
|
1075845734U, // FMULXvvv_2S
|
|
3225426534U, // FMULXvvv_4S
|
|
40904181U, // FMULddd
|
|
40904181U, // FMULddv_2D
|
|
40904181U, // FMULsss
|
|
40904181U, // FMULssv_4S
|
|
2148537845U, // FMULve_2d2d
|
|
1075844597U, // FMULve_2s4s
|
|
3225425397U, // FMULve_4s4s
|
|
2148537845U, // FMULvvv_2D
|
|
1075844597U, // FMULvvv_2S
|
|
3225425397U, // FMULvvv_4S
|
|
1074795487U, // FNEG2d
|
|
2149585887U, // FNEG2s
|
|
4199391U, // FNEG4s
|
|
3262129119U, // FNEGdd
|
|
3262129119U, // FNEGss
|
|
40903517U, // FNMADDdddd
|
|
40903517U, // FNMADDssss
|
|
40903380U, // FNMSUBdddd
|
|
40903380U, // FNMSUBssss
|
|
40904187U, // FNMULddd
|
|
40904187U, // FNMULsss
|
|
1074795413U, // FRECPE_2d
|
|
2149585813U, // FRECPE_2s
|
|
4199317U, // FRECPE_4s
|
|
3262129045U, // FRECPEdd
|
|
3262129045U, // FRECPEss
|
|
40904875U, // FRECPSddd
|
|
40904875U, // FRECPSsss
|
|
2148538539U, // FRECPSvvv_2D
|
|
1075845291U, // FRECPSvvv_2S
|
|
3225426091U, // FRECPSvvv_4S
|
|
3262130797U, // FRECPXdd
|
|
3262130797U, // FRECPXss
|
|
1074795034U, // FRINTA_2d
|
|
2149585434U, // FRINTA_2s
|
|
4198938U, // FRINTA_4s
|
|
3262128666U, // FRINTAdd
|
|
3262128666U, // FRINTAss
|
|
1074795725U, // FRINTI_2d
|
|
2149586125U, // FRINTI_2s
|
|
4199629U, // FRINTI_4s
|
|
3262129357U, // FRINTIdd
|
|
3262129357U, // FRINTIss
|
|
1074796081U, // FRINTM_2d
|
|
2149586481U, // FRINTM_2s
|
|
4199985U, // FRINTM_4s
|
|
3262129713U, // FRINTMdd
|
|
3262129713U, // FRINTMss
|
|
1074796180U, // FRINTN_2d
|
|
2149586580U, // FRINTN_2s
|
|
4200084U, // FRINTN_4s
|
|
3262129812U, // FRINTNdd
|
|
3262129812U, // FRINTNss
|
|
1074796376U, // FRINTP_2d
|
|
2149586776U, // FRINTP_2s
|
|
4200280U, // FRINTP_4s
|
|
3262130008U, // FRINTPdd
|
|
3262130008U, // FRINTPss
|
|
1074797173U, // FRINTX_2d
|
|
2149587573U, // FRINTX_2s
|
|
4201077U, // FRINTX_4s
|
|
3262130805U, // FRINTXdd
|
|
3262130805U, // FRINTXss
|
|
1074797222U, // FRINTZ_2d
|
|
2149587622U, // FRINTZ_2s
|
|
4201126U, // FRINTZ_4s
|
|
3262130854U, // FRINTZdd
|
|
3262130854U, // FRINTZss
|
|
1074795450U, // FRSQRTE_2d
|
|
2149585850U, // FRSQRTE_2s
|
|
4199354U, // FRSQRTE_4s
|
|
3262129082U, // FRSQRTEdd
|
|
3262129082U, // FRSQRTEss
|
|
40904896U, // FRSQRTSddd
|
|
40904896U, // FRSQRTSsss
|
|
2148538560U, // FRSQRTSvvv_2D
|
|
1075845312U, // FRSQRTSvvv_2S
|
|
3225426112U, // FRSQRTSvvv_4S
|
|
1074796815U, // FSQRT_2d
|
|
2149587215U, // FSQRT_2s
|
|
4200719U, // FSQRT_4s
|
|
3262130447U, // FSQRTdd
|
|
3262130447U, // FSQRTss
|
|
40903353U, // FSUBddd
|
|
40903353U, // FSUBsss
|
|
2148537017U, // FSUBvvv_2D
|
|
1075843769U, // FSUBvvv_2S
|
|
3225424569U, // FSUBvvv_4S
|
|
8399108U, // HINTi
|
|
8399091U, // HLTi
|
|
8397590U, // HVCi
|
|
8422140U, // ICi
|
|
3262153468U, // ICix
|
|
2225084574U, // INSELb
|
|
2593134750U, // INSELd
|
|
1152391326U, // INSELh
|
|
79698078U, // INSELs
|
|
3466598558U, // INSbw
|
|
3666876574U, // INSdx
|
|
3467647134U, // INShw
|
|
3468695710U, // INSsw
|
|
37521U, // ISBi
|
|
13672469U, // LD1LN_B
|
|
13676565U, // LD1LN_D
|
|
13680661U, // LD1LN_H
|
|
13684757U, // LD1LN_S
|
|
14721045U, // LD1LN_WB_B_fixed
|
|
14721045U, // LD1LN_WB_B_register
|
|
14725141U, // LD1LN_WB_D_fixed
|
|
14725141U, // LD1LN_WB_D_register
|
|
14729237U, // LD1LN_WB_H_fixed
|
|
14729237U, // LD1LN_WB_H_register
|
|
14733333U, // LD1LN_WB_S_fixed
|
|
14733333U, // LD1LN_WB_S_register
|
|
15787936U, // LD1R_16B
|
|
15792032U, // LD1R_1D
|
|
15796128U, // LD1R_2D
|
|
15800224U, // LD1R_2S
|
|
15804320U, // LD1R_4H
|
|
15808416U, // LD1R_4S
|
|
15812512U, // LD1R_8B
|
|
15816608U, // LD1R_8H
|
|
16836512U, // LD1R_WB_16B_fixed
|
|
16836512U, // LD1R_WB_16B_register
|
|
16840608U, // LD1R_WB_1D_fixed
|
|
16840608U, // LD1R_WB_1D_register
|
|
16844704U, // LD1R_WB_2D_fixed
|
|
16844704U, // LD1R_WB_2D_register
|
|
16848800U, // LD1R_WB_2S_fixed
|
|
16848800U, // LD1R_WB_2S_register
|
|
16852896U, // LD1R_WB_4H_fixed
|
|
16852896U, // LD1R_WB_4H_register
|
|
16856992U, // LD1R_WB_4S_fixed
|
|
16856992U, // LD1R_WB_4S_register
|
|
16861088U, // LD1R_WB_8B_fixed
|
|
16861088U, // LD1R_WB_8B_register
|
|
16865184U, // LD1R_WB_8H_fixed
|
|
16865184U, // LD1R_WB_8H_register
|
|
16834581U, // LD1WB_16B_fixed
|
|
16834581U, // LD1WB_16B_register
|
|
16838677U, // LD1WB_1D_fixed
|
|
16838677U, // LD1WB_1D_register
|
|
16842773U, // LD1WB_2D_fixed
|
|
16842773U, // LD1WB_2D_register
|
|
16846869U, // LD1WB_2S_fixed
|
|
16846869U, // LD1WB_2S_register
|
|
16850965U, // LD1WB_4H_fixed
|
|
16850965U, // LD1WB_4H_register
|
|
16855061U, // LD1WB_4S_fixed
|
|
16855061U, // LD1WB_4S_register
|
|
16859157U, // LD1WB_8B_fixed
|
|
16859157U, // LD1WB_8B_register
|
|
16863253U, // LD1WB_8H_fixed
|
|
16863253U, // LD1WB_8H_register
|
|
15786005U, // LD1_16B
|
|
15790101U, // LD1_1D
|
|
15794197U, // LD1_2D
|
|
15798293U, // LD1_2S
|
|
15802389U, // LD1_4H
|
|
15806485U, // LD1_4S
|
|
15810581U, // LD1_8B
|
|
15814677U, // LD1_8H
|
|
16867349U, // LD1x2WB_16B_fixed
|
|
16867349U, // LD1x2WB_16B_register
|
|
16871445U, // LD1x2WB_1D_fixed
|
|
16871445U, // LD1x2WB_1D_register
|
|
16875541U, // LD1x2WB_2D_fixed
|
|
16875541U, // LD1x2WB_2D_register
|
|
16879637U, // LD1x2WB_2S_fixed
|
|
16879637U, // LD1x2WB_2S_register
|
|
16883733U, // LD1x2WB_4H_fixed
|
|
16883733U, // LD1x2WB_4H_register
|
|
16887829U, // LD1x2WB_4S_fixed
|
|
16887829U, // LD1x2WB_4S_register
|
|
16891925U, // LD1x2WB_8B_fixed
|
|
16891925U, // LD1x2WB_8B_register
|
|
16896021U, // LD1x2WB_8H_fixed
|
|
16896021U, // LD1x2WB_8H_register
|
|
15818773U, // LD1x2_16B
|
|
15822869U, // LD1x2_1D
|
|
15826965U, // LD1x2_2D
|
|
15831061U, // LD1x2_2S
|
|
15835157U, // LD1x2_4H
|
|
15839253U, // LD1x2_4S
|
|
15843349U, // LD1x2_8B
|
|
15847445U, // LD1x2_8H
|
|
16900117U, // LD1x3WB_16B_fixed
|
|
16900117U, // LD1x3WB_16B_register
|
|
16904213U, // LD1x3WB_1D_fixed
|
|
16904213U, // LD1x3WB_1D_register
|
|
16908309U, // LD1x3WB_2D_fixed
|
|
16908309U, // LD1x3WB_2D_register
|
|
16912405U, // LD1x3WB_2S_fixed
|
|
16912405U, // LD1x3WB_2S_register
|
|
16916501U, // LD1x3WB_4H_fixed
|
|
16916501U, // LD1x3WB_4H_register
|
|
16920597U, // LD1x3WB_4S_fixed
|
|
16920597U, // LD1x3WB_4S_register
|
|
16924693U, // LD1x3WB_8B_fixed
|
|
16924693U, // LD1x3WB_8B_register
|
|
16928789U, // LD1x3WB_8H_fixed
|
|
16928789U, // LD1x3WB_8H_register
|
|
15851541U, // LD1x3_16B
|
|
15855637U, // LD1x3_1D
|
|
15859733U, // LD1x3_2D
|
|
15863829U, // LD1x3_2S
|
|
15867925U, // LD1x3_4H
|
|
15872021U, // LD1x3_4S
|
|
15876117U, // LD1x3_8B
|
|
15880213U, // LD1x3_8H
|
|
16932885U, // LD1x4WB_16B_fixed
|
|
16932885U, // LD1x4WB_16B_register
|
|
16936981U, // LD1x4WB_1D_fixed
|
|
16936981U, // LD1x4WB_1D_register
|
|
16941077U, // LD1x4WB_2D_fixed
|
|
16941077U, // LD1x4WB_2D_register
|
|
16945173U, // LD1x4WB_2S_fixed
|
|
16945173U, // LD1x4WB_2S_register
|
|
16949269U, // LD1x4WB_4H_fixed
|
|
16949269U, // LD1x4WB_4H_register
|
|
16953365U, // LD1x4WB_4S_fixed
|
|
16953365U, // LD1x4WB_4S_register
|
|
16957461U, // LD1x4WB_8B_fixed
|
|
16957461U, // LD1x4WB_8B_register
|
|
16961557U, // LD1x4WB_8H_fixed
|
|
16961557U, // LD1x4WB_8H_register
|
|
15884309U, // LD1x4_16B
|
|
15888405U, // LD1x4_1D
|
|
15892501U, // LD1x4_2D
|
|
15896597U, // LD1x4_2S
|
|
15900693U, // LD1x4_4H
|
|
15904789U, // LD1x4_4S
|
|
15908885U, // LD1x4_8B
|
|
15912981U, // LD1x4_8H
|
|
13819987U, // LD2LN_B
|
|
13824083U, // LD2LN_D
|
|
13828179U, // LD2LN_H
|
|
13832275U, // LD2LN_S
|
|
14868563U, // LD2LN_WB_B_fixed
|
|
14868563U, // LD2LN_WB_B_register
|
|
14872659U, // LD2LN_WB_D_fixed
|
|
14872659U, // LD2LN_WB_D_register
|
|
14876755U, // LD2LN_WB_H_fixed
|
|
14876755U, // LD2LN_WB_H_register
|
|
14880851U, // LD2LN_WB_S_fixed
|
|
14880851U, // LD2LN_WB_S_register
|
|
15820710U, // LD2R_16B
|
|
15824806U, // LD2R_1D
|
|
15828902U, // LD2R_2D
|
|
15832998U, // LD2R_2S
|
|
15837094U, // LD2R_4H
|
|
15841190U, // LD2R_4S
|
|
15845286U, // LD2R_8B
|
|
15849382U, // LD2R_8H
|
|
16869286U, // LD2R_WB_16B_fixed
|
|
16869286U, // LD2R_WB_16B_register
|
|
16873382U, // LD2R_WB_1D_fixed
|
|
16873382U, // LD2R_WB_1D_register
|
|
16877478U, // LD2R_WB_2D_fixed
|
|
16877478U, // LD2R_WB_2D_register
|
|
16881574U, // LD2R_WB_2S_fixed
|
|
16881574U, // LD2R_WB_2S_register
|
|
16885670U, // LD2R_WB_4H_fixed
|
|
16885670U, // LD2R_WB_4H_register
|
|
16889766U, // LD2R_WB_4S_fixed
|
|
16889766U, // LD2R_WB_4S_register
|
|
16893862U, // LD2R_WB_8B_fixed
|
|
16893862U, // LD2R_WB_8B_register
|
|
16897958U, // LD2R_WB_8H_fixed
|
|
16897958U, // LD2R_WB_8H_register
|
|
16867411U, // LD2WB_16B_fixed
|
|
16867411U, // LD2WB_16B_register
|
|
16875603U, // LD2WB_2D_fixed
|
|
16875603U, // LD2WB_2D_register
|
|
16879699U, // LD2WB_2S_fixed
|
|
16879699U, // LD2WB_2S_register
|
|
16883795U, // LD2WB_4H_fixed
|
|
16883795U, // LD2WB_4H_register
|
|
16887891U, // LD2WB_4S_fixed
|
|
16887891U, // LD2WB_4S_register
|
|
16891987U, // LD2WB_8B_fixed
|
|
16891987U, // LD2WB_8B_register
|
|
16896083U, // LD2WB_8H_fixed
|
|
16896083U, // LD2WB_8H_register
|
|
15818835U, // LD2_16B
|
|
15827027U, // LD2_2D
|
|
15831123U, // LD2_2S
|
|
15835219U, // LD2_4H
|
|
15839315U, // LD2_4S
|
|
15843411U, // LD2_8B
|
|
15847507U, // LD2_8H
|
|
13836741U, // LD3LN_B
|
|
13840837U, // LD3LN_D
|
|
13844933U, // LD3LN_H
|
|
13849029U, // LD3LN_S
|
|
14885317U, // LD3LN_WB_B_fixed
|
|
14885317U, // LD3LN_WB_B_register
|
|
14889413U, // LD3LN_WB_D_fixed
|
|
14889413U, // LD3LN_WB_D_register
|
|
14893509U, // LD3LN_WB_H_fixed
|
|
14893509U, // LD3LN_WB_H_register
|
|
14897605U, // LD3LN_WB_S_fixed
|
|
14897605U, // LD3LN_WB_S_register
|
|
15853484U, // LD3R_16B
|
|
15857580U, // LD3R_1D
|
|
15861676U, // LD3R_2D
|
|
15865772U, // LD3R_2S
|
|
15869868U, // LD3R_4H
|
|
15873964U, // LD3R_4S
|
|
15878060U, // LD3R_8B
|
|
15882156U, // LD3R_8H
|
|
16902060U, // LD3R_WB_16B_fixed
|
|
16902060U, // LD3R_WB_16B_register
|
|
16906156U, // LD3R_WB_1D_fixed
|
|
16906156U, // LD3R_WB_1D_register
|
|
16910252U, // LD3R_WB_2D_fixed
|
|
16910252U, // LD3R_WB_2D_register
|
|
16914348U, // LD3R_WB_2S_fixed
|
|
16914348U, // LD3R_WB_2S_register
|
|
16918444U, // LD3R_WB_4H_fixed
|
|
16918444U, // LD3R_WB_4H_register
|
|
16922540U, // LD3R_WB_4S_fixed
|
|
16922540U, // LD3R_WB_4S_register
|
|
16926636U, // LD3R_WB_8B_fixed
|
|
16926636U, // LD3R_WB_8B_register
|
|
16930732U, // LD3R_WB_8H_fixed
|
|
16930732U, // LD3R_WB_8H_register
|
|
16900549U, // LD3WB_16B_fixed
|
|
16900549U, // LD3WB_16B_register
|
|
16908741U, // LD3WB_2D_fixed
|
|
16908741U, // LD3WB_2D_register
|
|
16912837U, // LD3WB_2S_fixed
|
|
16912837U, // LD3WB_2S_register
|
|
16916933U, // LD3WB_4H_fixed
|
|
16916933U, // LD3WB_4H_register
|
|
16921029U, // LD3WB_4S_fixed
|
|
16921029U, // LD3WB_4S_register
|
|
16925125U, // LD3WB_8B_fixed
|
|
16925125U, // LD3WB_8B_register
|
|
16929221U, // LD3WB_8H_fixed
|
|
16929221U, // LD3WB_8H_register
|
|
15851973U, // LD3_16B
|
|
15860165U, // LD3_2D
|
|
15864261U, // LD3_2S
|
|
15868357U, // LD3_4H
|
|
15872453U, // LD3_4S
|
|
15876549U, // LD3_8B
|
|
15880645U, // LD3_8H
|
|
13853149U, // LD4LN_B
|
|
13857245U, // LD4LN_D
|
|
13861341U, // LD4LN_H
|
|
13865437U, // LD4LN_S
|
|
14901725U, // LD4LN_WB_B_fixed
|
|
14901725U, // LD4LN_WB_B_register
|
|
14905821U, // LD4LN_WB_D_fixed
|
|
14905821U, // LD4LN_WB_D_register
|
|
14909917U, // LD4LN_WB_H_fixed
|
|
14909917U, // LD4LN_WB_H_register
|
|
14914013U, // LD4LN_WB_S_fixed
|
|
14914013U, // LD4LN_WB_S_register
|
|
15886258U, // LD4R_16B
|
|
15890354U, // LD4R_1D
|
|
15894450U, // LD4R_2D
|
|
15898546U, // LD4R_2S
|
|
15902642U, // LD4R_4H
|
|
15906738U, // LD4R_4S
|
|
15910834U, // LD4R_8B
|
|
15914930U, // LD4R_8H
|
|
16934834U, // LD4R_WB_16B_fixed
|
|
16934834U, // LD4R_WB_16B_register
|
|
16938930U, // LD4R_WB_1D_fixed
|
|
16938930U, // LD4R_WB_1D_register
|
|
16943026U, // LD4R_WB_2D_fixed
|
|
16943026U, // LD4R_WB_2D_register
|
|
16947122U, // LD4R_WB_2S_fixed
|
|
16947122U, // LD4R_WB_2S_register
|
|
16951218U, // LD4R_WB_4H_fixed
|
|
16951218U, // LD4R_WB_4H_register
|
|
16955314U, // LD4R_WB_4S_fixed
|
|
16955314U, // LD4R_WB_4S_register
|
|
16959410U, // LD4R_WB_8B_fixed
|
|
16959410U, // LD4R_WB_8B_register
|
|
16963506U, // LD4R_WB_8H_fixed
|
|
16963506U, // LD4R_WB_8H_register
|
|
16933341U, // LD4WB_16B_fixed
|
|
16933341U, // LD4WB_16B_register
|
|
16941533U, // LD4WB_2D_fixed
|
|
16941533U, // LD4WB_2D_register
|
|
16945629U, // LD4WB_2S_fixed
|
|
16945629U, // LD4WB_2S_register
|
|
16949725U, // LD4WB_4H_fixed
|
|
16949725U, // LD4WB_4H_register
|
|
16953821U, // LD4WB_4S_fixed
|
|
16953821U, // LD4WB_4S_register
|
|
16957917U, // LD4WB_8B_fixed
|
|
16957917U, // LD4WB_8B_register
|
|
16962013U, // LD4WB_8H_fixed
|
|
16962013U, // LD4WB_8H_register
|
|
15884765U, // LD4_16B
|
|
15892957U, // LD4_2D
|
|
15897053U, // LD4_2S
|
|
15901149U, // LD4_4H
|
|
15905245U, // LD4_4S
|
|
15909341U, // LD4_8B
|
|
15913437U, // LD4_8H
|
|
51388984U, // LDAR_byte
|
|
51390392U, // LDAR_dword
|
|
51389493U, // LDAR_hword
|
|
51390392U, // LDAR_word
|
|
1114646378U, // LDAXP_dword
|
|
1114646378U, // LDAXP_word
|
|
51389038U, // LDAXR_byte
|
|
51390514U, // LDAXR_dword
|
|
51389547U, // LDAXR_hword
|
|
51390514U, // LDAXR_word
|
|
1114647047U, // LDPSWx
|
|
1114647047U, // LDPSWx_PostInd
|
|
1114647047U, // LDPSWx_PreInd
|
|
51389078U, // LDRSBw
|
|
2400199318U, // LDRSBw_PostInd
|
|
252715670U, // LDRSBw_PreInd
|
|
51389093U, // LDRSBw_U
|
|
51389078U, // LDRSBw_Wm_RegOffset
|
|
51389078U, // LDRSBw_Xm_RegOffset
|
|
51389078U, // LDRSBx
|
|
2400199318U, // LDRSBx_PostInd
|
|
252715670U, // LDRSBx_PreInd
|
|
51389093U, // LDRSBx_U
|
|
51389078U, // LDRSBx_Wm_RegOffset
|
|
51389078U, // LDRSBx_Xm_RegOffset
|
|
51389577U, // LDRSHw
|
|
2400199817U, // LDRSHw_PostInd
|
|
252716169U, // LDRSHw_PreInd
|
|
51389592U, // LDRSHw_U
|
|
51389577U, // LDRSHw_Wm_RegOffset
|
|
51389577U, // LDRSHw_Xm_RegOffset
|
|
51389577U, // LDRSHx
|
|
2400199817U, // LDRSHx_PostInd
|
|
252716169U, // LDRSHx_PreInd
|
|
51389592U, // LDRSHx_U
|
|
51389577U, // LDRSHx_Wm_RegOffset
|
|
51389577U, // LDRSHx_Xm_RegOffset
|
|
51390990U, // LDRSWx
|
|
2400201230U, // LDRSWx_PostInd
|
|
252717582U, // LDRSWx_PreInd
|
|
51390990U, // LDRSWx_Wm_RegOffset
|
|
51390990U, // LDRSWx_Xm_RegOffset
|
|
309340686U, // LDRSWx_lit
|
|
309340103U, // LDRd_lit
|
|
309340103U, // LDRq_lit
|
|
309340103U, // LDRs_lit
|
|
309340103U, // LDRw_lit
|
|
309340103U, // LDRx_lit
|
|
51389085U, // LDTRSBw
|
|
51389085U, // LDTRSBx
|
|
51389584U, // LDTRSHw
|
|
51389584U, // LDTRSHx
|
|
51390997U, // LDTRSWx
|
|
51391005U, // LDURSWx
|
|
1114646406U, // LDXP_dword
|
|
1114646406U, // LDXP_word
|
|
51389046U, // LDXR_byte
|
|
51390521U, // LDXR_dword
|
|
51389555U, // LDXR_hword
|
|
51390521U, // LDXR_word
|
|
51389500U, // LS16_LDR
|
|
51389533U, // LS16_LDUR
|
|
2400199740U, // LS16_PostInd_LDR
|
|
2400429136U, // LS16_PostInd_STR
|
|
252716092U, // LS16_PreInd_LDR
|
|
252945488U, // LS16_PreInd_STR
|
|
51389520U, // LS16_STR
|
|
51389540U, // LS16_STUR
|
|
51389513U, // LS16_UnPriv_LDR
|
|
51389526U, // LS16_UnPriv_STR
|
|
51389500U, // LS16_Wm_RegOffset_LDR
|
|
51389520U, // LS16_Wm_RegOffset_STR
|
|
51389500U, // LS16_Xm_RegOffset_LDR
|
|
51389520U, // LS16_Xm_RegOffset_STR
|
|
51390407U, // LS32_LDR
|
|
51390502U, // LS32_LDUR
|
|
2400200647U, // LS32_PostInd_LDR
|
|
2400430101U, // LS32_PostInd_STR
|
|
252716999U, // LS32_PreInd_LDR
|
|
252946453U, // LS32_PreInd_STR
|
|
51390485U, // LS32_STR
|
|
51390508U, // LS32_STUR
|
|
51390479U, // LS32_UnPriv_LDR
|
|
51390490U, // LS32_UnPriv_STR
|
|
51390407U, // LS32_Wm_RegOffset_LDR
|
|
51390485U, // LS32_Wm_RegOffset_STR
|
|
51390407U, // LS32_Xm_RegOffset_LDR
|
|
51390485U, // LS32_Xm_RegOffset_STR
|
|
51390407U, // LS64_LDR
|
|
51390502U, // LS64_LDUR
|
|
2400200647U, // LS64_PostInd_LDR
|
|
2400430101U, // LS64_PostInd_STR
|
|
252716999U, // LS64_PreInd_LDR
|
|
252946453U, // LS64_PreInd_STR
|
|
51390485U, // LS64_STR
|
|
51390508U, // LS64_STUR
|
|
51390479U, // LS64_UnPriv_LDR
|
|
51390490U, // LS64_UnPriv_STR
|
|
51390407U, // LS64_Wm_RegOffset_LDR
|
|
51390485U, // LS64_Wm_RegOffset_STR
|
|
51390407U, // LS64_Xm_RegOffset_LDR
|
|
51390485U, // LS64_Xm_RegOffset_STR
|
|
51388991U, // LS8_LDR
|
|
51389024U, // LS8_LDUR
|
|
2400199231U, // LS8_PostInd_LDR
|
|
2400428627U, // LS8_PostInd_STR
|
|
252715583U, // LS8_PreInd_LDR
|
|
252944979U, // LS8_PreInd_STR
|
|
51389011U, // LS8_STR
|
|
51389031U, // LS8_STUR
|
|
51389004U, // LS8_UnPriv_LDR
|
|
51389017U, // LS8_UnPriv_STR
|
|
51388991U, // LS8_Wm_RegOffset_LDR
|
|
51389011U, // LS8_Wm_RegOffset_STR
|
|
51388991U, // LS8_Xm_RegOffset_LDR
|
|
51389011U, // LS8_Xm_RegOffset_STR
|
|
51390407U, // LSFP128_LDR
|
|
51390502U, // LSFP128_LDUR
|
|
2400200647U, // LSFP128_PostInd_LDR
|
|
2400430101U, // LSFP128_PostInd_STR
|
|
252716999U, // LSFP128_PreInd_LDR
|
|
252946453U, // LSFP128_PreInd_STR
|
|
51390485U, // LSFP128_STR
|
|
51390508U, // LSFP128_STUR
|
|
51390407U, // LSFP128_Wm_RegOffset_LDR
|
|
51390485U, // LSFP128_Wm_RegOffset_STR
|
|
51390407U, // LSFP128_Xm_RegOffset_LDR
|
|
51390485U, // LSFP128_Xm_RegOffset_STR
|
|
51390407U, // LSFP16_LDR
|
|
51390502U, // LSFP16_LDUR
|
|
2400200647U, // LSFP16_PostInd_LDR
|
|
2400430101U, // LSFP16_PostInd_STR
|
|
252716999U, // LSFP16_PreInd_LDR
|
|
252946453U, // LSFP16_PreInd_STR
|
|
51390485U, // LSFP16_STR
|
|
51390508U, // LSFP16_STUR
|
|
51390407U, // LSFP16_Wm_RegOffset_LDR
|
|
51390485U, // LSFP16_Wm_RegOffset_STR
|
|
51390407U, // LSFP16_Xm_RegOffset_LDR
|
|
51390485U, // LSFP16_Xm_RegOffset_STR
|
|
51390407U, // LSFP32_LDR
|
|
51390502U, // LSFP32_LDUR
|
|
2400200647U, // LSFP32_PostInd_LDR
|
|
2400430101U, // LSFP32_PostInd_STR
|
|
252716999U, // LSFP32_PreInd_LDR
|
|
252946453U, // LSFP32_PreInd_STR
|
|
51390485U, // LSFP32_STR
|
|
51390508U, // LSFP32_STUR
|
|
51390407U, // LSFP32_Wm_RegOffset_LDR
|
|
51390485U, // LSFP32_Wm_RegOffset_STR
|
|
51390407U, // LSFP32_Xm_RegOffset_LDR
|
|
51390485U, // LSFP32_Xm_RegOffset_STR
|
|
51390407U, // LSFP64_LDR
|
|
51390502U, // LSFP64_LDUR
|
|
2400200647U, // LSFP64_PostInd_LDR
|
|
2400430101U, // LSFP64_PostInd_STR
|
|
252716999U, // LSFP64_PreInd_LDR
|
|
252946453U, // LSFP64_PreInd_STR
|
|
51390485U, // LSFP64_STR
|
|
51390508U, // LSFP64_STUR
|
|
51390407U, // LSFP64_Wm_RegOffset_LDR
|
|
51390485U, // LSFP64_Wm_RegOffset_STR
|
|
51390407U, // LSFP64_Xm_RegOffset_LDR
|
|
51390485U, // LSFP64_Xm_RegOffset_STR
|
|
51390407U, // LSFP8_LDR
|
|
51390502U, // LSFP8_LDUR
|
|
2400200647U, // LSFP8_PostInd_LDR
|
|
2400430101U, // LSFP8_PostInd_STR
|
|
252716999U, // LSFP8_PreInd_LDR
|
|
252946453U, // LSFP8_PreInd_STR
|
|
51390485U, // LSFP8_STR
|
|
51390508U, // LSFP8_STUR
|
|
51390407U, // LSFP8_Wm_RegOffset_LDR
|
|
51390485U, // LSFP8_Wm_RegOffset_STR
|
|
51390407U, // LSFP8_Xm_RegOffset_LDR
|
|
51390485U, // LSFP8_Xm_RegOffset_STR
|
|
1114646253U, // LSFPPair128_LDR
|
|
1114646321U, // LSFPPair128_NonTemp_LDR
|
|
1114646348U, // LSFPPair128_NonTemp_STR
|
|
1114646253U, // LSFPPair128_PostInd_LDR
|
|
1316202336U, // LSFPPair128_PostInd_STR
|
|
1114646253U, // LSFPPair128_PreInd_LDR
|
|
1316202336U, // LSFPPair128_PreInd_STR
|
|
1114646368U, // LSFPPair128_STR
|
|
1114646253U, // LSFPPair32_LDR
|
|
1114646321U, // LSFPPair32_NonTemp_LDR
|
|
1114646348U, // LSFPPair32_NonTemp_STR
|
|
1114646253U, // LSFPPair32_PostInd_LDR
|
|
1316202336U, // LSFPPair32_PostInd_STR
|
|
1114646253U, // LSFPPair32_PreInd_LDR
|
|
1316202336U, // LSFPPair32_PreInd_STR
|
|
1114646368U, // LSFPPair32_STR
|
|
1114646253U, // LSFPPair64_LDR
|
|
1114646321U, // LSFPPair64_NonTemp_LDR
|
|
1114646348U, // LSFPPair64_NonTemp_STR
|
|
1114646253U, // LSFPPair64_PostInd_LDR
|
|
1316202336U, // LSFPPair64_PostInd_STR
|
|
1114646253U, // LSFPPair64_PreInd_LDR
|
|
1316202336U, // LSFPPair64_PreInd_STR
|
|
1114646368U, // LSFPPair64_STR
|
|
40904149U, // LSLVwww
|
|
40904149U, // LSLVxxx
|
|
40904149U, // LSLwwi
|
|
40904149U, // LSLxxi
|
|
1114646253U, // LSPair32_LDR
|
|
1114646321U, // LSPair32_NonTemp_LDR
|
|
1114646348U, // LSPair32_NonTemp_STR
|
|
1114646253U, // LSPair32_PostInd_LDR
|
|
1316202336U, // LSPair32_PostInd_STR
|
|
1114646253U, // LSPair32_PreInd_LDR
|
|
1316202336U, // LSPair32_PreInd_STR
|
|
1114646368U, // LSPair32_STR
|
|
1114646253U, // LSPair64_LDR
|
|
1114646321U, // LSPair64_NonTemp_LDR
|
|
1114646348U, // LSPair64_NonTemp_STR
|
|
1114646253U, // LSPair64_PostInd_LDR
|
|
1316202336U, // LSPair64_PostInd_STR
|
|
1114646253U, // LSPair64_PreInd_LDR
|
|
1316202336U, // LSPair64_PreInd_STR
|
|
1114646368U, // LSPair64_STR
|
|
40904709U, // LSRVwww
|
|
40904709U, // LSRVxxx
|
|
40904709U, // LSRwwi
|
|
40904709U, // LSRxxi
|
|
40903511U, // MADDwwww
|
|
40903511U, // MADDxxxx
|
|
1142952443U, // MLAvve_2s4s
|
|
2217742843U, // MLAvve_4h8h
|
|
3292533243U, // MLAvve_4s4s
|
|
1147146747U, // MLAvve_8h8h
|
|
67113467U, // MLAvvv_16B
|
|
1142952443U, // MLAvvv_2S
|
|
2217742843U, // MLAvvv_4H
|
|
3292533243U, // MLAvvv_4S
|
|
3293581819U, // MLAvvv_8B
|
|
1147146747U, // MLAvvv_8H
|
|
1142954129U, // MLSvve_2s4s
|
|
2217744529U, // MLSvve_4h8h
|
|
3292534929U, // MLSvve_4s4s
|
|
1147148433U, // MLSvve_8h8h
|
|
67115153U, // MLSvvv_16B
|
|
1142954129U, // MLSvvv_2S
|
|
2217744529U, // MLSvvv_4H
|
|
3292534929U, // MLSvvv_4S
|
|
3293583505U, // MLSvvv_8B
|
|
1147148433U, // MLSvvv_8H
|
|
477113012U, // MOVIdi
|
|
3724547285U, // MOVIvi_16B
|
|
470817460U, // MOVIvi_2D
|
|
3729790165U, // MOVIvi_8B
|
|
3726644437U, // MOVIvi_lsl_2S
|
|
506467541U, // MOVIvi_lsl_4H
|
|
3728741589U, // MOVIvi_lsl_4S
|
|
509613269U, // MOVIvi_lsl_8H
|
|
1579160789U, // MOVIvi_msl_2S
|
|
1581257941U, // MOVIvi_msl_4S
|
|
544220384U, // MOVKwii
|
|
544220384U, // MOVKxii
|
|
577775313U, // MOVNwii
|
|
577775313U, // MOVNxii
|
|
577776302U, // MOVZwii
|
|
577776302U, // MOVZxii
|
|
611330235U, // MRSxi
|
|
243722U, // MSRii
|
|
247818U, // MSRix
|
|
40903374U, // MSUBwwww
|
|
40903374U, // MSUBxxxx
|
|
1075844598U, // MULve_2s4s
|
|
2150634998U, // MULve_4h8h
|
|
3225425398U, // MULve_4s4s
|
|
1080038902U, // MULve_8h8h
|
|
5622U, // MULvvv_16B
|
|
1075844598U, // MULvvv_2S
|
|
2150634998U, // MULvvv_4H
|
|
3225425398U, // MULvvv_4S
|
|
3226473974U, // MULvvv_8B
|
|
1080038902U, // MULvvv_8H
|
|
3726644418U, // MVNIvi_lsl_2S
|
|
506467522U, // MVNIvi_lsl_4H
|
|
3728741570U, // MVNIvi_lsl_4S
|
|
509613250U, // MVNIvi_lsl_8H
|
|
1579160770U, // MVNIvi_msl_2S
|
|
1581257922U, // MVNIvi_msl_4S
|
|
40904396U, // MVNww_asr
|
|
40904396U, // MVNww_lsl
|
|
40904396U, // MVNww_lsr
|
|
40904396U, // MVNww_ror
|
|
40904396U, // MVNxx_asr
|
|
40904396U, // MVNxx_lsl
|
|
40904396U, // MVNxx_lsr
|
|
40904396U, // MVNxx_ror
|
|
5088U, // NEG16b
|
|
1074795488U, // NEG2d
|
|
2149585888U, // NEG2s
|
|
3224376288U, // NEG4h
|
|
4199392U, // NEG4s
|
|
1078989792U, // NEG8b
|
|
2153780192U, // NEG8h
|
|
3262129120U, // NEGdd
|
|
6410U, // NOT16b
|
|
1078991114U, // NOT8b
|
|
5775U, // ORNvvv_16B
|
|
3226474127U, // ORNvvv_8B
|
|
40904335U, // ORNwww_asr
|
|
40904335U, // ORNwww_lsl
|
|
40904335U, // ORNwww_lsr
|
|
40904335U, // ORNwww_ror
|
|
40904335U, // ORNxxx_asr
|
|
40904335U, // ORNxxx_lsl
|
|
40904335U, // ORNxxx_lsr
|
|
40904335U, // ORNxxx_ror
|
|
270538747U, // ORRvi_lsl_2S
|
|
1345329147U, // ORRvi_lsl_4H
|
|
272635899U, // ORRvi_lsl_4S
|
|
1348474875U, // ORRvi_lsl_8H
|
|
6139U, // ORRvvv_16B
|
|
3226474491U, // ORRvvv_8B
|
|
40904699U, // ORRwwi
|
|
40904699U, // ORRwww_asr
|
|
40904699U, // ORRwww_lsl
|
|
40904699U, // ORRwww_lsr
|
|
40904699U, // ORRwww_ror
|
|
40904699U, // ORRxxi
|
|
40904699U, // ORRxxx_asr
|
|
40904699U, // ORRxxx_lsl
|
|
40904699U, // ORRxxx_lsr
|
|
40904699U, // ORRxxx_ror
|
|
656412886U, // PMULL2vvv_1q2d
|
|
6295766U, // PMULL2vvv_8h16b
|
|
689968567U, // PMULLvvv_1q1d
|
|
3227522487U, // PMULLvvv_8h8b
|
|
5634U, // PMULvvv_16B
|
|
3226473986U, // PMULvvv_8B
|
|
51631643U, // PRFM
|
|
51631643U, // PRFM_Wm_RegOffset
|
|
51631643U, // PRFM_Xm_RegOffset
|
|
309581339U, // PRFM_lit
|
|
51631673U, // PRFUM
|
|
1140855152U, // QRSHRUNvvi_16B
|
|
2149586618U, // QRSHRUNvvi_2S
|
|
3224377018U, // QRSHRUNvvi_4H
|
|
2218791280U, // QRSHRUNvvi_4S
|
|
1078990522U, // QRSHRUNvvi_8B
|
|
3294630256U, // QRSHRUNvvi_8H
|
|
1140855142U, // QSHRUNvvi_16B
|
|
2149586609U, // QSHRUNvvi_2S
|
|
3224377009U, // QSHRUNvvi_4H
|
|
2218791270U, // QSHRUNvvi_4S
|
|
1078990513U, // QSHRUNvvi_8B
|
|
3294630246U, // QSHRUNvvi_8H
|
|
1140855065U, // RADDHN2vvv_16b8h
|
|
2218791193U, // RADDHN2vvv_4s2d
|
|
3294630169U, // RADDHN2vvv_8h4s
|
|
2149586504U, // RADDHNvvv_2s2d
|
|
3224376904U, // RADDHNvvv_4h4s
|
|
1078990408U, // RADDHNvvv_8b8h
|
|
6381U, // RBIT16b
|
|
1078991085U, // RBIT8b
|
|
3262130413U, // RBITww
|
|
3262130413U, // RBITxx
|
|
0U, // RET
|
|
8399066U, // RETx
|
|
4583U, // REV16_16b
|
|
1078989287U, // REV16_8b
|
|
3262128615U, // REV16ww
|
|
3262128615U, // REV16xx
|
|
4172U, // REV32_16b
|
|
3224375372U, // REV32_4h
|
|
1078988876U, // REV32_8b
|
|
2153779276U, // REV32_8h
|
|
3262128204U, // REV32xx
|
|
4566U, // REV64_16b
|
|
2149585366U, // REV64_2s
|
|
3224375766U, // REV64_4h
|
|
4198870U, // REV64_4s
|
|
1078989270U, // REV64_8b
|
|
2153779670U, // REV64_8h
|
|
3262130526U, // REVww
|
|
3262130526U, // REVxx
|
|
40904694U, // RORVwww
|
|
40904694U, // RORVxxx
|
|
1140855094U, // RSHRNvvi_16B
|
|
2149586559U, // RSHRNvvi_2S
|
|
3224376959U, // RSHRNvvi_4H
|
|
2218791222U, // RSHRNvvi_4S
|
|
1078990463U, // RSHRNvvi_8B
|
|
3294630198U, // RSHRNvvi_8H
|
|
1140855056U, // RSUBHN2vvv_16b8h
|
|
2218791184U, // RSUBHN2vvv_4s2d
|
|
3294630160U, // RSUBHN2vvv_8h4s
|
|
2149586496U, // RSUBHNvvv_2s2d
|
|
3224376896U, // RSUBHNvvv_4h4s
|
|
1078990400U, // RSUBHNvvv_8b8h
|
|
3289387106U, // SABAL2vvv_2d2s
|
|
1145049186U, // SABAL2vvv_4s4h
|
|
73404514U, // SABAL2vvv_8h8b
|
|
1141904614U, // SABALvvv_2d2s
|
|
2218792166U, // SABALvvv_4s4h
|
|
3294631142U, // SABALvvv_8h8b
|
|
67113454U, // SABAvvv_16B
|
|
1142952430U, // SABAvvv_2S
|
|
2217742830U, // SABAvvv_4H
|
|
3292533230U, // SABAvvv_4S
|
|
3293581806U, // SABAvvv_8B
|
|
1147146734U, // SABAvvv_8H
|
|
3222278300U, // SABDL2vvv_2d2s
|
|
1077940380U, // SABDL2vvv_4s4h
|
|
6295708U, // SABDL2vvv_8h8b
|
|
1074795822U, // SABDLvvv_2d2s
|
|
2151683374U, // SABDLvvv_4s4h
|
|
3227522350U, // SABDLvvv_8h8b
|
|
4902U, // SABDvvv_16B
|
|
1075843878U, // SABDvvv_2S
|
|
2150634278U, // SABDvvv_4H
|
|
3225424678U, // SABDvvv_4S
|
|
3226473254U, // SABDvvv_8B
|
|
1080038182U, // SABDvvv_8H
|
|
73406194U, // SADALP16b8h
|
|
2234521330U, // SADALP2s1d
|
|
3290437362U, // SADALP4h2s
|
|
68163314U, // SADALP4s2d
|
|
1144002290U, // SADALP8b4h
|
|
2218792690U, // SADALP8h4s
|
|
3222278316U, // SADDL2vvv_2d4s
|
|
1077940396U, // SADDL2vvv_4s8h
|
|
6295724U, // SADDL2vvv_8h16b
|
|
6297346U, // SADDLP16b8h
|
|
2167412482U, // SADDLP2s1d
|
|
3223328514U, // SADDLP4h2s
|
|
1054466U, // SADDLP4s2d
|
|
1076893442U, // SADDLP8b4h
|
|
2151683842U, // SADDLP8h4s
|
|
7350645U, // SADDLV_1d4s
|
|
7350645U, // SADDLV_1h16b
|
|
1081092469U, // SADDLV_1h8b
|
|
3228576117U, // SADDLV_1s4h
|
|
2154834293U, // SADDLV_1s8h
|
|
1074795852U, // SADDLvvv_2d2s
|
|
2151683404U, // SADDLvvv_4s4h
|
|
3227522380U, // SADDLvvv_8h8b
|
|
2148536757U, // SADDW2vvv_2d4s
|
|
3225424309U, // SADDW2vvv_4s8h
|
|
1080037813U, // SADDW2vvv_8h16b
|
|
2148538873U, // SADDWvvv_2d2s
|
|
3225426425U, // SADDWvvv_4s4h
|
|
1080039929U, // SADDWvvv_8h8b
|
|
40904807U, // SBCSwww
|
|
40904807U, // SBCSxxx
|
|
40903409U, // SBCwww
|
|
40903409U, // SBCxxx
|
|
40905351U, // SBFIZwwii
|
|
40905351U, // SBFIZxxii
|
|
40904207U, // SBFMwwii
|
|
40904207U, // SBFMxxii
|
|
40905306U, // SBFXwwii
|
|
40905306U, // SBFXxxii
|
|
1074795473U, // SCVTF_2d
|
|
2149585873U, // SCVTF_2s
|
|
4199377U, // SCVTF_4s
|
|
40903633U, // SCVTF_Nddi
|
|
40903633U, // SCVTF_Nssi
|
|
3262129105U, // SCVTFdd
|
|
3262129105U, // SCVTFdw
|
|
40903633U, // SCVTFdwi
|
|
3262129105U, // SCVTFdx
|
|
40903633U, // SCVTFdxi
|
|
3262129105U, // SCVTFss
|
|
3262129105U, // SCVTFsw
|
|
40903633U, // SCVTFswi
|
|
3262129105U, // SCVTFsx
|
|
40903633U, // SCVTFsxi
|
|
40905065U, // SDIVwww
|
|
40905065U, // SDIVxxx
|
|
242229994U, // SHA1C
|
|
3262129139U, // SHA1H
|
|
242230792U, // SHA1M
|
|
242231007U, // SHA1P
|
|
3292532737U, // SHA1SU0
|
|
71307320U, // SHA1SU1
|
|
242230274U, // SHA256H
|
|
242229336U, // SHA256H2
|
|
71307274U, // SHA256SU0
|
|
3292532801U, // SHA256SU1
|
|
4936U, // SHADDvvv_16B
|
|
1075843912U, // SHADDvvv_2S
|
|
2150634312U, // SHADDvvv_4H
|
|
3225424712U, // SHADDvvv_4S
|
|
3226473288U, // SHADDvvv_8B
|
|
1080038216U, // SHADDvvv_8H
|
|
6295741U, // SHLL16b8h
|
|
1074795937U, // SHLL2s2d
|
|
2151683489U, // SHLL4h4s
|
|
3222278333U, // SHLL4s2d
|
|
3227522465U, // SHLL8b8h
|
|
1077940413U, // SHLL8h4s
|
|
40904035U, // SHLddi
|
|
5475U, // SHLvvi_16B
|
|
2148537699U, // SHLvvi_2D
|
|
1075844451U, // SHLvvi_2S
|
|
2150634851U, // SHLvvi_4H
|
|
3225425251U, // SHLvvi_4S
|
|
3226473827U, // SHLvvi_8B
|
|
1080038755U, // SHLvvi_8H
|
|
1140855076U, // SHRNvvi_16B
|
|
2149586543U, // SHRNvvi_2S
|
|
3224376943U, // SHRNvvi_4H
|
|
2218791204U, // SHRNvvi_4S
|
|
1078990447U, // SHRNvvi_8B
|
|
3294630180U, // SHRNvvi_8H
|
|
4799U, // SHSUBvvv_16B
|
|
1075843775U, // SHSUBvvv_2S
|
|
2150634175U, // SHSUBvvv_4H
|
|
3225424575U, // SHSUBvvv_4S
|
|
3226473151U, // SHSUBvvv_8B
|
|
1080038079U, // SHSUBvvv_8H
|
|
242230461U, // SLI
|
|
67114173U, // SLIvvi_16B
|
|
2215646397U, // SLIvvi_2D
|
|
1142953149U, // SLIvvi_2S
|
|
2217743549U, // SLIvvi_4H
|
|
3292533949U, // SLIvvi_4S
|
|
3293582525U, // SLIvvi_8B
|
|
1147147453U, // SLIvvi_8H
|
|
40903996U, // SMADDLxwwx
|
|
6008U, // SMAXPvvv_16B
|
|
1075844984U, // SMAXPvvv_2S
|
|
2150635384U, // SMAXPvvv_4H
|
|
3225425784U, // SMAXPvvv_4S
|
|
3226474360U, // SMAXPvvv_8B
|
|
1080039288U, // SMAXPvvv_8H
|
|
7350732U, // SMAXV_1b16b
|
|
1081092556U, // SMAXV_1b8b
|
|
3228576204U, // SMAXV_1h4h
|
|
2154834380U, // SMAXV_1h8h
|
|
7350732U, // SMAXV_1s4s
|
|
6713U, // SMAXvvv_16B
|
|
1075845689U, // SMAXvvv_2S
|
|
2150636089U, // SMAXvvv_4H
|
|
3225426489U, // SMAXvvv_4S
|
|
3226475065U, // SMAXvvv_8B
|
|
1080039993U, // SMAXvvv_8H
|
|
8397578U, // SMCi
|
|
5950U, // SMINPvvv_16B
|
|
1075844926U, // SMINPvvv_2S
|
|
2150635326U, // SMINPvvv_4H
|
|
3225425726U, // SMINPvvv_4S
|
|
3226474302U, // SMINPvvv_8B
|
|
1080039230U, // SMINPvvv_8H
|
|
7350686U, // SMINV_1b16b
|
|
1081092510U, // SMINV_1b8b
|
|
3228576158U, // SMINV_1h4h
|
|
2154834334U, // SMINV_1h8h
|
|
7350686U, // SMINV_1s4s
|
|
5718U, // SMINvvv_16B
|
|
1075844694U, // SMINvvv_2S
|
|
2150635094U, // SMINvvv_4H
|
|
3225425494U, // SMINvvv_4S
|
|
3226474070U, // SMINvvv_8B
|
|
1080038998U, // SMINvvv_8H
|
|
3289387132U, // SMLAL2vvv_2d4s
|
|
1145049212U, // SMLAL2vvv_4s8h
|
|
73404540U, // SMLAL2vvv_8h16b
|
|
1141904637U, // SMLALvve_2d2s
|
|
3289387132U, // SMLALvve_2d4s
|
|
2218792189U, // SMLALvve_4s4h
|
|
1145049212U, // SMLALvve_4s8h
|
|
1141904637U, // SMLALvvv_2d2s
|
|
2218792189U, // SMLALvvv_4s4h
|
|
3294631165U, // SMLALvvv_8h8b
|
|
3289387256U, // SMLSL2vvv_2d4s
|
|
1145049336U, // SMLSL2vvv_4s8h
|
|
73404664U, // SMLSL2vvv_8h16b
|
|
1141904858U, // SMLSLvve_2d2s
|
|
3289387256U, // SMLSLvve_2d4s
|
|
2218792410U, // SMLSLvve_4s4h
|
|
1145049336U, // SMLSLvve_4s8h
|
|
1141904858U, // SMLSLvvv_2d2s
|
|
2218792410U, // SMLSLvvv_4s4h
|
|
3294631386U, // SMLSLvvv_8h8b
|
|
2154834361U, // SMOVwb
|
|
1081092537U, // SMOVwh
|
|
2154834361U, // SMOVxb
|
|
1081092537U, // SMOVxh
|
|
7350713U, // SMOVxs
|
|
40903952U, // SMSUBLxwwx
|
|
40903719U, // SMULHxxx
|
|
3222278366U, // SMULL2vvv_2d4s
|
|
1077940446U, // SMULL2vvv_4s8h
|
|
6295774U, // SMULL2vvv_8h16b
|
|
1074795966U, // SMULLve_2d2s
|
|
3222278366U, // SMULLve_2d4s
|
|
2151683518U, // SMULLve_4s4h
|
|
1077940446U, // SMULLve_4s8h
|
|
1074795966U, // SMULLvvv_2d2s
|
|
2151683518U, // SMULLvvv_4s4h
|
|
3227522494U, // SMULLvvv_8h8b
|
|
6234U, // SQABS16b
|
|
1074796634U, // SQABS2d
|
|
2149587034U, // SQABS2s
|
|
3224377434U, // SQABS4h
|
|
4200538U, // SQABS4s
|
|
1078990938U, // SQABS8b
|
|
2153781338U, // SQABS8h
|
|
3262130266U, // SQABSbb
|
|
3262130266U, // SQABSdd
|
|
3262130266U, // SQABShh
|
|
3262130266U, // SQABSss
|
|
40903526U, // SQADDbbb
|
|
40903526U, // SQADDddd
|
|
40903526U, // SQADDhhh
|
|
40903526U, // SQADDsss
|
|
4966U, // SQADDvvv_16B
|
|
2148537190U, // SQADDvvv_2D
|
|
1075843942U, // SQADDvvv_2S
|
|
2150634342U, // SQADDvvv_4H
|
|
3225424742U, // SQADDvvv_4S
|
|
3226473318U, // SQADDvvv_8B
|
|
1080038246U, // SQADDvvv_8H
|
|
3289387122U, // SQDMLAL2vvv_2d4s
|
|
1145049202U, // SQDMLAL2vvv_4s8h
|
|
242230516U, // SQDMLALdss
|
|
242230516U, // SQDMLALdsv_2S
|
|
242230516U, // SQDMLALdsv_4S
|
|
242230516U, // SQDMLALshh
|
|
242230516U, // SQDMLALshv_4H
|
|
242230516U, // SQDMLALshv_8H
|
|
1141904628U, // SQDMLALvve_2d2s
|
|
3289387122U, // SQDMLALvve_2d4s
|
|
2218792180U, // SQDMLALvve_4s4h
|
|
1145049202U, // SQDMLALvve_4s8h
|
|
1141904628U, // SQDMLALvvv_2d2s
|
|
2218792180U, // SQDMLALvvv_4s4h
|
|
3289387246U, // SQDMLSL2vvv_2d4s
|
|
1145049326U, // SQDMLSL2vvv_4s8h
|
|
242230737U, // SQDMLSLdss
|
|
242230737U, // SQDMLSLdsv_2S
|
|
242230737U, // SQDMLSLdsv_4S
|
|
242230737U, // SQDMLSLshh
|
|
242230737U, // SQDMLSLshv_4H
|
|
242230737U, // SQDMLSLshv_8H
|
|
1141904849U, // SQDMLSLvve_2d2s
|
|
3289387246U, // SQDMLSLvve_2d4s
|
|
2218792401U, // SQDMLSLvve_4s4h
|
|
1145049326U, // SQDMLSLvve_4s8h
|
|
1141904849U, // SQDMLSLvvv_2d2s
|
|
2218792401U, // SQDMLSLvvv_4s4h
|
|
40903700U, // SQDMULHhhh
|
|
40903700U, // SQDMULHhhv_4H
|
|
40903700U, // SQDMULHhhv_8H
|
|
40903700U, // SQDMULHsss
|
|
40903700U, // SQDMULHssv_2S
|
|
40903700U, // SQDMULHssv_4S
|
|
1075844116U, // SQDMULHve_2s4s
|
|
2150634516U, // SQDMULHve_4h8h
|
|
3225424916U, // SQDMULHve_4s4s
|
|
1080038420U, // SQDMULHve_8h8h
|
|
1075844116U, // SQDMULHvvv_2S
|
|
2150634516U, // SQDMULHvvv_4H
|
|
3225424916U, // SQDMULHvvv_4S
|
|
1080038420U, // SQDMULHvvv_8H
|
|
3222278348U, // SQDMULL2vvv_2d4s
|
|
1077940428U, // SQDMULL2vvv_4s8h
|
|
40904110U, // SQDMULLdss
|
|
40904110U, // SQDMULLdsv_2S
|
|
40904110U, // SQDMULLdsv_4S
|
|
40904110U, // SQDMULLshh
|
|
40904110U, // SQDMULLshv_4H
|
|
40904110U, // SQDMULLshv_8H
|
|
1074795950U, // SQDMULLve_2d2s
|
|
3222278348U, // SQDMULLve_2d4s
|
|
2151683502U, // SQDMULLve_4s4h
|
|
1077940428U, // SQDMULLve_4s8h
|
|
1074795950U, // SQDMULLvvv_2d2s
|
|
2151683502U, // SQDMULLvvv_4s4h
|
|
5093U, // SQNEG16b
|
|
1074795493U, // SQNEG2d
|
|
2149585893U, // SQNEG2s
|
|
3224376293U, // SQNEG4h
|
|
4199397U, // SQNEG4s
|
|
1078989797U, // SQNEG8b
|
|
2153780197U, // SQNEG8h
|
|
3262129125U, // SQNEGbb
|
|
3262129125U, // SQNEGdd
|
|
3262129125U, // SQNEGhh
|
|
3262129125U, // SQNEGss
|
|
40903709U, // SQRDMULHhhh
|
|
40903709U, // SQRDMULHhhv_4H
|
|
40903709U, // SQRDMULHhhv_8H
|
|
40903709U, // SQRDMULHsss
|
|
40903709U, // SQRDMULHssv_2S
|
|
40903709U, // SQRDMULHssv_4S
|
|
1075844125U, // SQRDMULHve_2s4s
|
|
2150634525U, // SQRDMULHve_4h8h
|
|
3225424925U, // SQRDMULHve_4s4s
|
|
1080038429U, // SQRDMULHve_8h8h
|
|
1075844125U, // SQRDMULHvvv_2S
|
|
2150634525U, // SQRDMULHvvv_4H
|
|
3225424925U, // SQRDMULHvvv_4S
|
|
1080038429U, // SQRDMULHvvv_8H
|
|
40904047U, // SQRSHLbbb
|
|
40904047U, // SQRSHLddd
|
|
40904047U, // SQRSHLhhh
|
|
40904047U, // SQRSHLsss
|
|
5487U, // SQRSHLvvv_16B
|
|
2148537711U, // SQRSHLvvv_2D
|
|
1075844463U, // SQRSHLvvv_2S
|
|
2150634863U, // SQRSHLvvv_4H
|
|
3225425263U, // SQRSHLvvv_4S
|
|
3226473839U, // SQRSHLvvv_8B
|
|
1080038767U, // SQRSHLvvv_8H
|
|
40904317U, // SQRSHRNbhi
|
|
40904317U, // SQRSHRNhsi
|
|
40904317U, // SQRSHRNsdi
|
|
1140855092U, // SQRSHRNvvi_16B
|
|
2149586557U, // SQRSHRNvvi_2S
|
|
3224376957U, // SQRSHRNvvi_4H
|
|
2218791220U, // SQRSHRNvvi_4S
|
|
1078990461U, // SQRSHRNvvi_8B
|
|
3294630196U, // SQRSHRNvvi_8H
|
|
40904378U, // SQRSHRUNbhi
|
|
40904378U, // SQRSHRUNhsi
|
|
40904378U, // SQRSHRUNsdi
|
|
40905008U, // SQSHLUbbi
|
|
40905008U, // SQSHLUddi
|
|
40905008U, // SQSHLUhhi
|
|
40905008U, // SQSHLUssi
|
|
6448U, // SQSHLUvvi_16B
|
|
2148538672U, // SQSHLUvvi_2D
|
|
1075845424U, // SQSHLUvvi_2S
|
|
2150635824U, // SQSHLUvvi_4H
|
|
3225426224U, // SQSHLUvvi_4S
|
|
3226474800U, // SQSHLUvvi_8B
|
|
1080039728U, // SQSHLUvvi_8H
|
|
40904033U, // SQSHLbbb
|
|
40904033U, // SQSHLbbi
|
|
40904033U, // SQSHLddd
|
|
40904033U, // SQSHLddi
|
|
40904033U, // SQSHLhhh
|
|
40904033U, // SQSHLhhi
|
|
40904033U, // SQSHLssi
|
|
40904033U, // SQSHLsss
|
|
5473U, // SQSHLvvi_16B
|
|
2148537697U, // SQSHLvvi_2D
|
|
1075844449U, // SQSHLvvi_2S
|
|
2150634849U, // SQSHLvvi_4H
|
|
3225425249U, // SQSHLvvi_4S
|
|
3226473825U, // SQSHLvvi_8B
|
|
1080038753U, // SQSHLvvi_8H
|
|
5473U, // SQSHLvvv_16B
|
|
2148537697U, // SQSHLvvv_2D
|
|
1075844449U, // SQSHLvvv_2S
|
|
2150634849U, // SQSHLvvv_4H
|
|
3225425249U, // SQSHLvvv_4S
|
|
3226473825U, // SQSHLvvv_8B
|
|
1080038753U, // SQSHLvvv_8H
|
|
40904301U, // SQSHRNbhi
|
|
40904301U, // SQSHRNhsi
|
|
40904301U, // SQSHRNsdi
|
|
1140855074U, // SQSHRNvvi_16B
|
|
2149586541U, // SQSHRNvvi_2S
|
|
3224376941U, // SQSHRNvvi_4H
|
|
2218791202U, // SQSHRNvvi_4S
|
|
1078990445U, // SQSHRNvvi_8B
|
|
3294630178U, // SQSHRNvvi_8H
|
|
40904369U, // SQSHRUNbhi
|
|
40904369U, // SQSHRUNhsi
|
|
40904369U, // SQSHRUNsdi
|
|
40903388U, // SQSUBbbb
|
|
40903388U, // SQSUBddd
|
|
40903388U, // SQSUBhhh
|
|
40903388U, // SQSUBsss
|
|
4828U, // SQSUBvvv_16B
|
|
2148537052U, // SQSUBvvv_2D
|
|
1075843804U, // SQSUBvvv_2S
|
|
2150634204U, // SQSUBvvv_4H
|
|
3225424604U, // SQSUBvvv_4S
|
|
3226473180U, // SQSUBvvv_8B
|
|
1080038108U, // SQSUBvvv_8H
|
|
1075844771U, // SQXTN2d2s
|
|
1145049430U, // SQXTN2d4s
|
|
3151523U, // SQXTN4s4h
|
|
73404758U, // SQXTN4s8h
|
|
2214596950U, // SQXTN8h16b
|
|
2152732323U, // SQXTN8h8b
|
|
3262129827U, // SQXTNbh
|
|
3262129827U, // SQXTNhs
|
|
3262129827U, // SQXTNsd
|
|
1075844804U, // SQXTUN2d2s
|
|
1145049467U, // SQXTUN2d4s
|
|
3151556U, // SQXTUN4s4h
|
|
73404795U, // SQXTUN4s8h
|
|
2214596987U, // SQXTUN8h16b
|
|
2152732356U, // SQXTUN8h8b
|
|
3262129860U, // SQXTUNbh
|
|
3262129860U, // SQXTUNhs
|
|
3262129860U, // SQXTUNsd
|
|
4920U, // SRHADDvvv_16B
|
|
1075843896U, // SRHADDvvv_2S
|
|
2150634296U, // SRHADDvvv_4H
|
|
3225424696U, // SRHADDvvv_4S
|
|
3226473272U, // SRHADDvvv_8B
|
|
1080038200U, // SRHADDvvv_8H
|
|
242230472U, // SRI
|
|
67114184U, // SRIvvi_16B
|
|
2215646408U, // SRIvvi_2D
|
|
1142953160U, // SRIvvi_2S
|
|
2217743560U, // SRIvvi_4H
|
|
3292533960U, // SRIvvi_4S
|
|
3293582536U, // SRIvvi_8B
|
|
1147147464U, // SRIvvi_8H
|
|
40904063U, // SRSHLddd
|
|
5503U, // SRSHLvvv_16B
|
|
2148537727U, // SRSHLvvv_2D
|
|
1075844479U, // SRSHLvvv_2S
|
|
2150634879U, // SRSHLvvv_4H
|
|
3225425279U, // SRSHLvvv_4S
|
|
3226473855U, // SRSHLvvv_8B
|
|
1080038783U, // SRSHLvvv_8H
|
|
40904652U, // SRSHRddi
|
|
6092U, // SRSHRvvi_16B
|
|
2148538316U, // SRSHRvvi_2D
|
|
1075845068U, // SRSHRvvi_2S
|
|
2150635468U, // SRSHRvvi_4H
|
|
3225425868U, // SRSHRvvi_4S
|
|
3226474444U, // SRSHRvvi_8B
|
|
1080039372U, // SRSHRvvi_8H
|
|
242229760U, // SRSRA
|
|
67113472U, // SRSRAvvi_16B
|
|
2215645696U, // SRSRAvvi_2D
|
|
1142952448U, // SRSRAvvi_2S
|
|
2217742848U, // SRSRAvvi_4H
|
|
3292533248U, // SRSRAvvi_4S
|
|
3293581824U, // SRSRAvvi_8B
|
|
1147146752U, // SRSRAvvi_8H
|
|
6295740U, // SSHLLvvi_16B
|
|
1074795936U, // SSHLLvvi_2S
|
|
2151683488U, // SSHLLvvi_4H
|
|
3222278332U, // SSHLLvvi_4S
|
|
3227522464U, // SSHLLvvi_8B
|
|
1077940412U, // SSHLLvvi_8H
|
|
40904077U, // SSHLddd
|
|
5517U, // SSHLvvv_16B
|
|
2148537741U, // SSHLvvv_2D
|
|
1075844493U, // SSHLvvv_2S
|
|
2150634893U, // SSHLvvv_4H
|
|
3225425293U, // SSHLvvv_4S
|
|
3226473869U, // SSHLvvv_8B
|
|
1080038797U, // SSHLvvv_8H
|
|
40904666U, // SSHRddi
|
|
6106U, // SSHRvvi_16B
|
|
2148538330U, // SSHRvvi_2D
|
|
1075845082U, // SSHRvvi_2S
|
|
2150635482U, // SSHRvvi_4H
|
|
3225425882U, // SSHRvvi_4S
|
|
3226474458U, // SSHRvvi_8B
|
|
1080039386U, // SSHRvvi_8H
|
|
242229774U, // SSRA
|
|
67113486U, // SSRAvvi_16B
|
|
2215645710U, // SSRAvvi_2D
|
|
1142952462U, // SSRAvvi_2S
|
|
2217742862U, // SSRAvvi_4H
|
|
3292533262U, // SSRAvvi_4S
|
|
3293581838U, // SSRAvvi_8B
|
|
1147146766U, // SSRAvvi_8H
|
|
3222278284U, // SSUBL2vvv_2d4s
|
|
1077940364U, // SSUBL2vvv_4s8h
|
|
6295692U, // SSUBL2vvv_8h16b
|
|
1074795808U, // SSUBLvvv_2d2s
|
|
2151683360U, // SSUBLvvv_4s4h
|
|
3227522336U, // SSUBLvvv_8h8b
|
|
2148536741U, // SSUBW2vvv_2d4s
|
|
3225424293U, // SSUBW2vvv_4s8h
|
|
1080037797U, // SSUBW2vvv_8h16b
|
|
2148538850U, // SSUBWvvv_2d2s
|
|
3225426402U, // SSUBWvvv_4s4h
|
|
1080039906U, // SSUBWvvv_8h8b
|
|
254003U, // ST1LN_B
|
|
258099U, // ST1LN_D
|
|
262195U, // ST1LN_H
|
|
266291U, // ST1LN_S
|
|
270387U, // ST1LN_WB_B_fixed
|
|
270387U, // ST1LN_WB_B_register
|
|
274483U, // ST1LN_WB_D_fixed
|
|
274483U, // ST1LN_WB_D_register
|
|
278579U, // ST1LN_WB_H_fixed
|
|
278579U, // ST1LN_WB_H_register
|
|
282675U, // ST1LN_WB_S_fixed
|
|
282675U, // ST1LN_WB_S_register
|
|
286771U, // ST1WB_16B_fixed
|
|
286771U, // ST1WB_16B_register
|
|
290867U, // ST1WB_1D_fixed
|
|
290867U, // ST1WB_1D_register
|
|
294963U, // ST1WB_2D_fixed
|
|
294963U, // ST1WB_2D_register
|
|
299059U, // ST1WB_2S_fixed
|
|
299059U, // ST1WB_2S_register
|
|
303155U, // ST1WB_4H_fixed
|
|
303155U, // ST1WB_4H_register
|
|
307251U, // ST1WB_4S_fixed
|
|
307251U, // ST1WB_4S_register
|
|
311347U, // ST1WB_8B_fixed
|
|
311347U, // ST1WB_8B_register
|
|
315443U, // ST1WB_8H_fixed
|
|
315443U, // ST1WB_8H_register
|
|
319539U, // ST1_16B
|
|
323635U, // ST1_1D
|
|
327731U, // ST1_2D
|
|
331827U, // ST1_2S
|
|
335923U, // ST1_4H
|
|
340019U, // ST1_4S
|
|
344115U, // ST1_8B
|
|
348211U, // ST1_8H
|
|
352307U, // ST1x2WB_16B_fixed
|
|
352307U, // ST1x2WB_16B_register
|
|
356403U, // ST1x2WB_1D_fixed
|
|
356403U, // ST1x2WB_1D_register
|
|
360499U, // ST1x2WB_2D_fixed
|
|
360499U, // ST1x2WB_2D_register
|
|
364595U, // ST1x2WB_2S_fixed
|
|
364595U, // ST1x2WB_2S_register
|
|
368691U, // ST1x2WB_4H_fixed
|
|
368691U, // ST1x2WB_4H_register
|
|
372787U, // ST1x2WB_4S_fixed
|
|
372787U, // ST1x2WB_4S_register
|
|
376883U, // ST1x2WB_8B_fixed
|
|
376883U, // ST1x2WB_8B_register
|
|
380979U, // ST1x2WB_8H_fixed
|
|
380979U, // ST1x2WB_8H_register
|
|
385075U, // ST1x2_16B
|
|
389171U, // ST1x2_1D
|
|
393267U, // ST1x2_2D
|
|
397363U, // ST1x2_2S
|
|
401459U, // ST1x2_4H
|
|
405555U, // ST1x2_4S
|
|
409651U, // ST1x2_8B
|
|
413747U, // ST1x2_8H
|
|
417843U, // ST1x3WB_16B_fixed
|
|
417843U, // ST1x3WB_16B_register
|
|
421939U, // ST1x3WB_1D_fixed
|
|
421939U, // ST1x3WB_1D_register
|
|
426035U, // ST1x3WB_2D_fixed
|
|
426035U, // ST1x3WB_2D_register
|
|
430131U, // ST1x3WB_2S_fixed
|
|
430131U, // ST1x3WB_2S_register
|
|
434227U, // ST1x3WB_4H_fixed
|
|
434227U, // ST1x3WB_4H_register
|
|
438323U, // ST1x3WB_4S_fixed
|
|
438323U, // ST1x3WB_4S_register
|
|
442419U, // ST1x3WB_8B_fixed
|
|
442419U, // ST1x3WB_8B_register
|
|
446515U, // ST1x3WB_8H_fixed
|
|
446515U, // ST1x3WB_8H_register
|
|
450611U, // ST1x3_16B
|
|
454707U, // ST1x3_1D
|
|
458803U, // ST1x3_2D
|
|
462899U, // ST1x3_2S
|
|
466995U, // ST1x3_4H
|
|
471091U, // ST1x3_4S
|
|
475187U, // ST1x3_8B
|
|
479283U, // ST1x3_8H
|
|
483379U, // ST1x4WB_16B_fixed
|
|
483379U, // ST1x4WB_16B_register
|
|
487475U, // ST1x4WB_1D_fixed
|
|
487475U, // ST1x4WB_1D_register
|
|
491571U, // ST1x4WB_2D_fixed
|
|
491571U, // ST1x4WB_2D_register
|
|
495667U, // ST1x4WB_2S_fixed
|
|
495667U, // ST1x4WB_2S_register
|
|
499763U, // ST1x4WB_4H_fixed
|
|
499763U, // ST1x4WB_4H_register
|
|
503859U, // ST1x4WB_4S_fixed
|
|
503859U, // ST1x4WB_4S_register
|
|
507955U, // ST1x4WB_8B_fixed
|
|
507955U, // ST1x4WB_8B_register
|
|
512051U, // ST1x4WB_8H_fixed
|
|
512051U, // ST1x4WB_8H_register
|
|
516147U, // ST1x4_16B
|
|
520243U, // ST1x4_1D
|
|
524339U, // ST1x4_2D
|
|
528435U, // ST1x4_2S
|
|
532531U, // ST1x4_4H
|
|
536627U, // ST1x4_4S
|
|
540723U, // ST1x4_8B
|
|
544819U, // ST1x4_8H
|
|
549280U, // ST2LN_B
|
|
553376U, // ST2LN_D
|
|
557472U, // ST2LN_H
|
|
561568U, // ST2LN_S
|
|
565664U, // ST2LN_WB_B_fixed
|
|
565664U, // ST2LN_WB_B_register
|
|
569760U, // ST2LN_WB_D_fixed
|
|
569760U, // ST2LN_WB_D_register
|
|
573856U, // ST2LN_WB_H_fixed
|
|
573856U, // ST2LN_WB_H_register
|
|
577952U, // ST2LN_WB_S_fixed
|
|
577952U, // ST2LN_WB_S_register
|
|
352672U, // ST2WB_16B_fixed
|
|
352672U, // ST2WB_16B_register
|
|
360864U, // ST2WB_2D_fixed
|
|
360864U, // ST2WB_2D_register
|
|
364960U, // ST2WB_2S_fixed
|
|
364960U, // ST2WB_2S_register
|
|
369056U, // ST2WB_4H_fixed
|
|
369056U, // ST2WB_4H_register
|
|
373152U, // ST2WB_4S_fixed
|
|
373152U, // ST2WB_4S_register
|
|
377248U, // ST2WB_8B_fixed
|
|
377248U, // ST2WB_8B_register
|
|
381344U, // ST2WB_8H_fixed
|
|
381344U, // ST2WB_8H_register
|
|
385440U, // ST2_16B
|
|
393632U, // ST2_2D
|
|
397728U, // ST2_2S
|
|
401824U, // ST2_4H
|
|
405920U, // ST2_4S
|
|
410016U, // ST2_8B
|
|
414112U, // ST2_8H
|
|
582097U, // ST3LN_B
|
|
586193U, // ST3LN_D
|
|
590289U, // ST3LN_H
|
|
594385U, // ST3LN_S
|
|
598481U, // ST3LN_WB_B_fixed
|
|
598481U, // ST3LN_WB_B_register
|
|
602577U, // ST3LN_WB_D_fixed
|
|
602577U, // ST3LN_WB_D_register
|
|
606673U, // ST3LN_WB_H_fixed
|
|
606673U, // ST3LN_WB_H_register
|
|
610769U, // ST3LN_WB_S_fixed
|
|
610769U, // ST3LN_WB_S_register
|
|
418257U, // ST3WB_16B_fixed
|
|
418257U, // ST3WB_16B_register
|
|
426449U, // ST3WB_2D_fixed
|
|
426449U, // ST3WB_2D_register
|
|
430545U, // ST3WB_2S_fixed
|
|
430545U, // ST3WB_2S_register
|
|
434641U, // ST3WB_4H_fixed
|
|
434641U, // ST3WB_4H_register
|
|
438737U, // ST3WB_4S_fixed
|
|
438737U, // ST3WB_4S_register
|
|
442833U, // ST3WB_8B_fixed
|
|
442833U, // ST3WB_8B_register
|
|
446929U, // ST3WB_8H_fixed
|
|
446929U, // ST3WB_8H_register
|
|
451025U, // ST3_16B
|
|
459217U, // ST3_2D
|
|
463313U, // ST3_2S
|
|
467409U, // ST3_4H
|
|
471505U, // ST3_4S
|
|
475601U, // ST3_8B
|
|
479697U, // ST3_8H
|
|
614882U, // ST4LN_B
|
|
618978U, // ST4LN_D
|
|
623074U, // ST4LN_H
|
|
627170U, // ST4LN_S
|
|
631266U, // ST4LN_WB_B_fixed
|
|
631266U, // ST4LN_WB_B_register
|
|
635362U, // ST4LN_WB_D_fixed
|
|
635362U, // ST4LN_WB_D_register
|
|
639458U, // ST4LN_WB_H_fixed
|
|
639458U, // ST4LN_WB_H_register
|
|
643554U, // ST4LN_WB_S_fixed
|
|
643554U, // ST4LN_WB_S_register
|
|
483810U, // ST4WB_16B_fixed
|
|
483810U, // ST4WB_16B_register
|
|
492002U, // ST4WB_2D_fixed
|
|
492002U, // ST4WB_2D_register
|
|
496098U, // ST4WB_2S_fixed
|
|
496098U, // ST4WB_2S_register
|
|
500194U, // ST4WB_4H_fixed
|
|
500194U, // ST4WB_4H_register
|
|
504290U, // ST4WB_4S_fixed
|
|
504290U, // ST4WB_4S_register
|
|
508386U, // ST4WB_8B_fixed
|
|
508386U, // ST4WB_8B_register
|
|
512482U, // ST4WB_8H_fixed
|
|
512482U, // ST4WB_8H_register
|
|
516578U, // ST4_16B
|
|
524770U, // ST4_2D
|
|
528866U, // ST4_2S
|
|
532962U, // ST4_4H
|
|
537058U, // ST4_4S
|
|
541154U, // ST4_8B
|
|
545250U, // ST4_8H
|
|
51388997U, // STLR_byte
|
|
51390443U, // STLR_dword
|
|
51389506U, // STLR_hword
|
|
51390443U, // STLR_word
|
|
40904588U, // STLXP_dword
|
|
40904588U, // STLXP_word
|
|
1114645117U, // STLXR_byte
|
|
1114646591U, // STLXR_dword
|
|
1114645626U, // STLXR_hword
|
|
1114646591U, // STLXR_word
|
|
40904595U, // STXP_dword
|
|
40904595U, // STXP_word
|
|
1114645125U, // STXR_byte
|
|
1114646598U, // STXR_dword
|
|
1114645634U, // STXR_hword
|
|
1114646598U, // STXR_word
|
|
1140855057U, // SUBHN2vvv_16b8h
|
|
2218791185U, // SUBHN2vvv_4s2d
|
|
3294630161U, // SUBHN2vvv_8h4s
|
|
2149586497U, // SUBHNvvv_2s2d
|
|
3224376897U, // SUBHNvvv_4h4s
|
|
1078990401U, // SUBHNvvv_8b8h
|
|
40904801U, // SUBSwww_asr
|
|
40904801U, // SUBSwww_lsl
|
|
40904801U, // SUBSwww_lsr
|
|
40904801U, // SUBSwww_sxtb
|
|
40904801U, // SUBSwww_sxth
|
|
40904801U, // SUBSwww_sxtw
|
|
40904801U, // SUBSwww_sxtx
|
|
40904801U, // SUBSwww_uxtb
|
|
40904801U, // SUBSwww_uxth
|
|
40904801U, // SUBSwww_uxtw
|
|
40904801U, // SUBSwww_uxtx
|
|
40904801U, // SUBSxxw_sxtb
|
|
40904801U, // SUBSxxw_sxth
|
|
40904801U, // SUBSxxw_sxtw
|
|
40904801U, // SUBSxxw_uxtb
|
|
40904801U, // SUBSxxw_uxth
|
|
40904801U, // SUBSxxw_uxtw
|
|
40904801U, // SUBSxxx_asr
|
|
40904801U, // SUBSxxx_lsl
|
|
40904801U, // SUBSxxx_lsr
|
|
40904801U, // SUBSxxx_sxtx
|
|
40904801U, // SUBSxxx_uxtx
|
|
40903354U, // SUBddd
|
|
4794U, // SUBvvv_16B
|
|
2148537018U, // SUBvvv_2D
|
|
1075843770U, // SUBvvv_2S
|
|
2150634170U, // SUBvvv_4H
|
|
3225424570U, // SUBvvv_4S
|
|
3226473146U, // SUBvvv_8B
|
|
1080038074U, // SUBvvv_8H
|
|
40904801U, // SUBwwi_lsl0_S
|
|
108014272U, // SUBwwi_lsl0_cmp
|
|
40903354U, // SUBwwi_lsl0_s
|
|
40904801U, // SUBwwi_lsl12_S
|
|
141568704U, // SUBwwi_lsl12_cmp
|
|
40903354U, // SUBwwi_lsl12_s
|
|
40903354U, // SUBwww_asr
|
|
40903354U, // SUBwww_lsl
|
|
40903354U, // SUBwww_lsr
|
|
40903354U, // SUBwww_sxtb
|
|
40903354U, // SUBwww_sxth
|
|
40903354U, // SUBwww_sxtw
|
|
40903354U, // SUBwww_sxtx
|
|
40903354U, // SUBwww_uxtb
|
|
40903354U, // SUBwww_uxth
|
|
40903354U, // SUBwww_uxtw
|
|
40903354U, // SUBwww_uxtx
|
|
40904801U, // SUBxxi_lsl0_S
|
|
108014272U, // SUBxxi_lsl0_cmp
|
|
40903354U, // SUBxxi_lsl0_s
|
|
40904801U, // SUBxxi_lsl12_S
|
|
141568704U, // SUBxxi_lsl12_cmp
|
|
40903354U, // SUBxxi_lsl12_s
|
|
40903354U, // SUBxxw_sxtb
|
|
40903354U, // SUBxxw_sxth
|
|
40903354U, // SUBxxw_sxtw
|
|
40903354U, // SUBxxw_uxtb
|
|
40903354U, // SUBxxw_uxth
|
|
40903354U, // SUBxxw_uxtw
|
|
40903354U, // SUBxxx_asr
|
|
40903354U, // SUBxxx_lsl
|
|
40903354U, // SUBxxx_lsr
|
|
40903354U, // SUBxxx_sxtx
|
|
40903354U, // SUBxxx_uxtx
|
|
67113837U, // SUQADD16b
|
|
1141904237U, // SUQADD2d
|
|
2216694637U, // SUQADD2s
|
|
3291485037U, // SUQADD4h
|
|
71308141U, // SUQADD4s
|
|
1146098541U, // SUQADD8b
|
|
2220888941U, // SUQADD8h
|
|
3463455597U, // SUQADDbb
|
|
3463455597U, // SUQADDdd
|
|
3463455597U, // SUQADDhh
|
|
3463455597U, // SUQADDss
|
|
8397595U, // SVCi
|
|
3262128813U, // SXTBww
|
|
3262128813U, // SXTBxw
|
|
3262129312U, // SXTHww
|
|
3262129312U, // SXTHxw
|
|
3262130725U, // SXTWxw
|
|
40904168U, // SYSLxicci
|
|
711993545U, // SYSiccix
|
|
0U, // TAIL_BRx
|
|
0U, // TAIL_Bimm
|
|
738202891U, // TBL1_16b
|
|
1817187595U, // TBL1_8b
|
|
771757323U, // TBL2_16b
|
|
1850742027U, // TBL2_8b
|
|
805311755U, // TBL3_16b
|
|
1884296459U, // TBL3_8b
|
|
838866187U, // TBL4_16b
|
|
1917850891U, // TBL4_8b
|
|
40905376U, // TBNZwii
|
|
40905376U, // TBNZxii
|
|
872421957U, // TBX1_16b
|
|
1951406661U, // TBX1_8b
|
|
905976389U, // TBX2_16b
|
|
1984961093U, // TBX2_8b
|
|
939530821U, // TBX3_16b
|
|
2018515525U, // TBX3_8b
|
|
973085253U, // TBX4_16b
|
|
2052069957U, // TBX4_8b
|
|
40905346U, // TBZwii
|
|
40905346U, // TBZxii
|
|
0U, // TC_RETURNdi
|
|
0U, // TC_RETURNxi
|
|
9036972U, // TLBIi
|
|
3262768300U, // TLBIix
|
|
0U, // TLSDESCCALL
|
|
0U, // TLSDESC_BLRx
|
|
4122U, // TRN1vvv_16b
|
|
2148536346U, // TRN1vvv_2d
|
|
1075843098U, // TRN1vvv_2s
|
|
2150633498U, // TRN1vvv_4h
|
|
3225423898U, // TRN1vvv_4s
|
|
3226472474U, // TRN1vvv_8b
|
|
1080037402U, // TRN1vvv_8h
|
|
4424U, // TRN2vvv_16b
|
|
2148536648U, // TRN2vvv_2d
|
|
1075843400U, // TRN2vvv_2s
|
|
2150633800U, // TRN2vvv_4h
|
|
3225424200U, // TRN2vvv_4s
|
|
3226472776U, // TRN2vvv_8b
|
|
1080037704U, // TRN2vvv_8h
|
|
40904984U, // TSTww_asr
|
|
40904984U, // TSTww_lsl
|
|
40904984U, // TSTww_lsr
|
|
40904984U, // TSTww_ror
|
|
40904984U, // TSTxx_asr
|
|
40904984U, // TSTxx_lsl
|
|
40904984U, // TSTxx_lsr
|
|
40904984U, // TSTxx_ror
|
|
3289387114U, // UABAL2vvv_2d2s
|
|
1145049194U, // UABAL2vvv_4s4h
|
|
73404522U, // UABAL2vvv_8h8b
|
|
1141904621U, // UABALvvv_2d2s
|
|
2218792173U, // UABALvvv_4s4h
|
|
3294631149U, // UABALvvv_8h8b
|
|
67113460U, // UABAvvv_16B
|
|
1142952436U, // UABAvvv_2S
|
|
2217742836U, // UABAvvv_4H
|
|
3292533236U, // UABAvvv_4S
|
|
3293581812U, // UABAvvv_8B
|
|
1147146740U, // UABAvvv_8H
|
|
3222278308U, // UABDL2vvv_2d2s
|
|
1077940388U, // UABDL2vvv_4s4h
|
|
6295716U, // UABDL2vvv_8h8b
|
|
1074795829U, // UABDLvvv_2d2s
|
|
2151683381U, // UABDLvvv_4s4h
|
|
3227522357U, // UABDLvvv_8h8b
|
|
4908U, // UABDvvv_16B
|
|
1075843884U, // UABDvvv_2S
|
|
2150634284U, // UABDvvv_4H
|
|
3225424684U, // UABDvvv_4S
|
|
3226473260U, // UABDvvv_8B
|
|
1080038188U, // UABDvvv_8H
|
|
73406202U, // UADALP16b8h
|
|
2234521338U, // UADALP2s1d
|
|
3290437370U, // UADALP4h2s
|
|
68163322U, // UADALP4s2d
|
|
1144002298U, // UADALP8b4h
|
|
2218792698U, // UADALP8h4s
|
|
3222278324U, // UADDL2vvv_2d4s
|
|
1077940404U, // UADDL2vvv_4s8h
|
|
6295732U, // UADDL2vvv_8h16b
|
|
6297354U, // UADDLP16b8h
|
|
2167412490U, // UADDLP2s1d
|
|
3223328522U, // UADDLP4h2s
|
|
1054474U, // UADDLP4s2d
|
|
1076893450U, // UADDLP8b4h
|
|
2151683850U, // UADDLP8h4s
|
|
7350653U, // UADDLV_1d4s
|
|
7350653U, // UADDLV_1h16b
|
|
1081092477U, // UADDLV_1h8b
|
|
3228576125U, // UADDLV_1s4h
|
|
2154834301U, // UADDLV_1s8h
|
|
1074795859U, // UADDLvvv_2d2s
|
|
2151683411U, // UADDLvvv_4s4h
|
|
3227522387U, // UADDLvvv_8h8b
|
|
2148536765U, // UADDW2vvv_2d4s
|
|
3225424317U, // UADDW2vvv_4s8h
|
|
1080037821U, // UADDW2vvv_8h16b
|
|
2148538880U, // UADDWvvv_2d2s
|
|
3225426432U, // UADDWvvv_4s4h
|
|
1080039936U, // UADDWvvv_8h8b
|
|
40905358U, // UBFIZwwii
|
|
40905358U, // UBFIZxxii
|
|
40904213U, // UBFMwwii
|
|
40904213U, // UBFMxxii
|
|
40905312U, // UBFXwwii
|
|
40905312U, // UBFXxxii
|
|
1074795480U, // UCVTF_2d
|
|
2149585880U, // UCVTF_2s
|
|
4199384U, // UCVTF_4s
|
|
40903640U, // UCVTF_Nddi
|
|
40903640U, // UCVTF_Nssi
|
|
3262129112U, // UCVTFdd
|
|
3262129112U, // UCVTFdw
|
|
40903640U, // UCVTFdwi
|
|
3262129112U, // UCVTFdx
|
|
40903640U, // UCVTFdxi
|
|
3262129112U, // UCVTFss
|
|
3262129112U, // UCVTFsw
|
|
40903640U, // UCVTFswi
|
|
3262129112U, // UCVTFsx
|
|
40903640U, // UCVTFsxi
|
|
40905071U, // UDIVwww
|
|
40905071U, // UDIVxxx
|
|
4943U, // UHADDvvv_16B
|
|
1075843919U, // UHADDvvv_2S
|
|
2150634319U, // UHADDvvv_4H
|
|
3225424719U, // UHADDvvv_4S
|
|
3226473295U, // UHADDvvv_8B
|
|
1080038223U, // UHADDvvv_8H
|
|
4806U, // UHSUBvvv_16B
|
|
1075843782U, // UHSUBvvv_2S
|
|
2150634182U, // UHSUBvvv_4H
|
|
3225424582U, // UHSUBvvv_4S
|
|
3226473158U, // UHSUBvvv_8B
|
|
1080038086U, // UHSUBvvv_8H
|
|
40904004U, // UMADDLxwwx
|
|
6015U, // UMAXPvvv_16B
|
|
1075844991U, // UMAXPvvv_2S
|
|
2150635391U, // UMAXPvvv_4H
|
|
3225425791U, // UMAXPvvv_4S
|
|
3226474367U, // UMAXPvvv_8B
|
|
1080039295U, // UMAXPvvv_8H
|
|
7350739U, // UMAXV_1b16b
|
|
1081092563U, // UMAXV_1b8b
|
|
3228576211U, // UMAXV_1h4h
|
|
2154834387U, // UMAXV_1h8h
|
|
7350739U, // UMAXV_1s4s
|
|
6719U, // UMAXvvv_16B
|
|
1075845695U, // UMAXvvv_2S
|
|
2150636095U, // UMAXvvv_4H
|
|
3225426495U, // UMAXvvv_4S
|
|
3226475071U, // UMAXvvv_8B
|
|
1080039999U, // UMAXvvv_8H
|
|
5957U, // UMINPvvv_16B
|
|
1075844933U, // UMINPvvv_2S
|
|
2150635333U, // UMINPvvv_4H
|
|
3225425733U, // UMINPvvv_4S
|
|
3226474309U, // UMINPvvv_8B
|
|
1080039237U, // UMINPvvv_8H
|
|
7350693U, // UMINV_1b16b
|
|
1081092517U, // UMINV_1b8b
|
|
3228576165U, // UMINV_1h4h
|
|
2154834341U, // UMINV_1h8h
|
|
7350693U, // UMINV_1s4s
|
|
5724U, // UMINvvv_16B
|
|
1075844700U, // UMINvvv_2S
|
|
2150635100U, // UMINvvv_4H
|
|
3225425500U, // UMINvvv_4S
|
|
3226474076U, // UMINvvv_8B
|
|
1080039004U, // UMINvvv_8H
|
|
3289387140U, // UMLAL2vvv_2d4s
|
|
1145049220U, // UMLAL2vvv_4s8h
|
|
73404548U, // UMLAL2vvv_8h16b
|
|
1141904644U, // UMLALvve_2d2s
|
|
3289387140U, // UMLALvve_2d4s
|
|
2218792196U, // UMLALvve_4s4h
|
|
1145049220U, // UMLALvve_4s8h
|
|
1141904644U, // UMLALvvv_2d2s
|
|
2218792196U, // UMLALvvv_4s4h
|
|
3294631172U, // UMLALvvv_8h8b
|
|
3289387264U, // UMLSL2vvv_2d4s
|
|
1145049344U, // UMLSL2vvv_4s8h
|
|
73404672U, // UMLSL2vvv_8h16b
|
|
1141904865U, // UMLSLvve_2d2s
|
|
3289387264U, // UMLSLvve_2d4s
|
|
2218792417U, // UMLSLvve_4s4h
|
|
1145049344U, // UMLSLvve_4s8h
|
|
1141904865U, // UMLSLvvv_2d2s
|
|
2218792417U, // UMLSLvvv_4s4h
|
|
3294631393U, // UMLSLvvv_8h8b
|
|
2154834367U, // UMOVwb
|
|
1081092543U, // UMOVwh
|
|
7350719U, // UMOVws
|
|
3228576191U, // UMOVxd
|
|
40903960U, // UMSUBLxwwx
|
|
40903726U, // UMULHxxx
|
|
3222278374U, // UMULL2vvv_2d4s
|
|
1077940454U, // UMULL2vvv_4s8h
|
|
6295782U, // UMULL2vvv_8h16b
|
|
1074795973U, // UMULLve_2d2s
|
|
3222278374U, // UMULLve_2d4s
|
|
2151683525U, // UMULLve_4s4h
|
|
1077940454U, // UMULLve_4s8h
|
|
1074795973U, // UMULLvvv_2d2s
|
|
2151683525U, // UMULLvvv_4s4h
|
|
3227522501U, // UMULLvvv_8h8b
|
|
40903534U, // UQADDbbb
|
|
40903534U, // UQADDddd
|
|
40903534U, // UQADDhhh
|
|
40903534U, // UQADDsss
|
|
4974U, // UQADDvvv_16B
|
|
2148537198U, // UQADDvvv_2D
|
|
1075843950U, // UQADDvvv_2S
|
|
2150634350U, // UQADDvvv_4H
|
|
3225424750U, // UQADDvvv_4S
|
|
3226473326U, // UQADDvvv_8B
|
|
1080038254U, // UQADDvvv_8H
|
|
40904055U, // UQRSHLbbb
|
|
40904055U, // UQRSHLddd
|
|
40904055U, // UQRSHLhhh
|
|
40904055U, // UQRSHLsss
|
|
5495U, // UQRSHLvvv_16B
|
|
2148537719U, // UQRSHLvvv_2D
|
|
1075844471U, // UQRSHLvvv_2S
|
|
2150634871U, // UQRSHLvvv_4H
|
|
3225425271U, // UQRSHLvvv_4S
|
|
3226473847U, // UQRSHLvvv_8B
|
|
1080038775U, // UQRSHLvvv_8H
|
|
40904326U, // UQRSHRNbhi
|
|
40904326U, // UQRSHRNhsi
|
|
40904326U, // UQRSHRNsdi
|
|
1140855102U, // UQRSHRNvvi_16B
|
|
2149586566U, // UQRSHRNvvi_2S
|
|
3224376966U, // UQRSHRNvvi_4H
|
|
2218791230U, // UQRSHRNvvi_4S
|
|
1078990470U, // UQRSHRNvvi_8B
|
|
3294630206U, // UQRSHRNvvi_8H
|
|
40904040U, // UQSHLbbb
|
|
40904040U, // UQSHLbbi
|
|
40904040U, // UQSHLddd
|
|
40904040U, // UQSHLddi
|
|
40904040U, // UQSHLhhh
|
|
40904040U, // UQSHLhhi
|
|
40904040U, // UQSHLssi
|
|
40904040U, // UQSHLsss
|
|
5480U, // UQSHLvvi_16B
|
|
2148537704U, // UQSHLvvi_2D
|
|
1075844456U, // UQSHLvvi_2S
|
|
2150634856U, // UQSHLvvi_4H
|
|
3225425256U, // UQSHLvvi_4S
|
|
3226473832U, // UQSHLvvi_8B
|
|
1080038760U, // UQSHLvvi_8H
|
|
5480U, // UQSHLvvv_16B
|
|
2148537704U, // UQSHLvvv_2D
|
|
1075844456U, // UQSHLvvv_2S
|
|
2150634856U, // UQSHLvvv_4H
|
|
3225425256U, // UQSHLvvv_4S
|
|
3226473832U, // UQSHLvvv_8B
|
|
1080038760U, // UQSHLvvv_8H
|
|
40904309U, // UQSHRNbhi
|
|
40904309U, // UQSHRNhsi
|
|
40904309U, // UQSHRNsdi
|
|
1140855083U, // UQSHRNvvi_16B
|
|
2149586549U, // UQSHRNvvi_2S
|
|
3224376949U, // UQSHRNvvi_4H
|
|
2218791211U, // UQSHRNvvi_4S
|
|
1078990453U, // UQSHRNvvi_8B
|
|
3294630187U, // UQSHRNvvi_8H
|
|
40903395U, // UQSUBbbb
|
|
40903395U, // UQSUBddd
|
|
40903395U, // UQSUBhhh
|
|
40903395U, // UQSUBsss
|
|
4835U, // UQSUBvvv_16B
|
|
2148537059U, // UQSUBvvv_2D
|
|
1075843811U, // UQSUBvvv_2S
|
|
2150634211U, // UQSUBvvv_4H
|
|
3225424611U, // UQSUBvvv_4S
|
|
3226473187U, // UQSUBvvv_8B
|
|
1080038115U, // UQSUBvvv_8H
|
|
1075844778U, // UQXTN2d2s
|
|
1145049438U, // UQXTN2d4s
|
|
3151530U, // UQXTN4s4h
|
|
73404766U, // UQXTN4s8h
|
|
2214596958U, // UQXTN8h16b
|
|
2152732330U, // UQXTN8h8b
|
|
3262129834U, // UQXTNbh
|
|
3262129834U, // UQXTNhs
|
|
3262129834U, // UQXTNsd
|
|
2149585821U, // URECPE2s
|
|
4199325U, // URECPE4s
|
|
4928U, // URHADDvvv_16B
|
|
1075843904U, // URHADDvvv_2S
|
|
2150634304U, // URHADDvvv_4H
|
|
3225424704U, // URHADDvvv_4S
|
|
3226473280U, // URHADDvvv_8B
|
|
1080038208U, // URHADDvvv_8H
|
|
40904070U, // URSHLddd
|
|
5510U, // URSHLvvv_16B
|
|
2148537734U, // URSHLvvv_2D
|
|
1075844486U, // URSHLvvv_2S
|
|
2150634886U, // URSHLvvv_4H
|
|
3225425286U, // URSHLvvv_4S
|
|
3226473862U, // URSHLvvv_8B
|
|
1080038790U, // URSHLvvv_8H
|
|
40904659U, // URSHRddi
|
|
6099U, // URSHRvvi_16B
|
|
2148538323U, // URSHRvvi_2D
|
|
1075845075U, // URSHRvvi_2S
|
|
2150635475U, // URSHRvvi_4H
|
|
3225425875U, // URSHRvvi_4S
|
|
3226474451U, // URSHRvvi_8B
|
|
1080039379U, // URSHRvvi_8H
|
|
2149585859U, // URSQRTE2s
|
|
4199363U, // URSQRTE4s
|
|
242229767U, // URSRA
|
|
67113479U, // URSRAvvi_16B
|
|
2215645703U, // URSRAvvi_2D
|
|
1142952455U, // URSRAvvi_2S
|
|
2217742855U, // URSRAvvi_4H
|
|
3292533255U, // URSRAvvi_4S
|
|
3293581831U, // URSRAvvi_8B
|
|
1147146759U, // URSRAvvi_8H
|
|
6295748U, // USHLLvvi_16B
|
|
1074795943U, // USHLLvvi_2S
|
|
2151683495U, // USHLLvvi_4H
|
|
3222278340U, // USHLLvvi_4S
|
|
3227522471U, // USHLLvvi_8B
|
|
1077940420U, // USHLLvvi_8H
|
|
40904083U, // USHLddd
|
|
5523U, // USHLvvv_16B
|
|
2148537747U, // USHLvvv_2D
|
|
1075844499U, // USHLvvv_2S
|
|
2150634899U, // USHLvvv_4H
|
|
3225425299U, // USHLvvv_4S
|
|
3226473875U, // USHLvvv_8B
|
|
1080038803U, // USHLvvv_8H
|
|
40904672U, // USHRddi
|
|
6112U, // USHRvvi_16B
|
|
2148538336U, // USHRvvi_2D
|
|
1075845088U, // USHRvvi_2S
|
|
2150635488U, // USHRvvi_4H
|
|
3225425888U, // USHRvvi_4S
|
|
3226474464U, // USHRvvi_8B
|
|
1080039392U, // USHRvvi_8H
|
|
67113829U, // USQADD16b
|
|
1141904229U, // USQADD2d
|
|
2216694629U, // USQADD2s
|
|
3291485029U, // USQADD4h
|
|
71308133U, // USQADD4s
|
|
1146098533U, // USQADD8b
|
|
2220888933U, // USQADD8h
|
|
3463455589U, // USQADDbb
|
|
3463455589U, // USQADDdd
|
|
3463455589U, // USQADDhh
|
|
3463455589U, // USQADDss
|
|
242229780U, // USRA
|
|
67113492U, // USRAvvi_16B
|
|
2215645716U, // USRAvvi_2D
|
|
1142952468U, // USRAvvi_2S
|
|
2217742868U, // USRAvvi_4H
|
|
3292533268U, // USRAvvi_4S
|
|
3293581844U, // USRAvvi_8B
|
|
1147146772U, // USRAvvi_8H
|
|
3222278292U, // USUBL2vvv_2d4s
|
|
1077940372U, // USUBL2vvv_4s8h
|
|
6295700U, // USUBL2vvv_8h16b
|
|
1074795815U, // USUBLvvv_2d2s
|
|
2151683367U, // USUBLvvv_4s4h
|
|
3227522343U, // USUBLvvv_8h8b
|
|
2148536749U, // USUBW2vvv_2d4s
|
|
3225424301U, // USUBW2vvv_4s8h
|
|
1080037805U, // USUBW2vvv_8h16b
|
|
2148538857U, // USUBWvvv_2d2s
|
|
3225426409U, // USUBWvvv_4s4h
|
|
1080039913U, // USUBWvvv_8h8b
|
|
3262128819U, // UXTBww
|
|
3262128819U, // UXTBxw
|
|
3262129318U, // UXTHww
|
|
3262129318U, // UXTHxw
|
|
4134U, // UZP1vvv_16b
|
|
2148536358U, // UZP1vvv_2d
|
|
1075843110U, // UZP1vvv_2s
|
|
2150633510U, // UZP1vvv_4h
|
|
3225423910U, // UZP1vvv_4s
|
|
3226472486U, // UZP1vvv_8b
|
|
1080037414U, // UZP1vvv_8h
|
|
4499U, // UZP2vvv_16b
|
|
2148536723U, // UZP2vvv_2d
|
|
1075843475U, // UZP2vvv_2s
|
|
2150633875U, // UZP2vvv_4h
|
|
3225424275U, // UZP2vvv_4s
|
|
3226472851U, // UZP2vvv_8b
|
|
1080037779U, // UZP2vvv_8h
|
|
2148538574U, // VCVTf2xs_2D
|
|
1075845326U, // VCVTf2xs_2S
|
|
3225426126U, // VCVTf2xs_4S
|
|
2148538704U, // VCVTf2xu_2D
|
|
1075845456U, // VCVTf2xu_2S
|
|
3225426256U, // VCVTf2xu_4S
|
|
2148537297U, // VCVTxs2f_2D
|
|
1075844049U, // VCVTxs2f_2S
|
|
3225424849U, // VCVTxs2f_4S
|
|
2148537304U, // VCVTxu2f_2D
|
|
1075844056U, // VCVTxu2f_2S
|
|
3225424856U, // VCVTxu2f_4S
|
|
1075844773U, // XTN2d2s
|
|
1145049432U, // XTN2d4s
|
|
3151525U, // XTN4s4h
|
|
73404760U, // XTN4s8h
|
|
2214596952U, // XTN8h16b
|
|
2152732325U, // XTN8h8b
|
|
4128U, // ZIP1vvv_16b
|
|
2148536352U, // ZIP1vvv_2d
|
|
1075843104U, // ZIP1vvv_2s
|
|
2150633504U, // ZIP1vvv_4h
|
|
3225423904U, // ZIP1vvv_4s
|
|
3226472480U, // ZIP1vvv_8b
|
|
1080037408U, // ZIP1vvv_8h
|
|
4493U, // ZIP2vvv_16b
|
|
2148536717U, // ZIP2vvv_2d
|
|
1075843469U, // ZIP2vvv_2s
|
|
2150633869U, // ZIP2vvv_4h
|
|
3225424269U, // ZIP2vvv_4s
|
|
3226472845U, // ZIP2vvv_8b
|
|
1080037773U, // ZIP2vvv_8h
|
|
0U
|
|
};
|
|
|
|
static const uint32_t OpInfo2[] = {
|
|
0U, // PHI
|
|
0U, // INLINEASM
|
|
0U, // PROLOG_LABEL
|
|
0U, // EH_LABEL
|
|
0U, // GC_LABEL
|
|
0U, // KILL
|
|
0U, // EXTRACT_SUBREG
|
|
0U, // INSERT_SUBREG
|
|
0U, // IMPLICIT_DEF
|
|
0U, // SUBREG_TO_REG
|
|
0U, // COPY_TO_REGCLASS
|
|
0U, // DBG_VALUE
|
|
0U, // REG_SEQUENCE
|
|
0U, // COPY
|
|
0U, // BUNDLE
|
|
0U, // LIFETIME_START
|
|
0U, // LIFETIME_END
|
|
0U, // STACKMAP
|
|
0U, // PATCHPOINT
|
|
0U, // ABS16b
|
|
0U, // ABS2d
|
|
0U, // ABS2s
|
|
0U, // ABS4h
|
|
1U, // ABS4s
|
|
1U, // ABS8b
|
|
1U, // ABS8h
|
|
1U, // ABSdd
|
|
2U, // ADCSwww
|
|
2U, // ADCSxxx
|
|
2U, // ADCwww
|
|
2U, // ADCxxx
|
|
522U, // ADDHN2vvv_16b8h
|
|
1034U, // ADDHN2vvv_4s2d
|
|
1546U, // ADDHN2vvv_8h4s
|
|
1042U, // ADDHNvvv_2s2d
|
|
1554U, // ADDHNvvv_4h4s
|
|
530U, // ADDHNvvv_8b8h
|
|
2067U, // ADDP_16B
|
|
1042U, // ADDP_2D
|
|
2579U, // ADDP_2S
|
|
3091U, // ADDP_4H
|
|
1554U, // ADDP_4S
|
|
3603U, // ADDP_8B
|
|
530U, // ADDP_8H
|
|
0U, // ADDPvv_D_2D
|
|
4098U, // ADDSwww_asr
|
|
20482U, // ADDSwww_lsl
|
|
36866U, // ADDSwww_lsr
|
|
53250U, // ADDSwww_sxtb
|
|
69634U, // ADDSwww_sxth
|
|
86018U, // ADDSwww_sxtw
|
|
102402U, // ADDSwww_sxtx
|
|
118786U, // ADDSwww_uxtb
|
|
135170U, // ADDSwww_uxth
|
|
151554U, // ADDSwww_uxtw
|
|
167938U, // ADDSwww_uxtx
|
|
53250U, // ADDSxxw_sxtb
|
|
69634U, // ADDSxxw_sxth
|
|
86018U, // ADDSxxw_sxtw
|
|
118786U, // ADDSxxw_uxtb
|
|
135170U, // ADDSxxw_uxth
|
|
151554U, // ADDSxxw_uxtw
|
|
4098U, // ADDSxxx_asr
|
|
20482U, // ADDSxxx_lsl
|
|
36866U, // ADDSxxx_lsr
|
|
102402U, // ADDSxxx_sxtx
|
|
167938U, // ADDSxxx_uxtx
|
|
0U, // ADDV_1b16b
|
|
1U, // ADDV_1b8b
|
|
0U, // ADDV_1h4h
|
|
1U, // ADDV_1h8h
|
|
1U, // ADDV_1s4s
|
|
2U, // ADDddd
|
|
2067U, // ADDvvv_16B
|
|
1042U, // ADDvvv_2D
|
|
2579U, // ADDvvv_2S
|
|
3091U, // ADDvvv_4H
|
|
1554U, // ADDvvv_4S
|
|
3603U, // ADDvvv_8B
|
|
530U, // ADDvvv_8H
|
|
26U, // ADDwwi_lsl0_S
|
|
0U, // ADDwwi_lsl0_cmp
|
|
26U, // ADDwwi_lsl0_s
|
|
34U, // ADDwwi_lsl12_S
|
|
0U, // ADDwwi_lsl12_cmp
|
|
34U, // ADDwwi_lsl12_s
|
|
4098U, // ADDwww_asr
|
|
20482U, // ADDwww_lsl
|
|
36866U, // ADDwww_lsr
|
|
53250U, // ADDwww_sxtb
|
|
69634U, // ADDwww_sxth
|
|
86018U, // ADDwww_sxtw
|
|
102402U, // ADDwww_sxtx
|
|
118786U, // ADDwww_uxtb
|
|
135170U, // ADDwww_uxth
|
|
151554U, // ADDwww_uxtw
|
|
167938U, // ADDwww_uxtx
|
|
26U, // ADDxxi_lsl0_S
|
|
0U, // ADDxxi_lsl0_cmp
|
|
26U, // ADDxxi_lsl0_s
|
|
34U, // ADDxxi_lsl12_S
|
|
0U, // ADDxxi_lsl12_cmp
|
|
34U, // ADDxxi_lsl12_s
|
|
53250U, // ADDxxw_sxtb
|
|
69634U, // ADDxxw_sxth
|
|
86018U, // ADDxxw_sxtw
|
|
118786U, // ADDxxw_uxtb
|
|
135170U, // ADDxxw_uxth
|
|
151554U, // ADDxxw_uxtw
|
|
4098U, // ADDxxx_asr
|
|
20482U, // ADDxxx_lsl
|
|
36866U, // ADDxxx_lsr
|
|
102402U, // ADDxxx_sxtx
|
|
167938U, // ADDxxx_uxtx
|
|
0U, // ADJCALLSTACKDOWN
|
|
0U, // ADJCALLSTACKUP
|
|
0U, // ADRPxi
|
|
0U, // ADRxi
|
|
0U, // AESD
|
|
0U, // AESE
|
|
0U, // AESIMC
|
|
0U, // AESMC
|
|
42U, // ANDSwwi
|
|
4098U, // ANDSwww_asr
|
|
20482U, // ANDSwww_lsl
|
|
36866U, // ANDSwww_lsr
|
|
184322U, // ANDSwww_ror
|
|
50U, // ANDSxxi
|
|
4098U, // ANDSxxx_asr
|
|
20482U, // ANDSxxx_lsl
|
|
36866U, // ANDSxxx_lsr
|
|
184322U, // ANDSxxx_ror
|
|
2067U, // ANDvvv_16B
|
|
3603U, // ANDvvv_8B
|
|
42U, // ANDwwi
|
|
4098U, // ANDwww_asr
|
|
20482U, // ANDwww_lsl
|
|
36866U, // ANDwww_lsr
|
|
184322U, // ANDwww_ror
|
|
50U, // ANDxxi
|
|
4098U, // ANDxxx_asr
|
|
20482U, // ANDxxx_lsl
|
|
36866U, // ANDxxx_lsr
|
|
184322U, // ANDxxx_ror
|
|
2U, // ASRVwww
|
|
2U, // ASRVxxx
|
|
2U, // ASRwwi
|
|
2U, // ASRxxi
|
|
0U, // ATOMIC_CMP_SWAP_I16
|
|
0U, // ATOMIC_CMP_SWAP_I32
|
|
0U, // ATOMIC_CMP_SWAP_I64
|
|
0U, // ATOMIC_CMP_SWAP_I8
|
|
0U, // ATOMIC_LOAD_ADD_I16
|
|
0U, // ATOMIC_LOAD_ADD_I32
|
|
0U, // ATOMIC_LOAD_ADD_I64
|
|
0U, // ATOMIC_LOAD_ADD_I8
|
|
0U, // ATOMIC_LOAD_AND_I16
|
|
0U, // ATOMIC_LOAD_AND_I32
|
|
0U, // ATOMIC_LOAD_AND_I64
|
|
0U, // ATOMIC_LOAD_AND_I8
|
|
0U, // ATOMIC_LOAD_MAX_I16
|
|
0U, // ATOMIC_LOAD_MAX_I32
|
|
0U, // ATOMIC_LOAD_MAX_I64
|
|
0U, // ATOMIC_LOAD_MAX_I8
|
|
0U, // ATOMIC_LOAD_MIN_I16
|
|
0U, // ATOMIC_LOAD_MIN_I32
|
|
0U, // ATOMIC_LOAD_MIN_I64
|
|
0U, // ATOMIC_LOAD_MIN_I8
|
|
0U, // ATOMIC_LOAD_NAND_I16
|
|
0U, // ATOMIC_LOAD_NAND_I32
|
|
0U, // ATOMIC_LOAD_NAND_I64
|
|
0U, // ATOMIC_LOAD_NAND_I8
|
|
0U, // ATOMIC_LOAD_OR_I16
|
|
0U, // ATOMIC_LOAD_OR_I32
|
|
0U, // ATOMIC_LOAD_OR_I64
|
|
0U, // ATOMIC_LOAD_OR_I8
|
|
0U, // ATOMIC_LOAD_SUB_I16
|
|
0U, // ATOMIC_LOAD_SUB_I32
|
|
0U, // ATOMIC_LOAD_SUB_I64
|
|
0U, // ATOMIC_LOAD_SUB_I8
|
|
0U, // ATOMIC_LOAD_UMAX_I16
|
|
0U, // ATOMIC_LOAD_UMAX_I32
|
|
0U, // ATOMIC_LOAD_UMAX_I64
|
|
0U, // ATOMIC_LOAD_UMAX_I8
|
|
0U, // ATOMIC_LOAD_UMIN_I16
|
|
0U, // ATOMIC_LOAD_UMIN_I32
|
|
0U, // ATOMIC_LOAD_UMIN_I64
|
|
0U, // ATOMIC_LOAD_UMIN_I8
|
|
0U, // ATOMIC_LOAD_XOR_I16
|
|
0U, // ATOMIC_LOAD_XOR_I32
|
|
0U, // ATOMIC_LOAD_XOR_I64
|
|
0U, // ATOMIC_LOAD_XOR_I8
|
|
0U, // ATOMIC_SWAP_I16
|
|
0U, // ATOMIC_SWAP_I32
|
|
0U, // ATOMIC_SWAP_I64
|
|
0U, // ATOMIC_SWAP_I8
|
|
0U, // ATix
|
|
58U, // BFIwwii
|
|
66U, // BFIxxii
|
|
200778U, // BFMwwii
|
|
200778U, // BFMxxii
|
|
217162U, // BFXILwwii
|
|
217162U, // BFXILxxii
|
|
4098U, // BICSwww_asr
|
|
20482U, // BICSwww_lsl
|
|
36866U, // BICSwww_lsr
|
|
184322U, // BICSwww_ror
|
|
4098U, // BICSxxx_asr
|
|
20482U, // BICSxxx_lsl
|
|
36866U, // BICSxxx_lsr
|
|
184322U, // BICSxxx_ror
|
|
4U, // BICvi_lsl_2S
|
|
4U, // BICvi_lsl_4H
|
|
4U, // BICvi_lsl_4S
|
|
4U, // BICvi_lsl_8H
|
|
2067U, // BICvvv_16B
|
|
3603U, // BICvvv_8B
|
|
4098U, // BICwww_asr
|
|
20482U, // BICwww_lsl
|
|
36866U, // BICwww_lsr
|
|
184322U, // BICwww_ror
|
|
4098U, // BICxxx_asr
|
|
20482U, // BICxxx_lsl
|
|
36866U, // BICxxx_lsr
|
|
184322U, // BICxxx_ror
|
|
2059U, // BIFvvv_16B
|
|
3595U, // BIFvvv_8B
|
|
2059U, // BITvvv_16B
|
|
3595U, // BITvvv_8B
|
|
0U, // BLRx
|
|
0U, // BLimm
|
|
0U, // BRKi
|
|
0U, // BRx
|
|
2059U, // BSLvvv_16B
|
|
3595U, // BSLvvv_8B
|
|
0U, // Bcc
|
|
0U, // Bimm
|
|
0U, // CBNZw
|
|
0U, // CBNZx
|
|
0U, // CBZw
|
|
0U, // CBZx
|
|
233474U, // CCMNwi
|
|
233474U, // CCMNww
|
|
233474U, // CCMNxi
|
|
233474U, // CCMNxx
|
|
233474U, // CCMPwi
|
|
233474U, // CCMPww
|
|
233474U, // CCMPxi
|
|
233474U, // CCMPxx
|
|
0U, // CLREXi
|
|
0U, // CLS16b
|
|
0U, // CLS2s
|
|
0U, // CLS4h
|
|
1U, // CLS4s
|
|
1U, // CLS8b
|
|
1U, // CLS8h
|
|
1U, // CLSww
|
|
1U, // CLSxx
|
|
0U, // CLZ16b
|
|
0U, // CLZ2s
|
|
0U, // CLZ4h
|
|
1U, // CLZ4s
|
|
1U, // CLZ8b
|
|
1U, // CLZ8h
|
|
1U, // CLZww
|
|
1U, // CLZxx
|
|
2U, // CMEQddd
|
|
82U, // CMEQddi
|
|
83U, // CMEQvvi_16B
|
|
82U, // CMEQvvi_2D
|
|
83U, // CMEQvvi_2S
|
|
83U, // CMEQvvi_4H
|
|
82U, // CMEQvvi_4S
|
|
83U, // CMEQvvi_8B
|
|
82U, // CMEQvvi_8H
|
|
2067U, // CMEQvvv_16B
|
|
1042U, // CMEQvvv_2D
|
|
2579U, // CMEQvvv_2S
|
|
3091U, // CMEQvvv_4H
|
|
1554U, // CMEQvvv_4S
|
|
3603U, // CMEQvvv_8B
|
|
530U, // CMEQvvv_8H
|
|
2U, // CMGEddd
|
|
82U, // CMGEddi
|
|
83U, // CMGEvvi_16B
|
|
82U, // CMGEvvi_2D
|
|
83U, // CMGEvvi_2S
|
|
83U, // CMGEvvi_4H
|
|
82U, // CMGEvvi_4S
|
|
83U, // CMGEvvi_8B
|
|
82U, // CMGEvvi_8H
|
|
2067U, // CMGEvvv_16B
|
|
1042U, // CMGEvvv_2D
|
|
2579U, // CMGEvvv_2S
|
|
3091U, // CMGEvvv_4H
|
|
1554U, // CMGEvvv_4S
|
|
3603U, // CMGEvvv_8B
|
|
530U, // CMGEvvv_8H
|
|
2U, // CMGTddd
|
|
82U, // CMGTddi
|
|
83U, // CMGTvvi_16B
|
|
82U, // CMGTvvi_2D
|
|
83U, // CMGTvvi_2S
|
|
83U, // CMGTvvi_4H
|
|
82U, // CMGTvvi_4S
|
|
83U, // CMGTvvi_8B
|
|
82U, // CMGTvvi_8H
|
|
2067U, // CMGTvvv_16B
|
|
1042U, // CMGTvvv_2D
|
|
2579U, // CMGTvvv_2S
|
|
3091U, // CMGTvvv_4H
|
|
1554U, // CMGTvvv_4S
|
|
3603U, // CMGTvvv_8B
|
|
530U, // CMGTvvv_8H
|
|
2U, // CMHIddd
|
|
2067U, // CMHIvvv_16B
|
|
1042U, // CMHIvvv_2D
|
|
2579U, // CMHIvvv_2S
|
|
3091U, // CMHIvvv_4H
|
|
1554U, // CMHIvvv_4S
|
|
3603U, // CMHIvvv_8B
|
|
530U, // CMHIvvv_8H
|
|
2U, // CMHSddd
|
|
2067U, // CMHSvvv_16B
|
|
1042U, // CMHSvvv_2D
|
|
2579U, // CMHSvvv_2S
|
|
3091U, // CMHSvvv_4H
|
|
1554U, // CMHSvvv_4S
|
|
3603U, // CMHSvvv_8B
|
|
530U, // CMHSvvv_8H
|
|
82U, // CMLEddi
|
|
83U, // CMLEvvi_16B
|
|
82U, // CMLEvvi_2D
|
|
83U, // CMLEvvi_2S
|
|
83U, // CMLEvvi_4H
|
|
82U, // CMLEvvi_4S
|
|
83U, // CMLEvvi_8B
|
|
82U, // CMLEvvi_8H
|
|
82U, // CMLTddi
|
|
83U, // CMLTvvi_16B
|
|
82U, // CMLTvvi_2D
|
|
83U, // CMLTvvi_2S
|
|
83U, // CMLTvvi_4H
|
|
82U, // CMLTvvi_4S
|
|
83U, // CMLTvvi_8B
|
|
82U, // CMLTvvi_8H
|
|
90U, // CMNww_asr
|
|
98U, // CMNww_lsl
|
|
106U, // CMNww_lsr
|
|
114U, // CMNww_sxtb
|
|
122U, // CMNww_sxth
|
|
130U, // CMNww_sxtw
|
|
138U, // CMNww_sxtx
|
|
146U, // CMNww_uxtb
|
|
154U, // CMNww_uxth
|
|
162U, // CMNww_uxtw
|
|
170U, // CMNww_uxtx
|
|
114U, // CMNxw_sxtb
|
|
122U, // CMNxw_sxth
|
|
130U, // CMNxw_sxtw
|
|
146U, // CMNxw_uxtb
|
|
154U, // CMNxw_uxth
|
|
162U, // CMNxw_uxtw
|
|
90U, // CMNxx_asr
|
|
98U, // CMNxx_lsl
|
|
106U, // CMNxx_lsr
|
|
138U, // CMNxx_sxtx
|
|
170U, // CMNxx_uxtx
|
|
90U, // CMPww_asr
|
|
98U, // CMPww_lsl
|
|
106U, // CMPww_lsr
|
|
114U, // CMPww_sxtb
|
|
122U, // CMPww_sxth
|
|
130U, // CMPww_sxtw
|
|
138U, // CMPww_sxtx
|
|
146U, // CMPww_uxtb
|
|
154U, // CMPww_uxth
|
|
162U, // CMPww_uxtw
|
|
170U, // CMPww_uxtx
|
|
114U, // CMPxw_sxtb
|
|
122U, // CMPxw_sxth
|
|
130U, // CMPxw_sxtw
|
|
146U, // CMPxw_uxtb
|
|
154U, // CMPxw_uxth
|
|
162U, // CMPxw_uxtw
|
|
90U, // CMPxx_asr
|
|
98U, // CMPxx_lsl
|
|
106U, // CMPxx_lsr
|
|
138U, // CMPxx_sxtx
|
|
170U, // CMPxx_uxtx
|
|
2U, // CMTSTddd
|
|
2067U, // CMTSTvvv_16B
|
|
1042U, // CMTSTvvv_2D
|
|
2579U, // CMTSTvvv_2S
|
|
3091U, // CMTSTvvv_4H
|
|
1554U, // CMTSTvvv_4S
|
|
3603U, // CMTSTvvv_8B
|
|
530U, // CMTSTvvv_8H
|
|
0U, // CNT16b
|
|
1U, // CNT8b
|
|
2U, // CRC32B_www
|
|
2U, // CRC32CB_www
|
|
2U, // CRC32CH_www
|
|
2U, // CRC32CW_www
|
|
2U, // CRC32CX_wwx
|
|
2U, // CRC32H_www
|
|
2U, // CRC32W_www
|
|
2U, // CRC32X_wwx
|
|
233474U, // CSELwwwc
|
|
233474U, // CSELxxxc
|
|
233474U, // CSINCwwwc
|
|
233474U, // CSINCxxxc
|
|
233474U, // CSINVwwwc
|
|
233474U, // CSINVxxxc
|
|
233474U, // CSNEGwwwc
|
|
233474U, // CSNEGxxxc
|
|
0U, // DCPS1i
|
|
0U, // DCPS2i
|
|
0U, // DCPS3i
|
|
0U, // DCix
|
|
0U, // DMBi
|
|
0U, // DRPS
|
|
0U, // DSBi
|
|
1U, // DUP16b
|
|
1U, // DUP2d
|
|
1U, // DUP2s
|
|
1U, // DUP4h
|
|
1U, // DUP4s
|
|
1U, // DUP8b
|
|
1U, // DUP8h
|
|
180U, // DUPELT16b
|
|
180U, // DUPELT2d
|
|
181U, // DUPELT2s
|
|
181U, // DUPELT4h
|
|
181U, // DUPELT4s
|
|
180U, // DUPELT8b
|
|
181U, // DUPELT8h
|
|
180U, // DUPbv_B
|
|
180U, // DUPdv_D
|
|
181U, // DUPhv_H
|
|
181U, // DUPsv_S
|
|
4098U, // EONwww_asr
|
|
20482U, // EONwww_lsl
|
|
36866U, // EONwww_lsr
|
|
184322U, // EONwww_ror
|
|
4098U, // EONxxx_asr
|
|
20482U, // EONxxx_lsl
|
|
36866U, // EONxxx_lsr
|
|
184322U, // EONxxx_ror
|
|
2067U, // EORvvv_16B
|
|
3603U, // EORvvv_8B
|
|
42U, // EORwwi
|
|
4098U, // EORwww_asr
|
|
20482U, // EORwww_lsl
|
|
36866U, // EORwww_lsr
|
|
184322U, // EORwww_ror
|
|
50U, // EORxxi
|
|
4098U, // EORxxx_asr
|
|
20482U, // EORxxx_lsl
|
|
36866U, // EORxxx_lsr
|
|
184322U, // EORxxx_ror
|
|
0U, // ERET
|
|
249858U, // EXTRwwwi
|
|
249858U, // EXTRxxxi
|
|
4627U, // EXTvvvi_16b
|
|
5139U, // EXTvvvi_8b
|
|
0U, // F128CSEL
|
|
2U, // FABDddd
|
|
2U, // FABDsss
|
|
1042U, // FABDvvv_2D
|
|
2579U, // FABDvvv_2S
|
|
1554U, // FABDvvv_4S
|
|
0U, // FABS2d
|
|
0U, // FABS2s
|
|
1U, // FABS4s
|
|
1U, // FABSdd
|
|
1U, // FABSss
|
|
2U, // FACGEddd
|
|
2U, // FACGEsss
|
|
1042U, // FACGEvvv_2D
|
|
2579U, // FACGEvvv_2S
|
|
1554U, // FACGEvvv_4S
|
|
2U, // FACGTddd
|
|
2U, // FACGTsss
|
|
1042U, // FACGTvvv_2D
|
|
2579U, // FACGTvvv_2S
|
|
1554U, // FACGTvvv_4S
|
|
1042U, // FADDP_2D
|
|
2579U, // FADDP_2S
|
|
1554U, // FADDP_4S
|
|
0U, // FADDPvv_D_2D
|
|
0U, // FADDPvv_S_2S
|
|
2U, // FADDddd
|
|
2U, // FADDsss
|
|
1042U, // FADDvvv_2D
|
|
2579U, // FADDvvv_2S
|
|
1554U, // FADDvvv_4S
|
|
233474U, // FCCMPEdd
|
|
233474U, // FCCMPEss
|
|
233474U, // FCCMPdd
|
|
233474U, // FCCMPss
|
|
186U, // FCMEQZddi
|
|
186U, // FCMEQZssi
|
|
2U, // FCMEQddd
|
|
2U, // FCMEQsss
|
|
186U, // FCMEQvvi_2D
|
|
187U, // FCMEQvvi_2S
|
|
186U, // FCMEQvvi_4S
|
|
1042U, // FCMEQvvv_2D
|
|
2579U, // FCMEQvvv_2S
|
|
1554U, // FCMEQvvv_4S
|
|
186U, // FCMGEZddi
|
|
186U, // FCMGEZssi
|
|
2U, // FCMGEddd
|
|
2U, // FCMGEsss
|
|
186U, // FCMGEvvi_2D
|
|
187U, // FCMGEvvi_2S
|
|
186U, // FCMGEvvi_4S
|
|
1042U, // FCMGEvvv_2D
|
|
2579U, // FCMGEvvv_2S
|
|
1554U, // FCMGEvvv_4S
|
|
186U, // FCMGTZddi
|
|
186U, // FCMGTZssi
|
|
2U, // FCMGTddd
|
|
2U, // FCMGTsss
|
|
186U, // FCMGTvvi_2D
|
|
187U, // FCMGTvvi_2S
|
|
186U, // FCMGTvvi_4S
|
|
1042U, // FCMGTvvv_2D
|
|
2579U, // FCMGTvvv_2S
|
|
1554U, // FCMGTvvv_4S
|
|
186U, // FCMLEZddi
|
|
186U, // FCMLEZssi
|
|
186U, // FCMLEvvi_2D
|
|
187U, // FCMLEvvi_2S
|
|
186U, // FCMLEvvi_4S
|
|
186U, // FCMLTZddi
|
|
186U, // FCMLTZssi
|
|
186U, // FCMLTvvi_2D
|
|
187U, // FCMLTvvi_2S
|
|
186U, // FCMLTvvi_4S
|
|
1U, // FCMPdd_quiet
|
|
1U, // FCMPdd_sig
|
|
0U, // FCMPdi_quiet
|
|
0U, // FCMPdi_sig
|
|
0U, // FCMPsi_quiet
|
|
0U, // FCMPsi_sig
|
|
1U, // FCMPss_quiet
|
|
1U, // FCMPss_sig
|
|
233474U, // FCSELdddc
|
|
233474U, // FCSELsssc
|
|
0U, // FCVTAS_2d
|
|
0U, // FCVTAS_2s
|
|
1U, // FCVTAS_4s
|
|
1U, // FCVTASdd
|
|
1U, // FCVTASss
|
|
1U, // FCVTASwd
|
|
1U, // FCVTASws
|
|
1U, // FCVTASxd
|
|
1U, // FCVTASxs
|
|
0U, // FCVTAU_2d
|
|
0U, // FCVTAU_2s
|
|
1U, // FCVTAU_4s
|
|
1U, // FCVTAUdd
|
|
1U, // FCVTAUss
|
|
1U, // FCVTAUwd
|
|
1U, // FCVTAUws
|
|
1U, // FCVTAUxd
|
|
1U, // FCVTAUxs
|
|
0U, // FCVTL2s2d
|
|
0U, // FCVTL4h4s
|
|
1U, // FCVTL4s2d
|
|
1U, // FCVTL8h4s
|
|
0U, // FCVTMS_2d
|
|
0U, // FCVTMS_2s
|
|
1U, // FCVTMS_4s
|
|
1U, // FCVTMSdd
|
|
1U, // FCVTMSss
|
|
1U, // FCVTMSwd
|
|
1U, // FCVTMSws
|
|
1U, // FCVTMSxd
|
|
1U, // FCVTMSxs
|
|
0U, // FCVTMU_2d
|
|
0U, // FCVTMU_2s
|
|
1U, // FCVTMU_4s
|
|
1U, // FCVTMUdd
|
|
1U, // FCVTMUss
|
|
1U, // FCVTMUwd
|
|
1U, // FCVTMUws
|
|
1U, // FCVTMUxd
|
|
1U, // FCVTMUxs
|
|
0U, // FCVTN2d2s
|
|
0U, // FCVTN2d4s
|
|
1U, // FCVTN4s4h
|
|
1U, // FCVTN4s8h
|
|
0U, // FCVTNS_2d
|
|
0U, // FCVTNS_2s
|
|
1U, // FCVTNS_4s
|
|
1U, // FCVTNSdd
|
|
1U, // FCVTNSss
|
|
1U, // FCVTNSwd
|
|
1U, // FCVTNSws
|
|
1U, // FCVTNSxd
|
|
1U, // FCVTNSxs
|
|
0U, // FCVTNU_2d
|
|
0U, // FCVTNU_2s
|
|
1U, // FCVTNU_4s
|
|
1U, // FCVTNUdd
|
|
1U, // FCVTNUss
|
|
1U, // FCVTNUwd
|
|
1U, // FCVTNUws
|
|
1U, // FCVTNUxd
|
|
1U, // FCVTNUxs
|
|
0U, // FCVTPS_2d
|
|
0U, // FCVTPS_2s
|
|
1U, // FCVTPS_4s
|
|
1U, // FCVTPSdd
|
|
1U, // FCVTPSss
|
|
1U, // FCVTPSwd
|
|
1U, // FCVTPSws
|
|
1U, // FCVTPSxd
|
|
1U, // FCVTPSxs
|
|
0U, // FCVTPU_2d
|
|
0U, // FCVTPU_2s
|
|
1U, // FCVTPU_4s
|
|
1U, // FCVTPUdd
|
|
1U, // FCVTPUss
|
|
1U, // FCVTPUwd
|
|
1U, // FCVTPUws
|
|
1U, // FCVTPUxd
|
|
1U, // FCVTPUxs
|
|
1U, // FCVTXN
|
|
0U, // FCVTXN2d2s
|
|
0U, // FCVTXN2d4s
|
|
0U, // FCVTZS_2d
|
|
0U, // FCVTZS_2s
|
|
1U, // FCVTZS_4s
|
|
2U, // FCVTZS_Nddi
|
|
2U, // FCVTZS_Nssi
|
|
1U, // FCVTZSdd
|
|
1U, // FCVTZSss
|
|
1U, // FCVTZSwd
|
|
194U, // FCVTZSwdi
|
|
1U, // FCVTZSws
|
|
194U, // FCVTZSwsi
|
|
1U, // FCVTZSxd
|
|
194U, // FCVTZSxdi
|
|
1U, // FCVTZSxs
|
|
194U, // FCVTZSxsi
|
|
0U, // FCVTZU_2d
|
|
0U, // FCVTZU_2s
|
|
1U, // FCVTZU_4s
|
|
2U, // FCVTZU_Nddi
|
|
2U, // FCVTZU_Nssi
|
|
1U, // FCVTZUdd
|
|
1U, // FCVTZUss
|
|
1U, // FCVTZUwd
|
|
194U, // FCVTZUwdi
|
|
1U, // FCVTZUws
|
|
194U, // FCVTZUwsi
|
|
1U, // FCVTZUxd
|
|
194U, // FCVTZUxdi
|
|
1U, // FCVTZUxs
|
|
194U, // FCVTZUxsi
|
|
1U, // FCVTdh
|
|
1U, // FCVTds
|
|
1U, // FCVThd
|
|
1U, // FCVThs
|
|
1U, // FCVTsd
|
|
1U, // FCVTsh
|
|
2U, // FDIVddd
|
|
2U, // FDIVsss
|
|
1042U, // FDIVvvv_2D
|
|
2579U, // FDIVvvv_2S
|
|
1554U, // FDIVvvv_4S
|
|
249858U, // FMADDdddd
|
|
249858U, // FMADDssss
|
|
0U, // FMAXNMPvv_D_2D
|
|
0U, // FMAXNMPvv_S_2S
|
|
1042U, // FMAXNMPvvv_2D
|
|
2579U, // FMAXNMPvvv_2S
|
|
1554U, // FMAXNMPvvv_4S
|
|
1U, // FMAXNMV_1s4s
|
|
2U, // FMAXNMddd
|
|
2U, // FMAXNMsss
|
|
1042U, // FMAXNMvvv_2D
|
|
2579U, // FMAXNMvvv_2S
|
|
1554U, // FMAXNMvvv_4S
|
|
0U, // FMAXPvv_D_2D
|
|
0U, // FMAXPvv_S_2S
|
|
1042U, // FMAXPvvv_2D
|
|
2579U, // FMAXPvvv_2S
|
|
1554U, // FMAXPvvv_4S
|
|
1U, // FMAXV_1s4s
|
|
2U, // FMAXddd
|
|
2U, // FMAXsss
|
|
1042U, // FMAXvvv_2D
|
|
2579U, // FMAXvvv_2S
|
|
1554U, // FMAXvvv_4S
|
|
0U, // FMINNMPvv_D_2D
|
|
0U, // FMINNMPvv_S_2S
|
|
1042U, // FMINNMPvvv_2D
|
|
2579U, // FMINNMPvvv_2S
|
|
1554U, // FMINNMPvvv_4S
|
|
1U, // FMINNMV_1s4s
|
|
2U, // FMINNMddd
|
|
2U, // FMINNMsss
|
|
1042U, // FMINNMvvv_2D
|
|
2579U, // FMINNMvvv_2S
|
|
1554U, // FMINNMvvv_4S
|
|
0U, // FMINPvv_D_2D
|
|
0U, // FMINPvv_S_2S
|
|
1042U, // FMINPvvv_2D
|
|
2579U, // FMINPvvv_2S
|
|
1554U, // FMINPvvv_4S
|
|
1U, // FMINV_1s4s
|
|
2U, // FMINddd
|
|
2U, // FMINsss
|
|
1042U, // FMINvvv_2D
|
|
2579U, // FMINvvv_2S
|
|
1554U, // FMINvvv_4S
|
|
267786U, // FMLAddv_2D
|
|
268298U, // FMLAssv_4S
|
|
267786U, // FMLAvve_2d2d
|
|
268299U, // FMLAvve_2s4s
|
|
268298U, // FMLAvve_4s4s
|
|
1034U, // FMLAvvv_2D
|
|
2571U, // FMLAvvv_2S
|
|
1546U, // FMLAvvv_4S
|
|
267786U, // FMLSddv_2D
|
|
268298U, // FMLSssv_4S
|
|
267786U, // FMLSvve_2d2d
|
|
268299U, // FMLSvve_2s4s
|
|
268298U, // FMLSvve_4s4s
|
|
1034U, // FMLSvvv_2D
|
|
2571U, // FMLSvvv_2S
|
|
1546U, // FMLSvvv_4S
|
|
1U, // FMOVdd
|
|
0U, // FMOVdi
|
|
1U, // FMOVdx
|
|
0U, // FMOVsi
|
|
1U, // FMOVss
|
|
1U, // FMOVsw
|
|
0U, // FMOVvi_2D
|
|
0U, // FMOVvi_2S
|
|
0U, // FMOVvi_4S
|
|
0U, // FMOVvx
|
|
1U, // FMOVws
|
|
1U, // FMOVxd
|
|
204U, // FMOVxv
|
|
249858U, // FMSUBdddd
|
|
249858U, // FMSUBssss
|
|
2U, // FMULXddd
|
|
284178U, // FMULXddv_2D
|
|
2U, // FMULXsss
|
|
284690U, // FMULXssv_4S
|
|
284178U, // FMULXve_2d2d
|
|
284691U, // FMULXve_2s4s
|
|
284690U, // FMULXve_4s4s
|
|
1042U, // FMULXvvv_2D
|
|
2579U, // FMULXvvv_2S
|
|
1554U, // FMULXvvv_4S
|
|
2U, // FMULddd
|
|
284178U, // FMULddv_2D
|
|
2U, // FMULsss
|
|
284690U, // FMULssv_4S
|
|
284178U, // FMULve_2d2d
|
|
284691U, // FMULve_2s4s
|
|
284690U, // FMULve_4s4s
|
|
1042U, // FMULvvv_2D
|
|
2579U, // FMULvvv_2S
|
|
1554U, // FMULvvv_4S
|
|
0U, // FNEG2d
|
|
0U, // FNEG2s
|
|
1U, // FNEG4s
|
|
1U, // FNEGdd
|
|
1U, // FNEGss
|
|
249858U, // FNMADDdddd
|
|
249858U, // FNMADDssss
|
|
249858U, // FNMSUBdddd
|
|
249858U, // FNMSUBssss
|
|
2U, // FNMULddd
|
|
2U, // FNMULsss
|
|
0U, // FRECPE_2d
|
|
0U, // FRECPE_2s
|
|
1U, // FRECPE_4s
|
|
1U, // FRECPEdd
|
|
1U, // FRECPEss
|
|
2U, // FRECPSddd
|
|
2U, // FRECPSsss
|
|
1042U, // FRECPSvvv_2D
|
|
2579U, // FRECPSvvv_2S
|
|
1554U, // FRECPSvvv_4S
|
|
1U, // FRECPXdd
|
|
1U, // FRECPXss
|
|
0U, // FRINTA_2d
|
|
0U, // FRINTA_2s
|
|
1U, // FRINTA_4s
|
|
1U, // FRINTAdd
|
|
1U, // FRINTAss
|
|
0U, // FRINTI_2d
|
|
0U, // FRINTI_2s
|
|
1U, // FRINTI_4s
|
|
1U, // FRINTIdd
|
|
1U, // FRINTIss
|
|
0U, // FRINTM_2d
|
|
0U, // FRINTM_2s
|
|
1U, // FRINTM_4s
|
|
1U, // FRINTMdd
|
|
1U, // FRINTMss
|
|
0U, // FRINTN_2d
|
|
0U, // FRINTN_2s
|
|
1U, // FRINTN_4s
|
|
1U, // FRINTNdd
|
|
1U, // FRINTNss
|
|
0U, // FRINTP_2d
|
|
0U, // FRINTP_2s
|
|
1U, // FRINTP_4s
|
|
1U, // FRINTPdd
|
|
1U, // FRINTPss
|
|
0U, // FRINTX_2d
|
|
0U, // FRINTX_2s
|
|
1U, // FRINTX_4s
|
|
1U, // FRINTXdd
|
|
1U, // FRINTXss
|
|
0U, // FRINTZ_2d
|
|
0U, // FRINTZ_2s
|
|
1U, // FRINTZ_4s
|
|
1U, // FRINTZdd
|
|
1U, // FRINTZss
|
|
0U, // FRSQRTE_2d
|
|
0U, // FRSQRTE_2s
|
|
1U, // FRSQRTE_4s
|
|
1U, // FRSQRTEdd
|
|
1U, // FRSQRTEss
|
|
2U, // FRSQRTSddd
|
|
2U, // FRSQRTSsss
|
|
1042U, // FRSQRTSvvv_2D
|
|
2579U, // FRSQRTSvvv_2S
|
|
1554U, // FRSQRTSvvv_4S
|
|
0U, // FSQRT_2d
|
|
0U, // FSQRT_2s
|
|
1U, // FSQRT_4s
|
|
1U, // FSQRTdd
|
|
1U, // FSQRTss
|
|
2U, // FSUBddd
|
|
2U, // FSUBsss
|
|
1042U, // FSUBvvv_2D
|
|
2579U, // FSUBvvv_2S
|
|
1554U, // FSUBvvv_4S
|
|
0U, // HINTi
|
|
0U, // HLTi
|
|
0U, // HVCi
|
|
0U, // ICi
|
|
1U, // ICix
|
|
212U, // INSELb
|
|
5U, // INSELd
|
|
213U, // INSELh
|
|
213U, // INSELs
|
|
1U, // INSbw
|
|
5U, // INSdx
|
|
1U, // INShw
|
|
1U, // INSsw
|
|
0U, // ISBi
|
|
0U, // LD1LN_B
|
|
0U, // LD1LN_D
|
|
0U, // LD1LN_H
|
|
0U, // LD1LN_S
|
|
0U, // LD1LN_WB_B_fixed
|
|
0U, // LD1LN_WB_B_register
|
|
0U, // LD1LN_WB_D_fixed
|
|
0U, // LD1LN_WB_D_register
|
|
0U, // LD1LN_WB_H_fixed
|
|
0U, // LD1LN_WB_H_register
|
|
0U, // LD1LN_WB_S_fixed
|
|
0U, // LD1LN_WB_S_register
|
|
0U, // LD1R_16B
|
|
0U, // LD1R_1D
|
|
0U, // LD1R_2D
|
|
0U, // LD1R_2S
|
|
0U, // LD1R_4H
|
|
0U, // LD1R_4S
|
|
0U, // LD1R_8B
|
|
0U, // LD1R_8H
|
|
0U, // LD1R_WB_16B_fixed
|
|
0U, // LD1R_WB_16B_register
|
|
0U, // LD1R_WB_1D_fixed
|
|
0U, // LD1R_WB_1D_register
|
|
0U, // LD1R_WB_2D_fixed
|
|
0U, // LD1R_WB_2D_register
|
|
0U, // LD1R_WB_2S_fixed
|
|
0U, // LD1R_WB_2S_register
|
|
0U, // LD1R_WB_4H_fixed
|
|
0U, // LD1R_WB_4H_register
|
|
0U, // LD1R_WB_4S_fixed
|
|
0U, // LD1R_WB_4S_register
|
|
0U, // LD1R_WB_8B_fixed
|
|
0U, // LD1R_WB_8B_register
|
|
0U, // LD1R_WB_8H_fixed
|
|
0U, // LD1R_WB_8H_register
|
|
0U, // LD1WB_16B_fixed
|
|
0U, // LD1WB_16B_register
|
|
0U, // LD1WB_1D_fixed
|
|
0U, // LD1WB_1D_register
|
|
0U, // LD1WB_2D_fixed
|
|
0U, // LD1WB_2D_register
|
|
0U, // LD1WB_2S_fixed
|
|
0U, // LD1WB_2S_register
|
|
0U, // LD1WB_4H_fixed
|
|
0U, // LD1WB_4H_register
|
|
0U, // LD1WB_4S_fixed
|
|
0U, // LD1WB_4S_register
|
|
0U, // LD1WB_8B_fixed
|
|
0U, // LD1WB_8B_register
|
|
0U, // LD1WB_8H_fixed
|
|
0U, // LD1WB_8H_register
|
|
0U, // LD1_16B
|
|
0U, // LD1_1D
|
|
0U, // LD1_2D
|
|
0U, // LD1_2S
|
|
0U, // LD1_4H
|
|
0U, // LD1_4S
|
|
0U, // LD1_8B
|
|
0U, // LD1_8H
|
|
0U, // LD1x2WB_16B_fixed
|
|
0U, // LD1x2WB_16B_register
|
|
0U, // LD1x2WB_1D_fixed
|
|
0U, // LD1x2WB_1D_register
|
|
0U, // LD1x2WB_2D_fixed
|
|
0U, // LD1x2WB_2D_register
|
|
0U, // LD1x2WB_2S_fixed
|
|
0U, // LD1x2WB_2S_register
|
|
0U, // LD1x2WB_4H_fixed
|
|
0U, // LD1x2WB_4H_register
|
|
0U, // LD1x2WB_4S_fixed
|
|
0U, // LD1x2WB_4S_register
|
|
0U, // LD1x2WB_8B_fixed
|
|
0U, // LD1x2WB_8B_register
|
|
0U, // LD1x2WB_8H_fixed
|
|
0U, // LD1x2WB_8H_register
|
|
0U, // LD1x2_16B
|
|
0U, // LD1x2_1D
|
|
0U, // LD1x2_2D
|
|
0U, // LD1x2_2S
|
|
0U, // LD1x2_4H
|
|
0U, // LD1x2_4S
|
|
0U, // LD1x2_8B
|
|
0U, // LD1x2_8H
|
|
0U, // LD1x3WB_16B_fixed
|
|
0U, // LD1x3WB_16B_register
|
|
0U, // LD1x3WB_1D_fixed
|
|
0U, // LD1x3WB_1D_register
|
|
0U, // LD1x3WB_2D_fixed
|
|
0U, // LD1x3WB_2D_register
|
|
0U, // LD1x3WB_2S_fixed
|
|
0U, // LD1x3WB_2S_register
|
|
0U, // LD1x3WB_4H_fixed
|
|
0U, // LD1x3WB_4H_register
|
|
0U, // LD1x3WB_4S_fixed
|
|
0U, // LD1x3WB_4S_register
|
|
0U, // LD1x3WB_8B_fixed
|
|
0U, // LD1x3WB_8B_register
|
|
0U, // LD1x3WB_8H_fixed
|
|
0U, // LD1x3WB_8H_register
|
|
0U, // LD1x3_16B
|
|
0U, // LD1x3_1D
|
|
0U, // LD1x3_2D
|
|
0U, // LD1x3_2S
|
|
0U, // LD1x3_4H
|
|
0U, // LD1x3_4S
|
|
0U, // LD1x3_8B
|
|
0U, // LD1x3_8H
|
|
0U, // LD1x4WB_16B_fixed
|
|
0U, // LD1x4WB_16B_register
|
|
0U, // LD1x4WB_1D_fixed
|
|
0U, // LD1x4WB_1D_register
|
|
0U, // LD1x4WB_2D_fixed
|
|
0U, // LD1x4WB_2D_register
|
|
0U, // LD1x4WB_2S_fixed
|
|
0U, // LD1x4WB_2S_register
|
|
0U, // LD1x4WB_4H_fixed
|
|
0U, // LD1x4WB_4H_register
|
|
0U, // LD1x4WB_4S_fixed
|
|
0U, // LD1x4WB_4S_register
|
|
0U, // LD1x4WB_8B_fixed
|
|
0U, // LD1x4WB_8B_register
|
|
0U, // LD1x4WB_8H_fixed
|
|
0U, // LD1x4WB_8H_register
|
|
0U, // LD1x4_16B
|
|
0U, // LD1x4_1D
|
|
0U, // LD1x4_2D
|
|
0U, // LD1x4_2S
|
|
0U, // LD1x4_4H
|
|
0U, // LD1x4_4S
|
|
0U, // LD1x4_8B
|
|
0U, // LD1x4_8H
|
|
0U, // LD2LN_B
|
|
0U, // LD2LN_D
|
|
0U, // LD2LN_H
|
|
0U, // LD2LN_S
|
|
0U, // LD2LN_WB_B_fixed
|
|
0U, // LD2LN_WB_B_register
|
|
0U, // LD2LN_WB_D_fixed
|
|
0U, // LD2LN_WB_D_register
|
|
0U, // LD2LN_WB_H_fixed
|
|
0U, // LD2LN_WB_H_register
|
|
0U, // LD2LN_WB_S_fixed
|
|
0U, // LD2LN_WB_S_register
|
|
0U, // LD2R_16B
|
|
0U, // LD2R_1D
|
|
0U, // LD2R_2D
|
|
0U, // LD2R_2S
|
|
0U, // LD2R_4H
|
|
0U, // LD2R_4S
|
|
0U, // LD2R_8B
|
|
0U, // LD2R_8H
|
|
0U, // LD2R_WB_16B_fixed
|
|
0U, // LD2R_WB_16B_register
|
|
0U, // LD2R_WB_1D_fixed
|
|
0U, // LD2R_WB_1D_register
|
|
0U, // LD2R_WB_2D_fixed
|
|
0U, // LD2R_WB_2D_register
|
|
0U, // LD2R_WB_2S_fixed
|
|
0U, // LD2R_WB_2S_register
|
|
0U, // LD2R_WB_4H_fixed
|
|
0U, // LD2R_WB_4H_register
|
|
0U, // LD2R_WB_4S_fixed
|
|
0U, // LD2R_WB_4S_register
|
|
0U, // LD2R_WB_8B_fixed
|
|
0U, // LD2R_WB_8B_register
|
|
0U, // LD2R_WB_8H_fixed
|
|
0U, // LD2R_WB_8H_register
|
|
0U, // LD2WB_16B_fixed
|
|
0U, // LD2WB_16B_register
|
|
0U, // LD2WB_2D_fixed
|
|
0U, // LD2WB_2D_register
|
|
0U, // LD2WB_2S_fixed
|
|
0U, // LD2WB_2S_register
|
|
0U, // LD2WB_4H_fixed
|
|
0U, // LD2WB_4H_register
|
|
0U, // LD2WB_4S_fixed
|
|
0U, // LD2WB_4S_register
|
|
0U, // LD2WB_8B_fixed
|
|
0U, // LD2WB_8B_register
|
|
0U, // LD2WB_8H_fixed
|
|
0U, // LD2WB_8H_register
|
|
0U, // LD2_16B
|
|
0U, // LD2_2D
|
|
0U, // LD2_2S
|
|
0U, // LD2_4H
|
|
0U, // LD2_4S
|
|
0U, // LD2_8B
|
|
0U, // LD2_8H
|
|
0U, // LD3LN_B
|
|
0U, // LD3LN_D
|
|
0U, // LD3LN_H
|
|
0U, // LD3LN_S
|
|
0U, // LD3LN_WB_B_fixed
|
|
0U, // LD3LN_WB_B_register
|
|
0U, // LD3LN_WB_D_fixed
|
|
0U, // LD3LN_WB_D_register
|
|
0U, // LD3LN_WB_H_fixed
|
|
0U, // LD3LN_WB_H_register
|
|
0U, // LD3LN_WB_S_fixed
|
|
0U, // LD3LN_WB_S_register
|
|
0U, // LD3R_16B
|
|
0U, // LD3R_1D
|
|
0U, // LD3R_2D
|
|
0U, // LD3R_2S
|
|
0U, // LD3R_4H
|
|
0U, // LD3R_4S
|
|
0U, // LD3R_8B
|
|
0U, // LD3R_8H
|
|
0U, // LD3R_WB_16B_fixed
|
|
0U, // LD3R_WB_16B_register
|
|
0U, // LD3R_WB_1D_fixed
|
|
0U, // LD3R_WB_1D_register
|
|
0U, // LD3R_WB_2D_fixed
|
|
0U, // LD3R_WB_2D_register
|
|
0U, // LD3R_WB_2S_fixed
|
|
0U, // LD3R_WB_2S_register
|
|
0U, // LD3R_WB_4H_fixed
|
|
0U, // LD3R_WB_4H_register
|
|
0U, // LD3R_WB_4S_fixed
|
|
0U, // LD3R_WB_4S_register
|
|
0U, // LD3R_WB_8B_fixed
|
|
0U, // LD3R_WB_8B_register
|
|
0U, // LD3R_WB_8H_fixed
|
|
0U, // LD3R_WB_8H_register
|
|
0U, // LD3WB_16B_fixed
|
|
0U, // LD3WB_16B_register
|
|
0U, // LD3WB_2D_fixed
|
|
0U, // LD3WB_2D_register
|
|
0U, // LD3WB_2S_fixed
|
|
0U, // LD3WB_2S_register
|
|
0U, // LD3WB_4H_fixed
|
|
0U, // LD3WB_4H_register
|
|
0U, // LD3WB_4S_fixed
|
|
0U, // LD3WB_4S_register
|
|
0U, // LD3WB_8B_fixed
|
|
0U, // LD3WB_8B_register
|
|
0U, // LD3WB_8H_fixed
|
|
0U, // LD3WB_8H_register
|
|
0U, // LD3_16B
|
|
0U, // LD3_2D
|
|
0U, // LD3_2S
|
|
0U, // LD3_4H
|
|
0U, // LD3_4S
|
|
0U, // LD3_8B
|
|
0U, // LD3_8H
|
|
0U, // LD4LN_B
|
|
0U, // LD4LN_D
|
|
0U, // LD4LN_H
|
|
0U, // LD4LN_S
|
|
0U, // LD4LN_WB_B_fixed
|
|
0U, // LD4LN_WB_B_register
|
|
0U, // LD4LN_WB_D_fixed
|
|
0U, // LD4LN_WB_D_register
|
|
0U, // LD4LN_WB_H_fixed
|
|
0U, // LD4LN_WB_H_register
|
|
0U, // LD4LN_WB_S_fixed
|
|
0U, // LD4LN_WB_S_register
|
|
0U, // LD4R_16B
|
|
0U, // LD4R_1D
|
|
0U, // LD4R_2D
|
|
0U, // LD4R_2S
|
|
0U, // LD4R_4H
|
|
0U, // LD4R_4S
|
|
0U, // LD4R_8B
|
|
0U, // LD4R_8H
|
|
0U, // LD4R_WB_16B_fixed
|
|
0U, // LD4R_WB_16B_register
|
|
0U, // LD4R_WB_1D_fixed
|
|
0U, // LD4R_WB_1D_register
|
|
0U, // LD4R_WB_2D_fixed
|
|
0U, // LD4R_WB_2D_register
|
|
0U, // LD4R_WB_2S_fixed
|
|
0U, // LD4R_WB_2S_register
|
|
0U, // LD4R_WB_4H_fixed
|
|
0U, // LD4R_WB_4H_register
|
|
0U, // LD4R_WB_4S_fixed
|
|
0U, // LD4R_WB_4S_register
|
|
0U, // LD4R_WB_8B_fixed
|
|
0U, // LD4R_WB_8B_register
|
|
0U, // LD4R_WB_8H_fixed
|
|
0U, // LD4R_WB_8H_register
|
|
0U, // LD4WB_16B_fixed
|
|
0U, // LD4WB_16B_register
|
|
0U, // LD4WB_2D_fixed
|
|
0U, // LD4WB_2D_register
|
|
0U, // LD4WB_2S_fixed
|
|
0U, // LD4WB_2S_register
|
|
0U, // LD4WB_4H_fixed
|
|
0U, // LD4WB_4H_register
|
|
0U, // LD4WB_4S_fixed
|
|
0U, // LD4WB_4S_register
|
|
0U, // LD4WB_8B_fixed
|
|
0U, // LD4WB_8B_register
|
|
0U, // LD4WB_8H_fixed
|
|
0U, // LD4WB_8H_register
|
|
0U, // LD4_16B
|
|
0U, // LD4_2D
|
|
0U, // LD4_2S
|
|
0U, // LD4_4H
|
|
0U, // LD4_4S
|
|
0U, // LD4_8B
|
|
0U, // LD4_8H
|
|
6U, // LDAR_byte
|
|
6U, // LDAR_dword
|
|
6U, // LDAR_hword
|
|
6U, // LDAR_word
|
|
6662U, // LDAXP_dword
|
|
6662U, // LDAXP_word
|
|
6U, // LDAXR_byte
|
|
6U, // LDAXR_dword
|
|
6U, // LDAXR_hword
|
|
6U, // LDAXR_word
|
|
299014U, // LDPSWx
|
|
318542U, // LDPSWx_PostInd
|
|
1364046U, // LDPSWx_PreInd
|
|
218U, // LDRSBw
|
|
6U, // LDRSBw_PostInd
|
|
226U, // LDRSBw_PreInd
|
|
234U, // LDRSBw_U
|
|
331778U, // LDRSBw_Wm_RegOffset
|
|
348162U, // LDRSBw_Xm_RegOffset
|
|
218U, // LDRSBx
|
|
6U, // LDRSBx_PostInd
|
|
226U, // LDRSBx_PreInd
|
|
234U, // LDRSBx_U
|
|
331778U, // LDRSBx_Wm_RegOffset
|
|
348162U, // LDRSBx_Xm_RegOffset
|
|
242U, // LDRSHw
|
|
6U, // LDRSHw_PostInd
|
|
226U, // LDRSHw_PreInd
|
|
234U, // LDRSHw_U
|
|
364546U, // LDRSHw_Wm_RegOffset
|
|
380930U, // LDRSHw_Xm_RegOffset
|
|
242U, // LDRSHx
|
|
6U, // LDRSHx_PostInd
|
|
226U, // LDRSHx_PreInd
|
|
234U, // LDRSHx_U
|
|
364546U, // LDRSHx_Wm_RegOffset
|
|
380930U, // LDRSHx_Xm_RegOffset
|
|
250U, // LDRSWx
|
|
6U, // LDRSWx_PostInd
|
|
226U, // LDRSWx_PreInd
|
|
397314U, // LDRSWx_Wm_RegOffset
|
|
413698U, // LDRSWx_Xm_RegOffset
|
|
0U, // LDRSWx_lit
|
|
0U, // LDRd_lit
|
|
0U, // LDRq_lit
|
|
0U, // LDRs_lit
|
|
0U, // LDRw_lit
|
|
0U, // LDRx_lit
|
|
234U, // LDTRSBw
|
|
234U, // LDTRSBx
|
|
234U, // LDTRSHw
|
|
234U, // LDTRSHx
|
|
234U, // LDTRSWx
|
|
234U, // LDURSWx
|
|
6662U, // LDXP_dword
|
|
6662U, // LDXP_word
|
|
6U, // LDXR_byte
|
|
6U, // LDXR_dword
|
|
6U, // LDXR_hword
|
|
6U, // LDXR_word
|
|
242U, // LS16_LDR
|
|
234U, // LS16_LDUR
|
|
6U, // LS16_PostInd_LDR
|
|
6U, // LS16_PostInd_STR
|
|
226U, // LS16_PreInd_LDR
|
|
226U, // LS16_PreInd_STR
|
|
242U, // LS16_STR
|
|
234U, // LS16_STUR
|
|
234U, // LS16_UnPriv_LDR
|
|
234U, // LS16_UnPriv_STR
|
|
364546U, // LS16_Wm_RegOffset_LDR
|
|
364546U, // LS16_Wm_RegOffset_STR
|
|
380930U, // LS16_Xm_RegOffset_LDR
|
|
380930U, // LS16_Xm_RegOffset_STR
|
|
250U, // LS32_LDR
|
|
234U, // LS32_LDUR
|
|
6U, // LS32_PostInd_LDR
|
|
6U, // LS32_PostInd_STR
|
|
226U, // LS32_PreInd_LDR
|
|
226U, // LS32_PreInd_STR
|
|
250U, // LS32_STR
|
|
234U, // LS32_STUR
|
|
234U, // LS32_UnPriv_LDR
|
|
234U, // LS32_UnPriv_STR
|
|
397314U, // LS32_Wm_RegOffset_LDR
|
|
397314U, // LS32_Wm_RegOffset_STR
|
|
413698U, // LS32_Xm_RegOffset_LDR
|
|
413698U, // LS32_Xm_RegOffset_STR
|
|
258U, // LS64_LDR
|
|
234U, // LS64_LDUR
|
|
6U, // LS64_PostInd_LDR
|
|
6U, // LS64_PostInd_STR
|
|
226U, // LS64_PreInd_LDR
|
|
226U, // LS64_PreInd_STR
|
|
258U, // LS64_STR
|
|
234U, // LS64_STUR
|
|
234U, // LS64_UnPriv_LDR
|
|
234U, // LS64_UnPriv_STR
|
|
430082U, // LS64_Wm_RegOffset_LDR
|
|
430082U, // LS64_Wm_RegOffset_STR
|
|
446466U, // LS64_Xm_RegOffset_LDR
|
|
446466U, // LS64_Xm_RegOffset_STR
|
|
218U, // LS8_LDR
|
|
234U, // LS8_LDUR
|
|
6U, // LS8_PostInd_LDR
|
|
6U, // LS8_PostInd_STR
|
|
226U, // LS8_PreInd_LDR
|
|
226U, // LS8_PreInd_STR
|
|
218U, // LS8_STR
|
|
234U, // LS8_STUR
|
|
234U, // LS8_UnPriv_LDR
|
|
234U, // LS8_UnPriv_STR
|
|
331778U, // LS8_Wm_RegOffset_LDR
|
|
331778U, // LS8_Wm_RegOffset_STR
|
|
348162U, // LS8_Xm_RegOffset_LDR
|
|
348162U, // LS8_Xm_RegOffset_STR
|
|
266U, // LSFP128_LDR
|
|
234U, // LSFP128_LDUR
|
|
6U, // LSFP128_PostInd_LDR
|
|
6U, // LSFP128_PostInd_STR
|
|
226U, // LSFP128_PreInd_LDR
|
|
226U, // LSFP128_PreInd_STR
|
|
266U, // LSFP128_STR
|
|
234U, // LSFP128_STUR
|
|
462850U, // LSFP128_Wm_RegOffset_LDR
|
|
462850U, // LSFP128_Wm_RegOffset_STR
|
|
479234U, // LSFP128_Xm_RegOffset_LDR
|
|
479234U, // LSFP128_Xm_RegOffset_STR
|
|
242U, // LSFP16_LDR
|
|
234U, // LSFP16_LDUR
|
|
6U, // LSFP16_PostInd_LDR
|
|
6U, // LSFP16_PostInd_STR
|
|
226U, // LSFP16_PreInd_LDR
|
|
226U, // LSFP16_PreInd_STR
|
|
242U, // LSFP16_STR
|
|
234U, // LSFP16_STUR
|
|
364546U, // LSFP16_Wm_RegOffset_LDR
|
|
364546U, // LSFP16_Wm_RegOffset_STR
|
|
380930U, // LSFP16_Xm_RegOffset_LDR
|
|
380930U, // LSFP16_Xm_RegOffset_STR
|
|
250U, // LSFP32_LDR
|
|
234U, // LSFP32_LDUR
|
|
6U, // LSFP32_PostInd_LDR
|
|
6U, // LSFP32_PostInd_STR
|
|
226U, // LSFP32_PreInd_LDR
|
|
226U, // LSFP32_PreInd_STR
|
|
250U, // LSFP32_STR
|
|
234U, // LSFP32_STUR
|
|
397314U, // LSFP32_Wm_RegOffset_LDR
|
|
397314U, // LSFP32_Wm_RegOffset_STR
|
|
413698U, // LSFP32_Xm_RegOffset_LDR
|
|
413698U, // LSFP32_Xm_RegOffset_STR
|
|
258U, // LSFP64_LDR
|
|
234U, // LSFP64_LDUR
|
|
6U, // LSFP64_PostInd_LDR
|
|
6U, // LSFP64_PostInd_STR
|
|
226U, // LSFP64_PreInd_LDR
|
|
226U, // LSFP64_PreInd_STR
|
|
258U, // LSFP64_STR
|
|
234U, // LSFP64_STUR
|
|
430082U, // LSFP64_Wm_RegOffset_LDR
|
|
430082U, // LSFP64_Wm_RegOffset_STR
|
|
446466U, // LSFP64_Xm_RegOffset_LDR
|
|
446466U, // LSFP64_Xm_RegOffset_STR
|
|
218U, // LSFP8_LDR
|
|
234U, // LSFP8_LDUR
|
|
6U, // LSFP8_PostInd_LDR
|
|
6U, // LSFP8_PostInd_STR
|
|
226U, // LSFP8_PreInd_LDR
|
|
226U, // LSFP8_PreInd_STR
|
|
218U, // LSFP8_STR
|
|
234U, // LSFP8_STUR
|
|
331778U, // LSFP8_Wm_RegOffset_LDR
|
|
331778U, // LSFP8_Wm_RegOffset_STR
|
|
348162U, // LSFP8_Xm_RegOffset_LDR
|
|
348162U, // LSFP8_Xm_RegOffset_STR
|
|
495622U, // LSFPPair128_LDR
|
|
495622U, // LSFPPair128_NonTemp_LDR
|
|
495622U, // LSFPPair128_NonTemp_STR
|
|
515150U, // LSFPPair128_PostInd_LDR
|
|
515150U, // LSFPPair128_PostInd_STR
|
|
1560654U, // LSFPPair128_PreInd_LDR
|
|
1560654U, // LSFPPair128_PreInd_STR
|
|
495622U, // LSFPPair128_STR
|
|
299014U, // LSFPPair32_LDR
|
|
299014U, // LSFPPair32_NonTemp_LDR
|
|
299014U, // LSFPPair32_NonTemp_STR
|
|
318542U, // LSFPPair32_PostInd_LDR
|
|
318542U, // LSFPPair32_PostInd_STR
|
|
1364046U, // LSFPPair32_PreInd_LDR
|
|
1364046U, // LSFPPair32_PreInd_STR
|
|
299014U, // LSFPPair32_STR
|
|
528390U, // LSFPPair64_LDR
|
|
528390U, // LSFPPair64_NonTemp_LDR
|
|
528390U, // LSFPPair64_NonTemp_STR
|
|
547918U, // LSFPPair64_PostInd_LDR
|
|
547918U, // LSFPPair64_PostInd_STR
|
|
1593422U, // LSFPPair64_PreInd_LDR
|
|
1593422U, // LSFPPair64_PreInd_STR
|
|
528390U, // LSFPPair64_STR
|
|
2U, // LSLVwww
|
|
2U, // LSLVxxx
|
|
2U, // LSLwwi
|
|
2U, // LSLxxi
|
|
299014U, // LSPair32_LDR
|
|
299014U, // LSPair32_NonTemp_LDR
|
|
299014U, // LSPair32_NonTemp_STR
|
|
318542U, // LSPair32_PostInd_LDR
|
|
318542U, // LSPair32_PostInd_STR
|
|
1364046U, // LSPair32_PreInd_LDR
|
|
1364046U, // LSPair32_PreInd_STR
|
|
299014U, // LSPair32_STR
|
|
528390U, // LSPair64_LDR
|
|
528390U, // LSPair64_NonTemp_LDR
|
|
528390U, // LSPair64_NonTemp_STR
|
|
547918U, // LSPair64_PostInd_LDR
|
|
547918U, // LSPair64_PostInd_STR
|
|
1593422U, // LSPair64_PreInd_LDR
|
|
1593422U, // LSPair64_PreInd_STR
|
|
528390U, // LSPair64_STR
|
|
2U, // LSRVwww
|
|
2U, // LSRVxxx
|
|
2U, // LSRwwi
|
|
2U, // LSRxxi
|
|
249858U, // MADDwwww
|
|
249858U, // MADDxxxx
|
|
268299U, // MLAvve_2s4s
|
|
269835U, // MLAvve_4h8h
|
|
268298U, // MLAvve_4s4s
|
|
269834U, // MLAvve_8h8h
|
|
2059U, // MLAvvv_16B
|
|
2571U, // MLAvvv_2S
|
|
3083U, // MLAvvv_4H
|
|
1546U, // MLAvvv_4S
|
|
3595U, // MLAvvv_8B
|
|
522U, // MLAvvv_8H
|
|
268299U, // MLSvve_2s4s
|
|
269835U, // MLSvve_4h8h
|
|
268298U, // MLSvve_4s4s
|
|
269834U, // MLSvve_8h8h
|
|
2059U, // MLSvvv_16B
|
|
2571U, // MLSvvv_2S
|
|
3083U, // MLSvvv_4H
|
|
1546U, // MLSvvv_4S
|
|
3595U, // MLSvvv_8B
|
|
522U, // MLSvvv_8H
|
|
0U, // MOVIdi
|
|
1U, // MOVIvi_16B
|
|
0U, // MOVIvi_2D
|
|
1U, // MOVIvi_8B
|
|
6U, // MOVIvi_lsl_2S
|
|
7U, // MOVIvi_lsl_4H
|
|
6U, // MOVIvi_lsl_4S
|
|
7U, // MOVIvi_lsl_8H
|
|
7U, // MOVIvi_msl_2S
|
|
7U, // MOVIvi_msl_4S
|
|
0U, // MOVKwii
|
|
0U, // MOVKxii
|
|
0U, // MOVNwii
|
|
0U, // MOVNxii
|
|
0U, // MOVZwii
|
|
0U, // MOVZxii
|
|
0U, // MRSxi
|
|
0U, // MSRii
|
|
0U, // MSRix
|
|
249858U, // MSUBwwww
|
|
249858U, // MSUBxxxx
|
|
284691U, // MULve_2s4s
|
|
286227U, // MULve_4h8h
|
|
284690U, // MULve_4s4s
|
|
286226U, // MULve_8h8h
|
|
2067U, // MULvvv_16B
|
|
2579U, // MULvvv_2S
|
|
3091U, // MULvvv_4H
|
|
1554U, // MULvvv_4S
|
|
3603U, // MULvvv_8B
|
|
530U, // MULvvv_8H
|
|
6U, // MVNIvi_lsl_2S
|
|
7U, // MVNIvi_lsl_4H
|
|
6U, // MVNIvi_lsl_4S
|
|
7U, // MVNIvi_lsl_8H
|
|
7U, // MVNIvi_msl_2S
|
|
7U, // MVNIvi_msl_4S
|
|
90U, // MVNww_asr
|
|
98U, // MVNww_lsl
|
|
106U, // MVNww_lsr
|
|
274U, // MVNww_ror
|
|
90U, // MVNxx_asr
|
|
98U, // MVNxx_lsl
|
|
106U, // MVNxx_lsr
|
|
274U, // MVNxx_ror
|
|
0U, // NEG16b
|
|
0U, // NEG2d
|
|
0U, // NEG2s
|
|
0U, // NEG4h
|
|
1U, // NEG4s
|
|
1U, // NEG8b
|
|
1U, // NEG8h
|
|
1U, // NEGdd
|
|
0U, // NOT16b
|
|
1U, // NOT8b
|
|
2067U, // ORNvvv_16B
|
|
3603U, // ORNvvv_8B
|
|
4098U, // ORNwww_asr
|
|
20482U, // ORNwww_lsl
|
|
36866U, // ORNwww_lsr
|
|
184322U, // ORNwww_ror
|
|
4098U, // ORNxxx_asr
|
|
20482U, // ORNxxx_lsl
|
|
36866U, // ORNxxx_lsr
|
|
184322U, // ORNxxx_ror
|
|
4U, // ORRvi_lsl_2S
|
|
4U, // ORRvi_lsl_4H
|
|
4U, // ORRvi_lsl_4S
|
|
4U, // ORRvi_lsl_8H
|
|
2067U, // ORRvvv_16B
|
|
3603U, // ORRvvv_8B
|
|
42U, // ORRwwi
|
|
4098U, // ORRwww_asr
|
|
20482U, // ORRwww_lsl
|
|
36866U, // ORRwww_lsr
|
|
184322U, // ORRwww_ror
|
|
50U, // ORRxxi
|
|
4098U, // ORRxxx_asr
|
|
20482U, // ORRxxx_lsl
|
|
36866U, // ORRxxx_lsr
|
|
184322U, // ORRxxx_ror
|
|
0U, // PMULL2vvv_1q2d
|
|
2067U, // PMULL2vvv_8h16b
|
|
0U, // PMULLvvv_1q1d
|
|
3603U, // PMULLvvv_8h8b
|
|
2067U, // PMULvvv_16B
|
|
3603U, // PMULvvv_8B
|
|
258U, // PRFM
|
|
430082U, // PRFM_Wm_RegOffset
|
|
446466U, // PRFM_Xm_RegOffset
|
|
0U, // PRFM_lit
|
|
234U, // PRFUM
|
|
74U, // QRSHRUNvvi_16B
|
|
2U, // QRSHRUNvvi_2S
|
|
2U, // QRSHRUNvvi_4H
|
|
74U, // QRSHRUNvvi_4S
|
|
2U, // QRSHRUNvvi_8B
|
|
74U, // QRSHRUNvvi_8H
|
|
74U, // QSHRUNvvi_16B
|
|
2U, // QSHRUNvvi_2S
|
|
2U, // QSHRUNvvi_4H
|
|
74U, // QSHRUNvvi_4S
|
|
2U, // QSHRUNvvi_8B
|
|
74U, // QSHRUNvvi_8H
|
|
522U, // RADDHN2vvv_16b8h
|
|
1034U, // RADDHN2vvv_4s2d
|
|
1546U, // RADDHN2vvv_8h4s
|
|
1042U, // RADDHNvvv_2s2d
|
|
1554U, // RADDHNvvv_4h4s
|
|
530U, // RADDHNvvv_8b8h
|
|
0U, // RBIT16b
|
|
1U, // RBIT8b
|
|
1U, // RBITww
|
|
1U, // RBITxx
|
|
0U, // RET
|
|
0U, // RETx
|
|
0U, // REV16_16b
|
|
1U, // REV16_8b
|
|
1U, // REV16ww
|
|
1U, // REV16xx
|
|
0U, // REV32_16b
|
|
0U, // REV32_4h
|
|
1U, // REV32_8b
|
|
1U, // REV32_8h
|
|
1U, // REV32xx
|
|
0U, // REV64_16b
|
|
0U, // REV64_2s
|
|
0U, // REV64_4h
|
|
1U, // REV64_4s
|
|
1U, // REV64_8b
|
|
1U, // REV64_8h
|
|
1U, // REVww
|
|
1U, // REVxx
|
|
2U, // RORVwww
|
|
2U, // RORVxxx
|
|
74U, // RSHRNvvi_16B
|
|
2U, // RSHRNvvi_2S
|
|
2U, // RSHRNvvi_4H
|
|
74U, // RSHRNvvi_4S
|
|
2U, // RSHRNvvi_8B
|
|
74U, // RSHRNvvi_8H
|
|
522U, // RSUBHN2vvv_16b8h
|
|
1034U, // RSUBHN2vvv_4s2d
|
|
1546U, // RSUBHN2vvv_8h4s
|
|
1042U, // RSUBHNvvv_2s2d
|
|
1554U, // RSUBHNvvv_4h4s
|
|
530U, // RSUBHNvvv_8b8h
|
|
1546U, // SABAL2vvv_2d2s
|
|
522U, // SABAL2vvv_4s4h
|
|
2059U, // SABAL2vvv_8h8b
|
|
2571U, // SABALvvv_2d2s
|
|
3083U, // SABALvvv_4s4h
|
|
3595U, // SABALvvv_8h8b
|
|
2059U, // SABAvvv_16B
|
|
2571U, // SABAvvv_2S
|
|
3083U, // SABAvvv_4H
|
|
1546U, // SABAvvv_4S
|
|
3595U, // SABAvvv_8B
|
|
522U, // SABAvvv_8H
|
|
1554U, // SABDL2vvv_2d2s
|
|
530U, // SABDL2vvv_4s4h
|
|
2067U, // SABDL2vvv_8h8b
|
|
2579U, // SABDLvvv_2d2s
|
|
3091U, // SABDLvvv_4s4h
|
|
3603U, // SABDLvvv_8h8b
|
|
2067U, // SABDvvv_16B
|
|
2579U, // SABDvvv_2S
|
|
3091U, // SABDvvv_4H
|
|
1554U, // SABDvvv_4S
|
|
3603U, // SABDvvv_8B
|
|
530U, // SABDvvv_8H
|
|
0U, // SADALP16b8h
|
|
0U, // SADALP2s1d
|
|
0U, // SADALP4h2s
|
|
1U, // SADALP4s2d
|
|
1U, // SADALP8b4h
|
|
1U, // SADALP8h4s
|
|
1554U, // SADDL2vvv_2d4s
|
|
530U, // SADDL2vvv_4s8h
|
|
2067U, // SADDL2vvv_8h16b
|
|
0U, // SADDLP16b8h
|
|
0U, // SADDLP2s1d
|
|
0U, // SADDLP4h2s
|
|
1U, // SADDLP4s2d
|
|
1U, // SADDLP8b4h
|
|
1U, // SADDLP8h4s
|
|
1U, // SADDLV_1d4s
|
|
0U, // SADDLV_1h16b
|
|
1U, // SADDLV_1h8b
|
|
0U, // SADDLV_1s4h
|
|
1U, // SADDLV_1s8h
|
|
2579U, // SADDLvvv_2d2s
|
|
3091U, // SADDLvvv_4s4h
|
|
3603U, // SADDLvvv_8h8b
|
|
1554U, // SADDW2vvv_2d4s
|
|
530U, // SADDW2vvv_4s8h
|
|
2066U, // SADDW2vvv_8h16b
|
|
2578U, // SADDWvvv_2d2s
|
|
3090U, // SADDWvvv_4s4h
|
|
3602U, // SADDWvvv_8h8b
|
|
2U, // SBCSwww
|
|
2U, // SBCSxxx
|
|
2U, // SBCwww
|
|
2U, // SBCxxx
|
|
282U, // SBFIZwwii
|
|
290U, // SBFIZxxii
|
|
249858U, // SBFMwwii
|
|
249858U, // SBFMxxii
|
|
561154U, // SBFXwwii
|
|
561154U, // SBFXxxii
|
|
0U, // SCVTF_2d
|
|
0U, // SCVTF_2s
|
|
1U, // SCVTF_4s
|
|
2U, // SCVTF_Nddi
|
|
2U, // SCVTF_Nssi
|
|
1U, // SCVTFdd
|
|
1U, // SCVTFdw
|
|
194U, // SCVTFdwi
|
|
1U, // SCVTFdx
|
|
194U, // SCVTFdxi
|
|
1U, // SCVTFss
|
|
1U, // SCVTFsw
|
|
194U, // SCVTFswi
|
|
1U, // SCVTFsx
|
|
194U, // SCVTFsxi
|
|
2U, // SDIVwww
|
|
2U, // SDIVxxx
|
|
1546U, // SHA1C
|
|
1U, // SHA1H
|
|
1546U, // SHA1M
|
|
1546U, // SHA1P
|
|
1546U, // SHA1SU0
|
|
1U, // SHA1SU1
|
|
1546U, // SHA256H
|
|
1546U, // SHA256H2
|
|
1U, // SHA256SU0
|
|
1546U, // SHA256SU1
|
|
2067U, // SHADDvvv_16B
|
|
2579U, // SHADDvvv_2S
|
|
3091U, // SHADDvvv_4H
|
|
1554U, // SHADDvvv_4S
|
|
3603U, // SHADDvvv_8B
|
|
530U, // SHADDvvv_8H
|
|
3U, // SHLL16b8h
|
|
3U, // SHLL2s2d
|
|
3U, // SHLL4h4s
|
|
2U, // SHLL4s2d
|
|
3U, // SHLL8b8h
|
|
2U, // SHLL8h4s
|
|
2U, // SHLddi
|
|
3U, // SHLvvi_16B
|
|
2U, // SHLvvi_2D
|
|
3U, // SHLvvi_2S
|
|
3U, // SHLvvi_4H
|
|
2U, // SHLvvi_4S
|
|
3U, // SHLvvi_8B
|
|
2U, // SHLvvi_8H
|
|
74U, // SHRNvvi_16B
|
|
2U, // SHRNvvi_2S
|
|
2U, // SHRNvvi_4H
|
|
74U, // SHRNvvi_4S
|
|
2U, // SHRNvvi_8B
|
|
74U, // SHRNvvi_8H
|
|
2067U, // SHSUBvvv_16B
|
|
2579U, // SHSUBvvv_2S
|
|
3091U, // SHSUBvvv_4H
|
|
1554U, // SHSUBvvv_4S
|
|
3603U, // SHSUBvvv_8B
|
|
530U, // SHSUBvvv_8H
|
|
74U, // SLI
|
|
75U, // SLIvvi_16B
|
|
74U, // SLIvvi_2D
|
|
75U, // SLIvvi_2S
|
|
75U, // SLIvvi_4H
|
|
74U, // SLIvvi_4S
|
|
75U, // SLIvvi_8B
|
|
74U, // SLIvvi_8H
|
|
249858U, // SMADDLxwwx
|
|
2067U, // SMAXPvvv_16B
|
|
2579U, // SMAXPvvv_2S
|
|
3091U, // SMAXPvvv_4H
|
|
1554U, // SMAXPvvv_4S
|
|
3603U, // SMAXPvvv_8B
|
|
530U, // SMAXPvvv_8H
|
|
0U, // SMAXV_1b16b
|
|
1U, // SMAXV_1b8b
|
|
0U, // SMAXV_1h4h
|
|
1U, // SMAXV_1h8h
|
|
1U, // SMAXV_1s4s
|
|
2067U, // SMAXvvv_16B
|
|
2579U, // SMAXvvv_2S
|
|
3091U, // SMAXvvv_4H
|
|
1554U, // SMAXvvv_4S
|
|
3603U, // SMAXvvv_8B
|
|
530U, // SMAXvvv_8H
|
|
0U, // SMCi
|
|
2067U, // SMINPvvv_16B
|
|
2579U, // SMINPvvv_2S
|
|
3091U, // SMINPvvv_4H
|
|
1554U, // SMINPvvv_4S
|
|
3603U, // SMINPvvv_8B
|
|
530U, // SMINPvvv_8H
|
|
0U, // SMINV_1b16b
|
|
1U, // SMINV_1b8b
|
|
0U, // SMINV_1h4h
|
|
1U, // SMINV_1h8h
|
|
1U, // SMINV_1s4s
|
|
2067U, // SMINvvv_16B
|
|
2579U, // SMINvvv_2S
|
|
3091U, // SMINvvv_4H
|
|
1554U, // SMINvvv_4S
|
|
3603U, // SMINvvv_8B
|
|
530U, // SMINvvv_8H
|
|
1546U, // SMLAL2vvv_2d4s
|
|
522U, // SMLAL2vvv_4s8h
|
|
2059U, // SMLAL2vvv_8h16b
|
|
268299U, // SMLALvve_2d2s
|
|
268298U, // SMLALvve_2d4s
|
|
269835U, // SMLALvve_4s4h
|
|
269834U, // SMLALvve_4s8h
|
|
2571U, // SMLALvvv_2d2s
|
|
3083U, // SMLALvvv_4s4h
|
|
3595U, // SMLALvvv_8h8b
|
|
1546U, // SMLSL2vvv_2d4s
|
|
522U, // SMLSL2vvv_4s8h
|
|
2059U, // SMLSL2vvv_8h16b
|
|
268299U, // SMLSLvve_2d2s
|
|
268298U, // SMLSLvve_2d4s
|
|
269835U, // SMLSLvve_4s4h
|
|
269834U, // SMLSLvve_4s8h
|
|
2571U, // SMLSLvvv_2d2s
|
|
3083U, // SMLSLvvv_4s4h
|
|
3595U, // SMLSLvvv_8h8b
|
|
180U, // SMOVwb
|
|
181U, // SMOVwh
|
|
180U, // SMOVxb
|
|
181U, // SMOVxh
|
|
181U, // SMOVxs
|
|
249858U, // SMSUBLxwwx
|
|
2U, // SMULHxxx
|
|
1554U, // SMULL2vvv_2d4s
|
|
530U, // SMULL2vvv_4s8h
|
|
2067U, // SMULL2vvv_8h16b
|
|
284691U, // SMULLve_2d2s
|
|
284690U, // SMULLve_2d4s
|
|
286227U, // SMULLve_4s4h
|
|
286226U, // SMULLve_4s8h
|
|
2579U, // SMULLvvv_2d2s
|
|
3091U, // SMULLvvv_4s4h
|
|
3603U, // SMULLvvv_8h8b
|
|
0U, // SQABS16b
|
|
0U, // SQABS2d
|
|
0U, // SQABS2s
|
|
0U, // SQABS4h
|
|
1U, // SQABS4s
|
|
1U, // SQABS8b
|
|
1U, // SQABS8h
|
|
1U, // SQABSbb
|
|
1U, // SQABSdd
|
|
1U, // SQABShh
|
|
1U, // SQABSss
|
|
2U, // SQADDbbb
|
|
2U, // SQADDddd
|
|
2U, // SQADDhhh
|
|
2U, // SQADDsss
|
|
2067U, // SQADDvvv_16B
|
|
1042U, // SQADDvvv_2D
|
|
2579U, // SQADDvvv_2S
|
|
3091U, // SQADDvvv_4H
|
|
1554U, // SQADDvvv_4S
|
|
3603U, // SQADDvvv_8B
|
|
530U, // SQADDvvv_8H
|
|
1546U, // SQDMLAL2vvv_2d4s
|
|
522U, // SQDMLAL2vvv_4s8h
|
|
74U, // SQDMLALdss
|
|
268298U, // SQDMLALdsv_2S
|
|
268298U, // SQDMLALdsv_4S
|
|
74U, // SQDMLALshh
|
|
269834U, // SQDMLALshv_4H
|
|
269834U, // SQDMLALshv_8H
|
|
268299U, // SQDMLALvve_2d2s
|
|
268298U, // SQDMLALvve_2d4s
|
|
269835U, // SQDMLALvve_4s4h
|
|
269834U, // SQDMLALvve_4s8h
|
|
2571U, // SQDMLALvvv_2d2s
|
|
3083U, // SQDMLALvvv_4s4h
|
|
1546U, // SQDMLSL2vvv_2d4s
|
|
522U, // SQDMLSL2vvv_4s8h
|
|
74U, // SQDMLSLdss
|
|
268298U, // SQDMLSLdsv_2S
|
|
268298U, // SQDMLSLdsv_4S
|
|
74U, // SQDMLSLshh
|
|
269834U, // SQDMLSLshv_4H
|
|
269834U, // SQDMLSLshv_8H
|
|
268299U, // SQDMLSLvve_2d2s
|
|
268298U, // SQDMLSLvve_2d4s
|
|
269835U, // SQDMLSLvve_4s4h
|
|
269834U, // SQDMLSLvve_4s8h
|
|
2571U, // SQDMLSLvvv_2d2s
|
|
3083U, // SQDMLSLvvv_4s4h
|
|
2U, // SQDMULHhhh
|
|
286226U, // SQDMULHhhv_4H
|
|
286226U, // SQDMULHhhv_8H
|
|
2U, // SQDMULHsss
|
|
284690U, // SQDMULHssv_2S
|
|
284690U, // SQDMULHssv_4S
|
|
284691U, // SQDMULHve_2s4s
|
|
286227U, // SQDMULHve_4h8h
|
|
284690U, // SQDMULHve_4s4s
|
|
286226U, // SQDMULHve_8h8h
|
|
2579U, // SQDMULHvvv_2S
|
|
3091U, // SQDMULHvvv_4H
|
|
1554U, // SQDMULHvvv_4S
|
|
530U, // SQDMULHvvv_8H
|
|
1554U, // SQDMULL2vvv_2d4s
|
|
530U, // SQDMULL2vvv_4s8h
|
|
2U, // SQDMULLdss
|
|
284690U, // SQDMULLdsv_2S
|
|
284690U, // SQDMULLdsv_4S
|
|
2U, // SQDMULLshh
|
|
286226U, // SQDMULLshv_4H
|
|
286226U, // SQDMULLshv_8H
|
|
284691U, // SQDMULLve_2d2s
|
|
284690U, // SQDMULLve_2d4s
|
|
286227U, // SQDMULLve_4s4h
|
|
286226U, // SQDMULLve_4s8h
|
|
2579U, // SQDMULLvvv_2d2s
|
|
3091U, // SQDMULLvvv_4s4h
|
|
0U, // SQNEG16b
|
|
0U, // SQNEG2d
|
|
0U, // SQNEG2s
|
|
0U, // SQNEG4h
|
|
1U, // SQNEG4s
|
|
1U, // SQNEG8b
|
|
1U, // SQNEG8h
|
|
1U, // SQNEGbb
|
|
1U, // SQNEGdd
|
|
1U, // SQNEGhh
|
|
1U, // SQNEGss
|
|
2U, // SQRDMULHhhh
|
|
286226U, // SQRDMULHhhv_4H
|
|
286226U, // SQRDMULHhhv_8H
|
|
2U, // SQRDMULHsss
|
|
284690U, // SQRDMULHssv_2S
|
|
284690U, // SQRDMULHssv_4S
|
|
284691U, // SQRDMULHve_2s4s
|
|
286227U, // SQRDMULHve_4h8h
|
|
284690U, // SQRDMULHve_4s4s
|
|
286226U, // SQRDMULHve_8h8h
|
|
2579U, // SQRDMULHvvv_2S
|
|
3091U, // SQRDMULHvvv_4H
|
|
1554U, // SQRDMULHvvv_4S
|
|
530U, // SQRDMULHvvv_8H
|
|
2U, // SQRSHLbbb
|
|
2U, // SQRSHLddd
|
|
2U, // SQRSHLhhh
|
|
2U, // SQRSHLsss
|
|
2067U, // SQRSHLvvv_16B
|
|
1042U, // SQRSHLvvv_2D
|
|
2579U, // SQRSHLvvv_2S
|
|
3091U, // SQRSHLvvv_4H
|
|
1554U, // SQRSHLvvv_4S
|
|
3603U, // SQRSHLvvv_8B
|
|
530U, // SQRSHLvvv_8H
|
|
2U, // SQRSHRNbhi
|
|
2U, // SQRSHRNhsi
|
|
2U, // SQRSHRNsdi
|
|
74U, // SQRSHRNvvi_16B
|
|
2U, // SQRSHRNvvi_2S
|
|
2U, // SQRSHRNvvi_4H
|
|
74U, // SQRSHRNvvi_4S
|
|
2U, // SQRSHRNvvi_8B
|
|
74U, // SQRSHRNvvi_8H
|
|
2U, // SQRSHRUNbhi
|
|
2U, // SQRSHRUNhsi
|
|
2U, // SQRSHRUNsdi
|
|
2U, // SQSHLUbbi
|
|
2U, // SQSHLUddi
|
|
2U, // SQSHLUhhi
|
|
2U, // SQSHLUssi
|
|
3U, // SQSHLUvvi_16B
|
|
2U, // SQSHLUvvi_2D
|
|
3U, // SQSHLUvvi_2S
|
|
3U, // SQSHLUvvi_4H
|
|
2U, // SQSHLUvvi_4S
|
|
3U, // SQSHLUvvi_8B
|
|
2U, // SQSHLUvvi_8H
|
|
2U, // SQSHLbbb
|
|
2U, // SQSHLbbi
|
|
2U, // SQSHLddd
|
|
2U, // SQSHLddi
|
|
2U, // SQSHLhhh
|
|
2U, // SQSHLhhi
|
|
2U, // SQSHLssi
|
|
2U, // SQSHLsss
|
|
3U, // SQSHLvvi_16B
|
|
2U, // SQSHLvvi_2D
|
|
3U, // SQSHLvvi_2S
|
|
3U, // SQSHLvvi_4H
|
|
2U, // SQSHLvvi_4S
|
|
3U, // SQSHLvvi_8B
|
|
2U, // SQSHLvvi_8H
|
|
2067U, // SQSHLvvv_16B
|
|
1042U, // SQSHLvvv_2D
|
|
2579U, // SQSHLvvv_2S
|
|
3091U, // SQSHLvvv_4H
|
|
1554U, // SQSHLvvv_4S
|
|
3603U, // SQSHLvvv_8B
|
|
530U, // SQSHLvvv_8H
|
|
2U, // SQSHRNbhi
|
|
2U, // SQSHRNhsi
|
|
2U, // SQSHRNsdi
|
|
74U, // SQSHRNvvi_16B
|
|
2U, // SQSHRNvvi_2S
|
|
2U, // SQSHRNvvi_4H
|
|
74U, // SQSHRNvvi_4S
|
|
2U, // SQSHRNvvi_8B
|
|
74U, // SQSHRNvvi_8H
|
|
2U, // SQSHRUNbhi
|
|
2U, // SQSHRUNhsi
|
|
2U, // SQSHRUNsdi
|
|
2U, // SQSUBbbb
|
|
2U, // SQSUBddd
|
|
2U, // SQSUBhhh
|
|
2U, // SQSUBsss
|
|
2067U, // SQSUBvvv_16B
|
|
1042U, // SQSUBvvv_2D
|
|
2579U, // SQSUBvvv_2S
|
|
3091U, // SQSUBvvv_4H
|
|
1554U, // SQSUBvvv_4S
|
|
3603U, // SQSUBvvv_8B
|
|
530U, // SQSUBvvv_8H
|
|
0U, // SQXTN2d2s
|
|
0U, // SQXTN2d4s
|
|
1U, // SQXTN4s4h
|
|
1U, // SQXTN4s8h
|
|
1U, // SQXTN8h16b
|
|
1U, // SQXTN8h8b
|
|
1U, // SQXTNbh
|
|
1U, // SQXTNhs
|
|
1U, // SQXTNsd
|
|
0U, // SQXTUN2d2s
|
|
0U, // SQXTUN2d4s
|
|
1U, // SQXTUN4s4h
|
|
1U, // SQXTUN4s8h
|
|
1U, // SQXTUN8h16b
|
|
1U, // SQXTUN8h8b
|
|
1U, // SQXTUNbh
|
|
1U, // SQXTUNhs
|
|
1U, // SQXTUNsd
|
|
2067U, // SRHADDvvv_16B
|
|
2579U, // SRHADDvvv_2S
|
|
3091U, // SRHADDvvv_4H
|
|
1554U, // SRHADDvvv_4S
|
|
3603U, // SRHADDvvv_8B
|
|
530U, // SRHADDvvv_8H
|
|
74U, // SRI
|
|
75U, // SRIvvi_16B
|
|
74U, // SRIvvi_2D
|
|
75U, // SRIvvi_2S
|
|
75U, // SRIvvi_4H
|
|
74U, // SRIvvi_4S
|
|
75U, // SRIvvi_8B
|
|
74U, // SRIvvi_8H
|
|
2U, // SRSHLddd
|
|
2067U, // SRSHLvvv_16B
|
|
1042U, // SRSHLvvv_2D
|
|
2579U, // SRSHLvvv_2S
|
|
3091U, // SRSHLvvv_4H
|
|
1554U, // SRSHLvvv_4S
|
|
3603U, // SRSHLvvv_8B
|
|
530U, // SRSHLvvv_8H
|
|
2U, // SRSHRddi
|
|
3U, // SRSHRvvi_16B
|
|
2U, // SRSHRvvi_2D
|
|
3U, // SRSHRvvi_2S
|
|
3U, // SRSHRvvi_4H
|
|
2U, // SRSHRvvi_4S
|
|
3U, // SRSHRvvi_8B
|
|
2U, // SRSHRvvi_8H
|
|
74U, // SRSRA
|
|
75U, // SRSRAvvi_16B
|
|
74U, // SRSRAvvi_2D
|
|
75U, // SRSRAvvi_2S
|
|
75U, // SRSRAvvi_4H
|
|
74U, // SRSRAvvi_4S
|
|
75U, // SRSRAvvi_8B
|
|
74U, // SRSRAvvi_8H
|
|
3U, // SSHLLvvi_16B
|
|
3U, // SSHLLvvi_2S
|
|
3U, // SSHLLvvi_4H
|
|
2U, // SSHLLvvi_4S
|
|
3U, // SSHLLvvi_8B
|
|
2U, // SSHLLvvi_8H
|
|
2U, // SSHLddd
|
|
2067U, // SSHLvvv_16B
|
|
1042U, // SSHLvvv_2D
|
|
2579U, // SSHLvvv_2S
|
|
3091U, // SSHLvvv_4H
|
|
1554U, // SSHLvvv_4S
|
|
3603U, // SSHLvvv_8B
|
|
530U, // SSHLvvv_8H
|
|
2U, // SSHRddi
|
|
3U, // SSHRvvi_16B
|
|
2U, // SSHRvvi_2D
|
|
3U, // SSHRvvi_2S
|
|
3U, // SSHRvvi_4H
|
|
2U, // SSHRvvi_4S
|
|
3U, // SSHRvvi_8B
|
|
2U, // SSHRvvi_8H
|
|
74U, // SSRA
|
|
75U, // SSRAvvi_16B
|
|
74U, // SSRAvvi_2D
|
|
75U, // SSRAvvi_2S
|
|
75U, // SSRAvvi_4H
|
|
74U, // SSRAvvi_4S
|
|
75U, // SSRAvvi_8B
|
|
74U, // SSRAvvi_8H
|
|
1554U, // SSUBL2vvv_2d4s
|
|
530U, // SSUBL2vvv_4s8h
|
|
2067U, // SSUBL2vvv_8h16b
|
|
2579U, // SSUBLvvv_2d2s
|
|
3091U, // SSUBLvvv_4s4h
|
|
3603U, // SSUBLvvv_8h8b
|
|
1554U, // SSUBW2vvv_2d4s
|
|
530U, // SSUBW2vvv_4s8h
|
|
2066U, // SSUBW2vvv_8h16b
|
|
2578U, // SSUBWvvv_2d2s
|
|
3090U, // SSUBWvvv_4s4h
|
|
3602U, // SSUBWvvv_8h8b
|
|
0U, // ST1LN_B
|
|
0U, // ST1LN_D
|
|
0U, // ST1LN_H
|
|
0U, // ST1LN_S
|
|
0U, // ST1LN_WB_B_fixed
|
|
0U, // ST1LN_WB_B_register
|
|
0U, // ST1LN_WB_D_fixed
|
|
0U, // ST1LN_WB_D_register
|
|
0U, // ST1LN_WB_H_fixed
|
|
0U, // ST1LN_WB_H_register
|
|
0U, // ST1LN_WB_S_fixed
|
|
0U, // ST1LN_WB_S_register
|
|
0U, // ST1WB_16B_fixed
|
|
0U, // ST1WB_16B_register
|
|
0U, // ST1WB_1D_fixed
|
|
0U, // ST1WB_1D_register
|
|
0U, // ST1WB_2D_fixed
|
|
0U, // ST1WB_2D_register
|
|
0U, // ST1WB_2S_fixed
|
|
0U, // ST1WB_2S_register
|
|
0U, // ST1WB_4H_fixed
|
|
0U, // ST1WB_4H_register
|
|
0U, // ST1WB_4S_fixed
|
|
0U, // ST1WB_4S_register
|
|
0U, // ST1WB_8B_fixed
|
|
0U, // ST1WB_8B_register
|
|
0U, // ST1WB_8H_fixed
|
|
0U, // ST1WB_8H_register
|
|
0U, // ST1_16B
|
|
0U, // ST1_1D
|
|
0U, // ST1_2D
|
|
0U, // ST1_2S
|
|
0U, // ST1_4H
|
|
0U, // ST1_4S
|
|
0U, // ST1_8B
|
|
0U, // ST1_8H
|
|
0U, // ST1x2WB_16B_fixed
|
|
0U, // ST1x2WB_16B_register
|
|
0U, // ST1x2WB_1D_fixed
|
|
0U, // ST1x2WB_1D_register
|
|
0U, // ST1x2WB_2D_fixed
|
|
0U, // ST1x2WB_2D_register
|
|
0U, // ST1x2WB_2S_fixed
|
|
0U, // ST1x2WB_2S_register
|
|
0U, // ST1x2WB_4H_fixed
|
|
0U, // ST1x2WB_4H_register
|
|
0U, // ST1x2WB_4S_fixed
|
|
0U, // ST1x2WB_4S_register
|
|
0U, // ST1x2WB_8B_fixed
|
|
0U, // ST1x2WB_8B_register
|
|
0U, // ST1x2WB_8H_fixed
|
|
0U, // ST1x2WB_8H_register
|
|
0U, // ST1x2_16B
|
|
0U, // ST1x2_1D
|
|
0U, // ST1x2_2D
|
|
0U, // ST1x2_2S
|
|
0U, // ST1x2_4H
|
|
0U, // ST1x2_4S
|
|
0U, // ST1x2_8B
|
|
0U, // ST1x2_8H
|
|
0U, // ST1x3WB_16B_fixed
|
|
0U, // ST1x3WB_16B_register
|
|
0U, // ST1x3WB_1D_fixed
|
|
0U, // ST1x3WB_1D_register
|
|
0U, // ST1x3WB_2D_fixed
|
|
0U, // ST1x3WB_2D_register
|
|
0U, // ST1x3WB_2S_fixed
|
|
0U, // ST1x3WB_2S_register
|
|
0U, // ST1x3WB_4H_fixed
|
|
0U, // ST1x3WB_4H_register
|
|
0U, // ST1x3WB_4S_fixed
|
|
0U, // ST1x3WB_4S_register
|
|
0U, // ST1x3WB_8B_fixed
|
|
0U, // ST1x3WB_8B_register
|
|
0U, // ST1x3WB_8H_fixed
|
|
0U, // ST1x3WB_8H_register
|
|
0U, // ST1x3_16B
|
|
0U, // ST1x3_1D
|
|
0U, // ST1x3_2D
|
|
0U, // ST1x3_2S
|
|
0U, // ST1x3_4H
|
|
0U, // ST1x3_4S
|
|
0U, // ST1x3_8B
|
|
0U, // ST1x3_8H
|
|
0U, // ST1x4WB_16B_fixed
|
|
0U, // ST1x4WB_16B_register
|
|
0U, // ST1x4WB_1D_fixed
|
|
0U, // ST1x4WB_1D_register
|
|
0U, // ST1x4WB_2D_fixed
|
|
0U, // ST1x4WB_2D_register
|
|
0U, // ST1x4WB_2S_fixed
|
|
0U, // ST1x4WB_2S_register
|
|
0U, // ST1x4WB_4H_fixed
|
|
0U, // ST1x4WB_4H_register
|
|
0U, // ST1x4WB_4S_fixed
|
|
0U, // ST1x4WB_4S_register
|
|
0U, // ST1x4WB_8B_fixed
|
|
0U, // ST1x4WB_8B_register
|
|
0U, // ST1x4WB_8H_fixed
|
|
0U, // ST1x4WB_8H_register
|
|
0U, // ST1x4_16B
|
|
0U, // ST1x4_1D
|
|
0U, // ST1x4_2D
|
|
0U, // ST1x4_2S
|
|
0U, // ST1x4_4H
|
|
0U, // ST1x4_4S
|
|
0U, // ST1x4_8B
|
|
0U, // ST1x4_8H
|
|
0U, // ST2LN_B
|
|
0U, // ST2LN_D
|
|
0U, // ST2LN_H
|
|
0U, // ST2LN_S
|
|
0U, // ST2LN_WB_B_fixed
|
|
0U, // ST2LN_WB_B_register
|
|
0U, // ST2LN_WB_D_fixed
|
|
0U, // ST2LN_WB_D_register
|
|
0U, // ST2LN_WB_H_fixed
|
|
0U, // ST2LN_WB_H_register
|
|
0U, // ST2LN_WB_S_fixed
|
|
0U, // ST2LN_WB_S_register
|
|
0U, // ST2WB_16B_fixed
|
|
0U, // ST2WB_16B_register
|
|
0U, // ST2WB_2D_fixed
|
|
0U, // ST2WB_2D_register
|
|
0U, // ST2WB_2S_fixed
|
|
0U, // ST2WB_2S_register
|
|
0U, // ST2WB_4H_fixed
|
|
0U, // ST2WB_4H_register
|
|
0U, // ST2WB_4S_fixed
|
|
0U, // ST2WB_4S_register
|
|
0U, // ST2WB_8B_fixed
|
|
0U, // ST2WB_8B_register
|
|
0U, // ST2WB_8H_fixed
|
|
0U, // ST2WB_8H_register
|
|
0U, // ST2_16B
|
|
0U, // ST2_2D
|
|
0U, // ST2_2S
|
|
0U, // ST2_4H
|
|
0U, // ST2_4S
|
|
0U, // ST2_8B
|
|
0U, // ST2_8H
|
|
0U, // ST3LN_B
|
|
0U, // ST3LN_D
|
|
0U, // ST3LN_H
|
|
0U, // ST3LN_S
|
|
0U, // ST3LN_WB_B_fixed
|
|
0U, // ST3LN_WB_B_register
|
|
0U, // ST3LN_WB_D_fixed
|
|
0U, // ST3LN_WB_D_register
|
|
0U, // ST3LN_WB_H_fixed
|
|
0U, // ST3LN_WB_H_register
|
|
0U, // ST3LN_WB_S_fixed
|
|
0U, // ST3LN_WB_S_register
|
|
0U, // ST3WB_16B_fixed
|
|
0U, // ST3WB_16B_register
|
|
0U, // ST3WB_2D_fixed
|
|
0U, // ST3WB_2D_register
|
|
0U, // ST3WB_2S_fixed
|
|
0U, // ST3WB_2S_register
|
|
0U, // ST3WB_4H_fixed
|
|
0U, // ST3WB_4H_register
|
|
0U, // ST3WB_4S_fixed
|
|
0U, // ST3WB_4S_register
|
|
0U, // ST3WB_8B_fixed
|
|
0U, // ST3WB_8B_register
|
|
0U, // ST3WB_8H_fixed
|
|
0U, // ST3WB_8H_register
|
|
0U, // ST3_16B
|
|
0U, // ST3_2D
|
|
0U, // ST3_2S
|
|
0U, // ST3_4H
|
|
0U, // ST3_4S
|
|
0U, // ST3_8B
|
|
0U, // ST3_8H
|
|
0U, // ST4LN_B
|
|
0U, // ST4LN_D
|
|
0U, // ST4LN_H
|
|
0U, // ST4LN_S
|
|
0U, // ST4LN_WB_B_fixed
|
|
0U, // ST4LN_WB_B_register
|
|
0U, // ST4LN_WB_D_fixed
|
|
0U, // ST4LN_WB_D_register
|
|
0U, // ST4LN_WB_H_fixed
|
|
0U, // ST4LN_WB_H_register
|
|
0U, // ST4LN_WB_S_fixed
|
|
0U, // ST4LN_WB_S_register
|
|
0U, // ST4WB_16B_fixed
|
|
0U, // ST4WB_16B_register
|
|
0U, // ST4WB_2D_fixed
|
|
0U, // ST4WB_2D_register
|
|
0U, // ST4WB_2S_fixed
|
|
0U, // ST4WB_2S_register
|
|
0U, // ST4WB_4H_fixed
|
|
0U, // ST4WB_4H_register
|
|
0U, // ST4WB_4S_fixed
|
|
0U, // ST4WB_4S_register
|
|
0U, // ST4WB_8B_fixed
|
|
0U, // ST4WB_8B_register
|
|
0U, // ST4WB_8H_fixed
|
|
0U, // ST4WB_8H_register
|
|
0U, // ST4_16B
|
|
0U, // ST4_2D
|
|
0U, // ST4_2S
|
|
0U, // ST4_4H
|
|
0U, // ST4_4S
|
|
0U, // ST4_8B
|
|
0U, // ST4_8H
|
|
6U, // STLR_byte
|
|
6U, // STLR_dword
|
|
6U, // STLR_hword
|
|
6U, // STLR_word
|
|
8194U, // STLXP_dword
|
|
8194U, // STLXP_word
|
|
6662U, // STLXR_byte
|
|
6662U, // STLXR_dword
|
|
6662U, // STLXR_hword
|
|
6662U, // STLXR_word
|
|
8194U, // STXP_dword
|
|
8194U, // STXP_word
|
|
6662U, // STXR_byte
|
|
6662U, // STXR_dword
|
|
6662U, // STXR_hword
|
|
6662U, // STXR_word
|
|
522U, // SUBHN2vvv_16b8h
|
|
1034U, // SUBHN2vvv_4s2d
|
|
1546U, // SUBHN2vvv_8h4s
|
|
1042U, // SUBHNvvv_2s2d
|
|
1554U, // SUBHNvvv_4h4s
|
|
530U, // SUBHNvvv_8b8h
|
|
4098U, // SUBSwww_asr
|
|
20482U, // SUBSwww_lsl
|
|
36866U, // SUBSwww_lsr
|
|
53250U, // SUBSwww_sxtb
|
|
69634U, // SUBSwww_sxth
|
|
86018U, // SUBSwww_sxtw
|
|
102402U, // SUBSwww_sxtx
|
|
118786U, // SUBSwww_uxtb
|
|
135170U, // SUBSwww_uxth
|
|
151554U, // SUBSwww_uxtw
|
|
167938U, // SUBSwww_uxtx
|
|
53250U, // SUBSxxw_sxtb
|
|
69634U, // SUBSxxw_sxth
|
|
86018U, // SUBSxxw_sxtw
|
|
118786U, // SUBSxxw_uxtb
|
|
135170U, // SUBSxxw_uxth
|
|
151554U, // SUBSxxw_uxtw
|
|
4098U, // SUBSxxx_asr
|
|
20482U, // SUBSxxx_lsl
|
|
36866U, // SUBSxxx_lsr
|
|
102402U, // SUBSxxx_sxtx
|
|
167938U, // SUBSxxx_uxtx
|
|
2U, // SUBddd
|
|
2067U, // SUBvvv_16B
|
|
1042U, // SUBvvv_2D
|
|
2579U, // SUBvvv_2S
|
|
3091U, // SUBvvv_4H
|
|
1554U, // SUBvvv_4S
|
|
3603U, // SUBvvv_8B
|
|
530U, // SUBvvv_8H
|
|
26U, // SUBwwi_lsl0_S
|
|
0U, // SUBwwi_lsl0_cmp
|
|
26U, // SUBwwi_lsl0_s
|
|
34U, // SUBwwi_lsl12_S
|
|
0U, // SUBwwi_lsl12_cmp
|
|
34U, // SUBwwi_lsl12_s
|
|
4098U, // SUBwww_asr
|
|
20482U, // SUBwww_lsl
|
|
36866U, // SUBwww_lsr
|
|
53250U, // SUBwww_sxtb
|
|
69634U, // SUBwww_sxth
|
|
86018U, // SUBwww_sxtw
|
|
102402U, // SUBwww_sxtx
|
|
118786U, // SUBwww_uxtb
|
|
135170U, // SUBwww_uxth
|
|
151554U, // SUBwww_uxtw
|
|
167938U, // SUBwww_uxtx
|
|
26U, // SUBxxi_lsl0_S
|
|
0U, // SUBxxi_lsl0_cmp
|
|
26U, // SUBxxi_lsl0_s
|
|
34U, // SUBxxi_lsl12_S
|
|
0U, // SUBxxi_lsl12_cmp
|
|
34U, // SUBxxi_lsl12_s
|
|
53250U, // SUBxxw_sxtb
|
|
69634U, // SUBxxw_sxth
|
|
86018U, // SUBxxw_sxtw
|
|
118786U, // SUBxxw_uxtb
|
|
135170U, // SUBxxw_uxth
|
|
151554U, // SUBxxw_uxtw
|
|
4098U, // SUBxxx_asr
|
|
20482U, // SUBxxx_lsl
|
|
36866U, // SUBxxx_lsr
|
|
102402U, // SUBxxx_sxtx
|
|
167938U, // SUBxxx_uxtx
|
|
0U, // SUQADD16b
|
|
0U, // SUQADD2d
|
|
0U, // SUQADD2s
|
|
0U, // SUQADD4h
|
|
1U, // SUQADD4s
|
|
1U, // SUQADD8b
|
|
1U, // SUQADD8h
|
|
1U, // SUQADDbb
|
|
1U, // SUQADDdd
|
|
1U, // SUQADDhh
|
|
1U, // SUQADDss
|
|
0U, // SVCi
|
|
1U, // SXTBww
|
|
1U, // SXTBxw
|
|
1U, // SXTHww
|
|
1U, // SXTHxw
|
|
1U, // SXTWxw
|
|
298U, // SYSLxicci
|
|
0U, // SYSiccix
|
|
0U, // TAIL_BRx
|
|
0U, // TAIL_Bimm
|
|
0U, // TBL1_16b
|
|
1U, // TBL1_8b
|
|
0U, // TBL2_16b
|
|
1U, // TBL2_8b
|
|
0U, // TBL3_16b
|
|
1U, // TBL3_8b
|
|
0U, // TBL4_16b
|
|
1U, // TBL4_8b
|
|
306U, // TBNZwii
|
|
306U, // TBNZxii
|
|
0U, // TBX1_16b
|
|
1U, // TBX1_8b
|
|
0U, // TBX2_16b
|
|
1U, // TBX2_8b
|
|
0U, // TBX3_16b
|
|
1U, // TBX3_8b
|
|
0U, // TBX4_16b
|
|
1U, // TBX4_8b
|
|
306U, // TBZwii
|
|
306U, // TBZxii
|
|
0U, // TC_RETURNdi
|
|
0U, // TC_RETURNxi
|
|
0U, // TLBIi
|
|
1U, // TLBIix
|
|
0U, // TLSDESCCALL
|
|
0U, // TLSDESC_BLRx
|
|
2067U, // TRN1vvv_16b
|
|
1042U, // TRN1vvv_2d
|
|
2579U, // TRN1vvv_2s
|
|
3091U, // TRN1vvv_4h
|
|
1554U, // TRN1vvv_4s
|
|
3603U, // TRN1vvv_8b
|
|
530U, // TRN1vvv_8h
|
|
2067U, // TRN2vvv_16b
|
|
1042U, // TRN2vvv_2d
|
|
2579U, // TRN2vvv_2s
|
|
3091U, // TRN2vvv_4h
|
|
1554U, // TRN2vvv_4s
|
|
3603U, // TRN2vvv_8b
|
|
530U, // TRN2vvv_8h
|
|
90U, // TSTww_asr
|
|
98U, // TSTww_lsl
|
|
106U, // TSTww_lsr
|
|
274U, // TSTww_ror
|
|
90U, // TSTxx_asr
|
|
98U, // TSTxx_lsl
|
|
106U, // TSTxx_lsr
|
|
274U, // TSTxx_ror
|
|
1546U, // UABAL2vvv_2d2s
|
|
522U, // UABAL2vvv_4s4h
|
|
2059U, // UABAL2vvv_8h8b
|
|
2571U, // UABALvvv_2d2s
|
|
3083U, // UABALvvv_4s4h
|
|
3595U, // UABALvvv_8h8b
|
|
2059U, // UABAvvv_16B
|
|
2571U, // UABAvvv_2S
|
|
3083U, // UABAvvv_4H
|
|
1546U, // UABAvvv_4S
|
|
3595U, // UABAvvv_8B
|
|
522U, // UABAvvv_8H
|
|
1554U, // UABDL2vvv_2d2s
|
|
530U, // UABDL2vvv_4s4h
|
|
2067U, // UABDL2vvv_8h8b
|
|
2579U, // UABDLvvv_2d2s
|
|
3091U, // UABDLvvv_4s4h
|
|
3603U, // UABDLvvv_8h8b
|
|
2067U, // UABDvvv_16B
|
|
2579U, // UABDvvv_2S
|
|
3091U, // UABDvvv_4H
|
|
1554U, // UABDvvv_4S
|
|
3603U, // UABDvvv_8B
|
|
530U, // UABDvvv_8H
|
|
0U, // UADALP16b8h
|
|
0U, // UADALP2s1d
|
|
0U, // UADALP4h2s
|
|
1U, // UADALP4s2d
|
|
1U, // UADALP8b4h
|
|
1U, // UADALP8h4s
|
|
1554U, // UADDL2vvv_2d4s
|
|
530U, // UADDL2vvv_4s8h
|
|
2067U, // UADDL2vvv_8h16b
|
|
0U, // UADDLP16b8h
|
|
0U, // UADDLP2s1d
|
|
0U, // UADDLP4h2s
|
|
1U, // UADDLP4s2d
|
|
1U, // UADDLP8b4h
|
|
1U, // UADDLP8h4s
|
|
1U, // UADDLV_1d4s
|
|
0U, // UADDLV_1h16b
|
|
1U, // UADDLV_1h8b
|
|
0U, // UADDLV_1s4h
|
|
1U, // UADDLV_1s8h
|
|
2579U, // UADDLvvv_2d2s
|
|
3091U, // UADDLvvv_4s4h
|
|
3603U, // UADDLvvv_8h8b
|
|
1554U, // UADDW2vvv_2d4s
|
|
530U, // UADDW2vvv_4s8h
|
|
2066U, // UADDW2vvv_8h16b
|
|
2578U, // UADDWvvv_2d2s
|
|
3090U, // UADDWvvv_4s4h
|
|
3602U, // UADDWvvv_8h8b
|
|
282U, // UBFIZwwii
|
|
290U, // UBFIZxxii
|
|
249858U, // UBFMwwii
|
|
249858U, // UBFMxxii
|
|
561154U, // UBFXwwii
|
|
561154U, // UBFXxxii
|
|
0U, // UCVTF_2d
|
|
0U, // UCVTF_2s
|
|
1U, // UCVTF_4s
|
|
2U, // UCVTF_Nddi
|
|
2U, // UCVTF_Nssi
|
|
1U, // UCVTFdd
|
|
1U, // UCVTFdw
|
|
194U, // UCVTFdwi
|
|
1U, // UCVTFdx
|
|
194U, // UCVTFdxi
|
|
1U, // UCVTFss
|
|
1U, // UCVTFsw
|
|
194U, // UCVTFswi
|
|
1U, // UCVTFsx
|
|
194U, // UCVTFsxi
|
|
2U, // UDIVwww
|
|
2U, // UDIVxxx
|
|
2067U, // UHADDvvv_16B
|
|
2579U, // UHADDvvv_2S
|
|
3091U, // UHADDvvv_4H
|
|
1554U, // UHADDvvv_4S
|
|
3603U, // UHADDvvv_8B
|
|
530U, // UHADDvvv_8H
|
|
2067U, // UHSUBvvv_16B
|
|
2579U, // UHSUBvvv_2S
|
|
3091U, // UHSUBvvv_4H
|
|
1554U, // UHSUBvvv_4S
|
|
3603U, // UHSUBvvv_8B
|
|
530U, // UHSUBvvv_8H
|
|
249858U, // UMADDLxwwx
|
|
2067U, // UMAXPvvv_16B
|
|
2579U, // UMAXPvvv_2S
|
|
3091U, // UMAXPvvv_4H
|
|
1554U, // UMAXPvvv_4S
|
|
3603U, // UMAXPvvv_8B
|
|
530U, // UMAXPvvv_8H
|
|
0U, // UMAXV_1b16b
|
|
1U, // UMAXV_1b8b
|
|
0U, // UMAXV_1h4h
|
|
1U, // UMAXV_1h8h
|
|
1U, // UMAXV_1s4s
|
|
2067U, // UMAXvvv_16B
|
|
2579U, // UMAXvvv_2S
|
|
3091U, // UMAXvvv_4H
|
|
1554U, // UMAXvvv_4S
|
|
3603U, // UMAXvvv_8B
|
|
530U, // UMAXvvv_8H
|
|
2067U, // UMINPvvv_16B
|
|
2579U, // UMINPvvv_2S
|
|
3091U, // UMINPvvv_4H
|
|
1554U, // UMINPvvv_4S
|
|
3603U, // UMINPvvv_8B
|
|
530U, // UMINPvvv_8H
|
|
0U, // UMINV_1b16b
|
|
1U, // UMINV_1b8b
|
|
0U, // UMINV_1h4h
|
|
1U, // UMINV_1h8h
|
|
1U, // UMINV_1s4s
|
|
2067U, // UMINvvv_16B
|
|
2579U, // UMINvvv_2S
|
|
3091U, // UMINvvv_4H
|
|
1554U, // UMINvvv_4S
|
|
3603U, // UMINvvv_8B
|
|
530U, // UMINvvv_8H
|
|
1546U, // UMLAL2vvv_2d4s
|
|
522U, // UMLAL2vvv_4s8h
|
|
2059U, // UMLAL2vvv_8h16b
|
|
268299U, // UMLALvve_2d2s
|
|
268298U, // UMLALvve_2d4s
|
|
269835U, // UMLALvve_4s4h
|
|
269834U, // UMLALvve_4s8h
|
|
2571U, // UMLALvvv_2d2s
|
|
3083U, // UMLALvvv_4s4h
|
|
3595U, // UMLALvvv_8h8b
|
|
1546U, // UMLSL2vvv_2d4s
|
|
522U, // UMLSL2vvv_4s8h
|
|
2059U, // UMLSL2vvv_8h16b
|
|
268299U, // UMLSLvve_2d2s
|
|
268298U, // UMLSLvve_2d4s
|
|
269835U, // UMLSLvve_4s4h
|
|
269834U, // UMLSLvve_4s8h
|
|
2571U, // UMLSLvvv_2d2s
|
|
3083U, // UMLSLvvv_4s4h
|
|
3595U, // UMLSLvvv_8h8b
|
|
180U, // UMOVwb
|
|
181U, // UMOVwh
|
|
181U, // UMOVws
|
|
180U, // UMOVxd
|
|
249858U, // UMSUBLxwwx
|
|
2U, // UMULHxxx
|
|
1554U, // UMULL2vvv_2d4s
|
|
530U, // UMULL2vvv_4s8h
|
|
2067U, // UMULL2vvv_8h16b
|
|
284691U, // UMULLve_2d2s
|
|
284690U, // UMULLve_2d4s
|
|
286227U, // UMULLve_4s4h
|
|
286226U, // UMULLve_4s8h
|
|
2579U, // UMULLvvv_2d2s
|
|
3091U, // UMULLvvv_4s4h
|
|
3603U, // UMULLvvv_8h8b
|
|
2U, // UQADDbbb
|
|
2U, // UQADDddd
|
|
2U, // UQADDhhh
|
|
2U, // UQADDsss
|
|
2067U, // UQADDvvv_16B
|
|
1042U, // UQADDvvv_2D
|
|
2579U, // UQADDvvv_2S
|
|
3091U, // UQADDvvv_4H
|
|
1554U, // UQADDvvv_4S
|
|
3603U, // UQADDvvv_8B
|
|
530U, // UQADDvvv_8H
|
|
2U, // UQRSHLbbb
|
|
2U, // UQRSHLddd
|
|
2U, // UQRSHLhhh
|
|
2U, // UQRSHLsss
|
|
2067U, // UQRSHLvvv_16B
|
|
1042U, // UQRSHLvvv_2D
|
|
2579U, // UQRSHLvvv_2S
|
|
3091U, // UQRSHLvvv_4H
|
|
1554U, // UQRSHLvvv_4S
|
|
3603U, // UQRSHLvvv_8B
|
|
530U, // UQRSHLvvv_8H
|
|
2U, // UQRSHRNbhi
|
|
2U, // UQRSHRNhsi
|
|
2U, // UQRSHRNsdi
|
|
74U, // UQRSHRNvvi_16B
|
|
2U, // UQRSHRNvvi_2S
|
|
2U, // UQRSHRNvvi_4H
|
|
74U, // UQRSHRNvvi_4S
|
|
2U, // UQRSHRNvvi_8B
|
|
74U, // UQRSHRNvvi_8H
|
|
2U, // UQSHLbbb
|
|
2U, // UQSHLbbi
|
|
2U, // UQSHLddd
|
|
2U, // UQSHLddi
|
|
2U, // UQSHLhhh
|
|
2U, // UQSHLhhi
|
|
2U, // UQSHLssi
|
|
2U, // UQSHLsss
|
|
3U, // UQSHLvvi_16B
|
|
2U, // UQSHLvvi_2D
|
|
3U, // UQSHLvvi_2S
|
|
3U, // UQSHLvvi_4H
|
|
2U, // UQSHLvvi_4S
|
|
3U, // UQSHLvvi_8B
|
|
2U, // UQSHLvvi_8H
|
|
2067U, // UQSHLvvv_16B
|
|
1042U, // UQSHLvvv_2D
|
|
2579U, // UQSHLvvv_2S
|
|
3091U, // UQSHLvvv_4H
|
|
1554U, // UQSHLvvv_4S
|
|
3603U, // UQSHLvvv_8B
|
|
530U, // UQSHLvvv_8H
|
|
2U, // UQSHRNbhi
|
|
2U, // UQSHRNhsi
|
|
2U, // UQSHRNsdi
|
|
74U, // UQSHRNvvi_16B
|
|
2U, // UQSHRNvvi_2S
|
|
2U, // UQSHRNvvi_4H
|
|
74U, // UQSHRNvvi_4S
|
|
2U, // UQSHRNvvi_8B
|
|
74U, // UQSHRNvvi_8H
|
|
2U, // UQSUBbbb
|
|
2U, // UQSUBddd
|
|
2U, // UQSUBhhh
|
|
2U, // UQSUBsss
|
|
2067U, // UQSUBvvv_16B
|
|
1042U, // UQSUBvvv_2D
|
|
2579U, // UQSUBvvv_2S
|
|
3091U, // UQSUBvvv_4H
|
|
1554U, // UQSUBvvv_4S
|
|
3603U, // UQSUBvvv_8B
|
|
530U, // UQSUBvvv_8H
|
|
0U, // UQXTN2d2s
|
|
0U, // UQXTN2d4s
|
|
1U, // UQXTN4s4h
|
|
1U, // UQXTN4s8h
|
|
1U, // UQXTN8h16b
|
|
1U, // UQXTN8h8b
|
|
1U, // UQXTNbh
|
|
1U, // UQXTNhs
|
|
1U, // UQXTNsd
|
|
0U, // URECPE2s
|
|
1U, // URECPE4s
|
|
2067U, // URHADDvvv_16B
|
|
2579U, // URHADDvvv_2S
|
|
3091U, // URHADDvvv_4H
|
|
1554U, // URHADDvvv_4S
|
|
3603U, // URHADDvvv_8B
|
|
530U, // URHADDvvv_8H
|
|
2U, // URSHLddd
|
|
2067U, // URSHLvvv_16B
|
|
1042U, // URSHLvvv_2D
|
|
2579U, // URSHLvvv_2S
|
|
3091U, // URSHLvvv_4H
|
|
1554U, // URSHLvvv_4S
|
|
3603U, // URSHLvvv_8B
|
|
530U, // URSHLvvv_8H
|
|
2U, // URSHRddi
|
|
3U, // URSHRvvi_16B
|
|
2U, // URSHRvvi_2D
|
|
3U, // URSHRvvi_2S
|
|
3U, // URSHRvvi_4H
|
|
2U, // URSHRvvi_4S
|
|
3U, // URSHRvvi_8B
|
|
2U, // URSHRvvi_8H
|
|
0U, // URSQRTE2s
|
|
1U, // URSQRTE4s
|
|
74U, // URSRA
|
|
75U, // URSRAvvi_16B
|
|
74U, // URSRAvvi_2D
|
|
75U, // URSRAvvi_2S
|
|
75U, // URSRAvvi_4H
|
|
74U, // URSRAvvi_4S
|
|
75U, // URSRAvvi_8B
|
|
74U, // URSRAvvi_8H
|
|
3U, // USHLLvvi_16B
|
|
3U, // USHLLvvi_2S
|
|
3U, // USHLLvvi_4H
|
|
2U, // USHLLvvi_4S
|
|
3U, // USHLLvvi_8B
|
|
2U, // USHLLvvi_8H
|
|
2U, // USHLddd
|
|
2067U, // USHLvvv_16B
|
|
1042U, // USHLvvv_2D
|
|
2579U, // USHLvvv_2S
|
|
3091U, // USHLvvv_4H
|
|
1554U, // USHLvvv_4S
|
|
3603U, // USHLvvv_8B
|
|
530U, // USHLvvv_8H
|
|
2U, // USHRddi
|
|
3U, // USHRvvi_16B
|
|
2U, // USHRvvi_2D
|
|
3U, // USHRvvi_2S
|
|
3U, // USHRvvi_4H
|
|
2U, // USHRvvi_4S
|
|
3U, // USHRvvi_8B
|
|
2U, // USHRvvi_8H
|
|
0U, // USQADD16b
|
|
0U, // USQADD2d
|
|
0U, // USQADD2s
|
|
0U, // USQADD4h
|
|
1U, // USQADD4s
|
|
1U, // USQADD8b
|
|
1U, // USQADD8h
|
|
1U, // USQADDbb
|
|
1U, // USQADDdd
|
|
1U, // USQADDhh
|
|
1U, // USQADDss
|
|
74U, // USRA
|
|
75U, // USRAvvi_16B
|
|
74U, // USRAvvi_2D
|
|
75U, // USRAvvi_2S
|
|
75U, // USRAvvi_4H
|
|
74U, // USRAvvi_4S
|
|
75U, // USRAvvi_8B
|
|
74U, // USRAvvi_8H
|
|
1554U, // USUBL2vvv_2d4s
|
|
530U, // USUBL2vvv_4s8h
|
|
2067U, // USUBL2vvv_8h16b
|
|
2579U, // USUBLvvv_2d2s
|
|
3091U, // USUBLvvv_4s4h
|
|
3603U, // USUBLvvv_8h8b
|
|
1554U, // USUBW2vvv_2d4s
|
|
530U, // USUBW2vvv_4s8h
|
|
2066U, // USUBW2vvv_8h16b
|
|
2578U, // USUBWvvv_2d2s
|
|
3090U, // USUBWvvv_4s4h
|
|
3602U, // USUBWvvv_8h8b
|
|
1U, // UXTBww
|
|
1U, // UXTBxw
|
|
1U, // UXTHww
|
|
1U, // UXTHxw
|
|
2067U, // UZP1vvv_16b
|
|
1042U, // UZP1vvv_2d
|
|
2579U, // UZP1vvv_2s
|
|
3091U, // UZP1vvv_4h
|
|
1554U, // UZP1vvv_4s
|
|
3603U, // UZP1vvv_8b
|
|
530U, // UZP1vvv_8h
|
|
2067U, // UZP2vvv_16b
|
|
1042U, // UZP2vvv_2d
|
|
2579U, // UZP2vvv_2s
|
|
3091U, // UZP2vvv_4h
|
|
1554U, // UZP2vvv_4s
|
|
3603U, // UZP2vvv_8b
|
|
530U, // UZP2vvv_8h
|
|
2U, // VCVTf2xs_2D
|
|
3U, // VCVTf2xs_2S
|
|
2U, // VCVTf2xs_4S
|
|
2U, // VCVTf2xu_2D
|
|
3U, // VCVTf2xu_2S
|
|
2U, // VCVTf2xu_4S
|
|
2U, // VCVTxs2f_2D
|
|
3U, // VCVTxs2f_2S
|
|
2U, // VCVTxs2f_4S
|
|
2U, // VCVTxu2f_2D
|
|
3U, // VCVTxu2f_2S
|
|
2U, // VCVTxu2f_4S
|
|
0U, // XTN2d2s
|
|
0U, // XTN2d4s
|
|
1U, // XTN4s4h
|
|
1U, // XTN4s8h
|
|
1U, // XTN8h16b
|
|
1U, // XTN8h8b
|
|
2067U, // ZIP1vvv_16b
|
|
1042U, // ZIP1vvv_2d
|
|
2579U, // ZIP1vvv_2s
|
|
3091U, // ZIP1vvv_4h
|
|
1554U, // ZIP1vvv_4s
|
|
3603U, // ZIP1vvv_8b
|
|
530U, // ZIP1vvv_8h
|
|
2067U, // ZIP2vvv_16b
|
|
1042U, // ZIP2vvv_2d
|
|
2579U, // ZIP2vvv_2s
|
|
3091U, // ZIP2vvv_4h
|
|
1554U, // ZIP2vvv_4s
|
|
3603U, // ZIP2vvv_8b
|
|
530U, // ZIP2vvv_8h
|
|
0U
|
|
};
|
|
|
|
#ifndef CAPSTONE_DIET
|
|
static char AsmStrs[] = {
|
|
/* 0 */ 's', 'h', 'a', '1', 's', 'u', '0', 9, 0,
|
|
/* 9 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '0', 9, 0,
|
|
/* 20 */ 'l', 'd', '1', 9, 0,
|
|
/* 25 */ 't', 'r', 'n', '1', 9, 0,
|
|
/* 31 */ 'z', 'i', 'p', '1', 9, 0,
|
|
/* 37 */ 'u', 'z', 'p', '1', 9, 0,
|
|
/* 43 */ 'd', 'c', 'p', 's', '1', 9, 0,
|
|
/* 50 */ 's', 't', '1', 9, 0,
|
|
/* 55 */ 's', 'h', 'a', '1', 's', 'u', '1', 9, 0,
|
|
/* 64 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '1', 9, 0,
|
|
/* 75 */ 'r', 'e', 'v', '3', '2', 9, 0,
|
|
/* 82 */ 'l', 'd', '2', 9, 0,
|
|
/* 87 */ 's', 'h', 'a', '2', '5', '6', 'h', '2', 9, 0,
|
|
/* 97 */ 's', 'a', 'b', 'a', 'l', '2', 9, 0,
|
|
/* 105 */ 'u', 'a', 'b', 'a', 'l', '2', 9, 0,
|
|
/* 113 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', '2', 9, 0,
|
|
/* 123 */ 's', 'm', 'l', 'a', 'l', '2', 9, 0,
|
|
/* 131 */ 'u', 'm', 'l', 'a', 'l', '2', 9, 0,
|
|
/* 139 */ 's', 's', 'u', 'b', 'l', '2', 9, 0,
|
|
/* 147 */ 'u', 's', 'u', 'b', 'l', '2', 9, 0,
|
|
/* 155 */ 's', 'a', 'b', 'd', 'l', '2', 9, 0,
|
|
/* 163 */ 'u', 'a', 'b', 'd', 'l', '2', 9, 0,
|
|
/* 171 */ 's', 'a', 'd', 'd', 'l', '2', 9, 0,
|
|
/* 179 */ 'u', 'a', 'd', 'd', 'l', '2', 9, 0,
|
|
/* 187 */ 's', 's', 'h', 'l', 'l', '2', 9, 0,
|
|
/* 195 */ 'u', 's', 'h', 'l', 'l', '2', 9, 0,
|
|
/* 203 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', '2', 9, 0,
|
|
/* 213 */ 'p', 'm', 'u', 'l', 'l', '2', 9, 0,
|
|
/* 221 */ 's', 'm', 'u', 'l', 'l', '2', 9, 0,
|
|
/* 229 */ 'u', 'm', 'u', 'l', 'l', '2', 9, 0,
|
|
/* 237 */ 's', 'q', 'd', 'm', 'l', 's', 'l', '2', 9, 0,
|
|
/* 247 */ 's', 'm', 'l', 's', 'l', '2', 9, 0,
|
|
/* 255 */ 'u', 'm', 'l', 's', 'l', '2', 9, 0,
|
|
/* 263 */ 'f', 'c', 'v', 't', 'l', '2', 9, 0,
|
|
/* 271 */ 'r', 's', 'u', 'b', 'h', 'n', '2', 9, 0,
|
|
/* 280 */ 'r', 'a', 'd', 'd', 'h', 'n', '2', 9, 0,
|
|
/* 289 */ 's', 'q', 's', 'h', 'r', 'n', '2', 9, 0,
|
|
/* 298 */ 'u', 'q', 's', 'h', 'r', 'n', '2', 9, 0,
|
|
/* 307 */ 's', 'q', 'r', 's', 'h', 'r', 'n', '2', 9, 0,
|
|
/* 317 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', '2', 9, 0,
|
|
/* 327 */ 't', 'r', 'n', '2', 9, 0,
|
|
/* 333 */ 'f', 'c', 'v', 't', 'n', '2', 9, 0,
|
|
/* 341 */ 's', 'q', 'x', 't', 'n', '2', 9, 0,
|
|
/* 349 */ 'u', 'q', 'x', 't', 'n', '2', 9, 0,
|
|
/* 357 */ 's', 'q', 's', 'h', 'r', 'u', 'n', '2', 9, 0,
|
|
/* 367 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', '2', 9, 0,
|
|
/* 378 */ 's', 'q', 'x', 't', 'u', 'n', '2', 9, 0,
|
|
/* 387 */ 'f', 'c', 'v', 't', 'x', 'n', '2', 9, 0,
|
|
/* 396 */ 'z', 'i', 'p', '2', 9, 0,
|
|
/* 402 */ 'u', 'z', 'p', '2', 9, 0,
|
|
/* 408 */ 'd', 'c', 'p', 's', '2', 9, 0,
|
|
/* 415 */ 's', 't', '2', 9, 0,
|
|
/* 420 */ 's', 's', 'u', 'b', 'w', '2', 9, 0,
|
|
/* 428 */ 'u', 's', 'u', 'b', 'w', '2', 9, 0,
|
|
/* 436 */ 's', 'a', 'd', 'd', 'w', '2', 9, 0,
|
|
/* 444 */ 'u', 'a', 'd', 'd', 'w', '2', 9, 0,
|
|
/* 452 */ 'l', 'd', '3', 9, 0,
|
|
/* 457 */ 'd', 'c', 'p', 's', '3', 9, 0,
|
|
/* 464 */ 's', 't', '3', 9, 0,
|
|
/* 469 */ 'r', 'e', 'v', '6', '4', 9, 0,
|
|
/* 476 */ 'l', 'd', '4', 9, 0,
|
|
/* 481 */ 's', 't', '4', 9, 0,
|
|
/* 486 */ 'r', 'e', 'v', '1', '6', 9, 0,
|
|
/* 493 */ 's', 'a', 'b', 'a', 9, 0,
|
|
/* 499 */ 'u', 'a', 'b', 'a', 9, 0,
|
|
/* 505 */ 'f', 'm', 'l', 'a', 9, 0,
|
|
/* 511 */ 's', 'r', 's', 'r', 'a', 9, 0,
|
|
/* 518 */ 'u', 'r', 's', 'r', 'a', 9, 0,
|
|
/* 525 */ 's', 's', 'r', 'a', 9, 0,
|
|
/* 531 */ 'u', 's', 'r', 'a', 9, 0,
|
|
/* 537 */ 'f', 'r', 'i', 'n', 't', 'a', 9, 0,
|
|
/* 545 */ 'c', 'r', 'c', '3', '2', 'b', 9, 0,
|
|
/* 553 */ 'c', 'r', 'c', '3', '2', 'c', 'b', 9, 0,
|
|
/* 562 */ 'd', 'm', 'b', 9, 0,
|
|
/* 567 */ 'l', 'd', 'a', 'r', 'b', 9, 0,
|
|
/* 574 */ 'l', 'd', 'r', 'b', 9, 0,
|
|
/* 580 */ 's', 't', 'l', 'r', 'b', 9, 0,
|
|
/* 587 */ 'l', 'd', 't', 'r', 'b', 9, 0,
|
|
/* 594 */ 's', 't', 'r', 'b', 9, 0,
|
|
/* 600 */ 's', 't', 't', 'r', 'b', 9, 0,
|
|
/* 607 */ 'l', 'd', 'u', 'r', 'b', 9, 0,
|
|
/* 614 */ 's', 't', 'u', 'r', 'b', 9, 0,
|
|
/* 621 */ 'l', 'd', 'a', 'x', 'r', 'b', 9, 0,
|
|
/* 629 */ 'l', 'd', 'x', 'r', 'b', 9, 0,
|
|
/* 636 */ 's', 't', 'l', 'x', 'r', 'b', 9, 0,
|
|
/* 644 */ 's', 't', 'x', 'r', 'b', 9, 0,
|
|
/* 651 */ 'd', 's', 'b', 9, 0,
|
|
/* 656 */ 'i', 's', 'b', 9, 0,
|
|
/* 661 */ 'l', 'd', 'r', 's', 'b', 9, 0,
|
|
/* 668 */ 'l', 'd', 't', 'r', 's', 'b', 9, 0,
|
|
/* 676 */ 'l', 'd', 'u', 'r', 's', 'b', 9, 0,
|
|
/* 684 */ 's', 'x', 't', 'b', 9, 0,
|
|
/* 690 */ 'u', 'x', 't', 'b', 9, 0,
|
|
/* 696 */ 'f', 's', 'u', 'b', 9, 0,
|
|
/* 702 */ 's', 'h', 's', 'u', 'b', 9, 0,
|
|
/* 709 */ 'u', 'h', 's', 'u', 'b', 9, 0,
|
|
/* 716 */ 'f', 'm', 's', 'u', 'b', 9, 0,
|
|
/* 723 */ 'f', 'n', 'm', 's', 'u', 'b', 9, 0,
|
|
/* 731 */ 's', 'q', 's', 'u', 'b', 9, 0,
|
|
/* 738 */ 'u', 'q', 's', 'u', 'b', 9, 0,
|
|
/* 745 */ 's', 'h', 'a', '1', 'c', 9, 0,
|
|
/* 752 */ 's', 'b', 'c', 9, 0,
|
|
/* 757 */ 'a', 'd', 'c', 9, 0,
|
|
/* 762 */ 'b', 'i', 'c', 9, 0,
|
|
/* 767 */ 'a', 'e', 's', 'i', 'm', 'c', 9, 0,
|
|
/* 775 */ 'a', 'e', 's', 'm', 'c', 9, 0,
|
|
/* 782 */ 'c', 's', 'i', 'n', 'c', 9, 0,
|
|
/* 789 */ 'h', 'v', 'c', 9, 0,
|
|
/* 794 */ 's', 'v', 'c', 9, 0,
|
|
/* 799 */ 'f', 'a', 'b', 'd', 9, 0,
|
|
/* 805 */ 's', 'a', 'b', 'd', 9, 0,
|
|
/* 811 */ 'u', 'a', 'b', 'd', 9, 0,
|
|
/* 817 */ 'f', 'a', 'd', 'd', 9, 0,
|
|
/* 823 */ 's', 'r', 'h', 'a', 'd', 'd', 9, 0,
|
|
/* 831 */ 'u', 'r', 'h', 'a', 'd', 'd', 9, 0,
|
|
/* 839 */ 's', 'h', 'a', 'd', 'd', 9, 0,
|
|
/* 846 */ 'u', 'h', 'a', 'd', 'd', 9, 0,
|
|
/* 853 */ 'f', 'm', 'a', 'd', 'd', 9, 0,
|
|
/* 860 */ 'f', 'n', 'm', 'a', 'd', 'd', 9, 0,
|
|
/* 868 */ 'u', 's', 'q', 'a', 'd', 'd', 9, 0,
|
|
/* 876 */ 's', 'u', 'q', 'a', 'd', 'd', 9, 0,
|
|
/* 884 */ 'a', 'n', 'd', 9, 0,
|
|
/* 889 */ 'a', 'e', 's', 'd', 9, 0,
|
|
/* 895 */ 'f', 'a', 'c', 'g', 'e', 9, 0,
|
|
/* 902 */ 'f', 'c', 'm', 'g', 'e', 9, 0,
|
|
/* 909 */ 'f', 'c', 'm', 'l', 'e', 9, 0,
|
|
/* 916 */ 'f', 'r', 'e', 'c', 'p', 'e', 9, 0,
|
|
/* 924 */ 'u', 'r', 'e', 'c', 'p', 'e', 9, 0,
|
|
/* 932 */ 'f', 'c', 'c', 'm', 'p', 'e', 9, 0,
|
|
/* 940 */ 'f', 'c', 'm', 'p', 'e', 9, 0,
|
|
/* 947 */ 'a', 'e', 's', 'e', 9, 0,
|
|
/* 953 */ 'f', 'r', 's', 'q', 'r', 't', 'e', 9, 0,
|
|
/* 962 */ 'u', 'r', 's', 'q', 'r', 't', 'e', 9, 0,
|
|
/* 971 */ 'b', 'i', 'f', 9, 0,
|
|
/* 976 */ 's', 'c', 'v', 't', 'f', 9, 0,
|
|
/* 983 */ 'u', 'c', 'v', 't', 'f', 9, 0,
|
|
/* 990 */ 'f', 'n', 'e', 'g', 9, 0,
|
|
/* 996 */ 's', 'q', 'n', 'e', 'g', 9, 0,
|
|
/* 1003 */ 'c', 's', 'n', 'e', 'g', 9, 0,
|
|
/* 1010 */ 's', 'h', 'a', '1', 'h', 9, 0,
|
|
/* 1017 */ 'c', 'r', 'c', '3', '2', 'h', 9, 0,
|
|
/* 1025 */ 's', 'h', 'a', '2', '5', '6', 'h', 9, 0,
|
|
/* 1034 */ 'c', 'r', 'c', '3', '2', 'c', 'h', 9, 0,
|
|
/* 1043 */ 's', 'q', 'd', 'm', 'u', 'l', 'h', 9, 0,
|
|
/* 1052 */ 's', 'q', 'r', 'd', 'm', 'u', 'l', 'h', 9, 0,
|
|
/* 1062 */ 's', 'm', 'u', 'l', 'h', 9, 0,
|
|
/* 1069 */ 'u', 'm', 'u', 'l', 'h', 9, 0,
|
|
/* 1076 */ 'l', 'd', 'a', 'r', 'h', 9, 0,
|
|
/* 1083 */ 'l', 'd', 'r', 'h', 9, 0,
|
|
/* 1089 */ 's', 't', 'l', 'r', 'h', 9, 0,
|
|
/* 1096 */ 'l', 'd', 't', 'r', 'h', 9, 0,
|
|
/* 1103 */ 's', 't', 'r', 'h', 9, 0,
|
|
/* 1109 */ 's', 't', 't', 'r', 'h', 9, 0,
|
|
/* 1116 */ 'l', 'd', 'u', 'r', 'h', 9, 0,
|
|
/* 1123 */ 's', 't', 'u', 'r', 'h', 9, 0,
|
|
/* 1130 */ 'l', 'd', 'a', 'x', 'r', 'h', 9, 0,
|
|
/* 1138 */ 'l', 'd', 'x', 'r', 'h', 9, 0,
|
|
/* 1145 */ 's', 't', 'l', 'x', 'r', 'h', 9, 0,
|
|
/* 1153 */ 's', 't', 'x', 'r', 'h', 9, 0,
|
|
/* 1160 */ 'l', 'd', 'r', 's', 'h', 9, 0,
|
|
/* 1167 */ 'l', 'd', 't', 'r', 's', 'h', 9, 0,
|
|
/* 1175 */ 'l', 'd', 'u', 'r', 's', 'h', 9, 0,
|
|
/* 1183 */ 's', 'x', 't', 'h', 9, 0,
|
|
/* 1189 */ 'u', 'x', 't', 'h', 9, 0,
|
|
/* 1195 */ 't', 'l', 'b', 'i', 9, 0,
|
|
/* 1201 */ 'b', 'f', 'i', 9, 0,
|
|
/* 1206 */ 'c', 'm', 'h', 'i', 9, 0,
|
|
/* 1212 */ 's', 'l', 'i', 9, 0,
|
|
/* 1217 */ 'm', 'v', 'n', 'i', 9, 0,
|
|
/* 1223 */ 's', 'r', 'i', 9, 0,
|
|
/* 1228 */ 'f', 'r', 'i', 'n', 't', 'i', 9, 0,
|
|
/* 1236 */ 'm', 'o', 'v', 'i', 9, 0,
|
|
/* 1242 */ 'b', 'r', 'k', 9, 0,
|
|
/* 1247 */ 'm', 'o', 'v', 'k', 9, 0,
|
|
/* 1253 */ 's', 'a', 'b', 'a', 'l', 9, 0,
|
|
/* 1260 */ 'u', 'a', 'b', 'a', 'l', 9, 0,
|
|
/* 1267 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', 9, 0,
|
|
/* 1276 */ 's', 'm', 'l', 'a', 'l', 9, 0,
|
|
/* 1283 */ 'u', 'm', 'l', 'a', 'l', 9, 0,
|
|
/* 1290 */ 't', 'b', 'l', 9, 0,
|
|
/* 1295 */ 's', 'm', 's', 'u', 'b', 'l', 9, 0,
|
|
/* 1303 */ 'u', 'm', 's', 'u', 'b', 'l', 9, 0,
|
|
/* 1311 */ 's', 's', 'u', 'b', 'l', 9, 0,
|
|
/* 1318 */ 'u', 's', 'u', 'b', 'l', 9, 0,
|
|
/* 1325 */ 's', 'a', 'b', 'd', 'l', 9, 0,
|
|
/* 1332 */ 'u', 'a', 'b', 'd', 'l', 9, 0,
|
|
/* 1339 */ 's', 'm', 'a', 'd', 'd', 'l', 9, 0,
|
|
/* 1347 */ 'u', 'm', 'a', 'd', 'd', 'l', 9, 0,
|
|
/* 1355 */ 's', 'a', 'd', 'd', 'l', 9, 0,
|
|
/* 1362 */ 'u', 'a', 'd', 'd', 'l', 9, 0,
|
|
/* 1369 */ 'f', 'c', 's', 'e', 'l', 9, 0,
|
|
/* 1376 */ 's', 'q', 's', 'h', 'l', 9, 0,
|
|
/* 1383 */ 'u', 'q', 's', 'h', 'l', 9, 0,
|
|
/* 1390 */ 's', 'q', 'r', 's', 'h', 'l', 9, 0,
|
|
/* 1398 */ 'u', 'q', 'r', 's', 'h', 'l', 9, 0,
|
|
/* 1406 */ 's', 'r', 's', 'h', 'l', 9, 0,
|
|
/* 1413 */ 'u', 'r', 's', 'h', 'l', 9, 0,
|
|
/* 1420 */ 's', 's', 'h', 'l', 9, 0,
|
|
/* 1426 */ 'u', 's', 'h', 'l', 9, 0,
|
|
/* 1432 */ 'b', 'f', 'x', 'i', 'l', 9, 0,
|
|
/* 1439 */ 's', 's', 'h', 'l', 'l', 9, 0,
|
|
/* 1446 */ 'u', 's', 'h', 'l', 'l', 9, 0,
|
|
/* 1453 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', 9, 0,
|
|
/* 1462 */ 'p', 'm', 'u', 'l', 'l', 9, 0,
|
|
/* 1469 */ 's', 'm', 'u', 'l', 'l', 9, 0,
|
|
/* 1476 */ 'u', 'm', 'u', 'l', 'l', 9, 0,
|
|
/* 1483 */ 'b', 's', 'l', 9, 0,
|
|
/* 1488 */ 's', 'q', 'd', 'm', 'l', 's', 'l', 9, 0,
|
|
/* 1497 */ 's', 'm', 'l', 's', 'l', 9, 0,
|
|
/* 1504 */ 'u', 'm', 'l', 's', 'l', 9, 0,
|
|
/* 1511 */ 's', 'y', 's', 'l', 9, 0,
|
|
/* 1517 */ 'f', 'c', 'v', 't', 'l', 9, 0,
|
|
/* 1524 */ 'f', 'm', 'u', 'l', 9, 0,
|
|
/* 1530 */ 'f', 'n', 'm', 'u', 'l', 9, 0,
|
|
/* 1537 */ 'p', 'm', 'u', 'l', 9, 0,
|
|
/* 1543 */ 's', 'h', 'a', '1', 'm', 9, 0,
|
|
/* 1550 */ 's', 'b', 'f', 'm', 9, 0,
|
|
/* 1556 */ 'u', 'b', 'f', 'm', 9, 0,
|
|
/* 1562 */ 'p', 'r', 'f', 'm', 9, 0,
|
|
/* 1568 */ 'f', 'm', 'i', 'n', 'n', 'm', 9, 0,
|
|
/* 1576 */ 'f', 'm', 'a', 'x', 'n', 'm', 9, 0,
|
|
/* 1584 */ 'f', 'r', 'i', 'n', 't', 'm', 9, 0,
|
|
/* 1592 */ 'p', 'r', 'f', 'u', 'm', 9, 0,
|
|
/* 1599 */ 'r', 's', 'u', 'b', 'h', 'n', 9, 0,
|
|
/* 1607 */ 'r', 'a', 'd', 'd', 'h', 'n', 9, 0,
|
|
/* 1615 */ 'f', 'm', 'i', 'n', 9, 0,
|
|
/* 1621 */ 's', 'm', 'i', 'n', 9, 0,
|
|
/* 1627 */ 'u', 'm', 'i', 'n', 9, 0,
|
|
/* 1633 */ 'c', 'c', 'm', 'n', 9, 0,
|
|
/* 1639 */ 'e', 'o', 'n', 9, 0,
|
|
/* 1644 */ 's', 'q', 's', 'h', 'r', 'n', 9, 0,
|
|
/* 1652 */ 'u', 'q', 's', 'h', 'r', 'n', 9, 0,
|
|
/* 1660 */ 's', 'q', 'r', 's', 'h', 'r', 'n', 9, 0,
|
|
/* 1669 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', 9, 0,
|
|
/* 1678 */ 'o', 'r', 'n', 9, 0,
|
|
/* 1683 */ 'f', 'r', 'i', 'n', 't', 'n', 9, 0,
|
|
/* 1691 */ 'f', 'c', 'v', 't', 'n', 9, 0,
|
|
/* 1698 */ 's', 'q', 'x', 't', 'n', 9, 0,
|
|
/* 1705 */ 'u', 'q', 'x', 't', 'n', 9, 0,
|
|
/* 1712 */ 's', 'q', 's', 'h', 'r', 'u', 'n', 9, 0,
|
|
/* 1721 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', 9, 0,
|
|
/* 1731 */ 's', 'q', 'x', 't', 'u', 'n', 9, 0,
|
|
/* 1739 */ 'm', 'v', 'n', 9, 0,
|
|
/* 1744 */ 'm', 'o', 'v', 'n', 9, 0,
|
|
/* 1750 */ 'f', 'c', 'v', 't', 'x', 'n', 9, 0,
|
|
/* 1758 */ 's', 'h', 'a', '1', 'p', 9, 0,
|
|
/* 1765 */ 'f', 'a', 'd', 'd', 'p', 9, 0,
|
|
/* 1772 */ 'l', 'd', 'p', 9, 0,
|
|
/* 1777 */ 's', 'a', 'd', 'a', 'l', 'p', 9, 0,
|
|
/* 1785 */ 'u', 'a', 'd', 'a', 'l', 'p', 9, 0,
|
|
/* 1793 */ 's', 'a', 'd', 'd', 'l', 'p', 9, 0,
|
|
/* 1801 */ 'u', 'a', 'd', 'd', 'l', 'p', 9, 0,
|
|
/* 1809 */ 'f', 'c', 'c', 'm', 'p', 9, 0,
|
|
/* 1816 */ 'f', 'c', 'm', 'p', 9, 0,
|
|
/* 1822 */ 'f', 'm', 'i', 'n', 'n', 'm', 'p', 9, 0,
|
|
/* 1831 */ 'f', 'm', 'a', 'x', 'n', 'm', 'p', 9, 0,
|
|
/* 1840 */ 'l', 'd', 'n', 'p', 9, 0,
|
|
/* 1846 */ 'f', 'm', 'i', 'n', 'p', 9, 0,
|
|
/* 1853 */ 's', 'm', 'i', 'n', 'p', 9, 0,
|
|
/* 1860 */ 'u', 'm', 'i', 'n', 'p', 9, 0,
|
|
/* 1867 */ 's', 't', 'n', 'p', 9, 0,
|
|
/* 1873 */ 'a', 'd', 'r', 'p', 9, 0,
|
|
/* 1879 */ 'f', 'r', 'i', 'n', 't', 'p', 9, 0,
|
|
/* 1887 */ 's', 't', 'p', 9, 0,
|
|
/* 1892 */ 'd', 'u', 'p', 9, 0,
|
|
/* 1897 */ 'l', 'd', 'a', 'x', 'p', 9, 0,
|
|
/* 1904 */ 'f', 'm', 'a', 'x', 'p', 9, 0,
|
|
/* 1911 */ 's', 'm', 'a', 'x', 'p', 9, 0,
|
|
/* 1918 */ 'u', 'm', 'a', 'x', 'p', 9, 0,
|
|
/* 1925 */ 'l', 'd', 'x', 'p', 9, 0,
|
|
/* 1931 */ 's', 't', 'l', 'x', 'p', 9, 0,
|
|
/* 1938 */ 's', 't', 'x', 'p', 9, 0,
|
|
/* 1944 */ 'f', 'c', 'm', 'e', 'q', 9, 0,
|
|
/* 1951 */ 'l', 'd', '1', 'r', 9, 0,
|
|
/* 1957 */ 'l', 'd', '2', 'r', 9, 0,
|
|
/* 1963 */ 'l', 'd', '3', 'r', 9, 0,
|
|
/* 1969 */ 'l', 'd', '4', 'r', 9, 0,
|
|
/* 1975 */ 'l', 'd', 'a', 'r', 9, 0,
|
|
/* 1981 */ 'b', 'r', 9, 0,
|
|
/* 1985 */ 'a', 'd', 'r', 9, 0,
|
|
/* 1990 */ 'l', 'd', 'r', 9, 0,
|
|
/* 1995 */ 's', 'r', 's', 'h', 'r', 9, 0,
|
|
/* 2002 */ 'u', 'r', 's', 'h', 'r', 9, 0,
|
|
/* 2009 */ 's', 's', 'h', 'r', 9, 0,
|
|
/* 2015 */ 'u', 's', 'h', 'r', 9, 0,
|
|
/* 2021 */ 'b', 'l', 'r', 9, 0,
|
|
/* 2026 */ 's', 't', 'l', 'r', 9, 0,
|
|
/* 2032 */ 'e', 'o', 'r', 9, 0,
|
|
/* 2037 */ 'r', 'o', 'r', 9, 0,
|
|
/* 2042 */ 'o', 'r', 'r', 9, 0,
|
|
/* 2047 */ 'a', 's', 'r', 9, 0,
|
|
/* 2052 */ 'l', 's', 'r', 9, 0,
|
|
/* 2057 */ 'm', 's', 'r', 9, 0,
|
|
/* 2062 */ 'l', 'd', 't', 'r', 9, 0,
|
|
/* 2068 */ 's', 't', 'r', 9, 0,
|
|
/* 2073 */ 's', 't', 't', 'r', 9, 0,
|
|
/* 2079 */ 'e', 'x', 't', 'r', 9, 0,
|
|
/* 2085 */ 'l', 'd', 'u', 'r', 9, 0,
|
|
/* 2091 */ 's', 't', 'u', 'r', 9, 0,
|
|
/* 2097 */ 'l', 'd', 'a', 'x', 'r', 9, 0,
|
|
/* 2104 */ 'l', 'd', 'x', 'r', 9, 0,
|
|
/* 2110 */ 's', 't', 'l', 'x', 'r', 9, 0,
|
|
/* 2117 */ 's', 't', 'x', 'r', 9, 0,
|
|
/* 2123 */ 'f', 'c', 'v', 't', 'a', 's', 9, 0,
|
|
/* 2131 */ 'f', 'a', 'b', 's', 9, 0,
|
|
/* 2137 */ 's', 'q', 'a', 'b', 's', 9, 0,
|
|
/* 2144 */ 's', 'u', 'b', 's', 9, 0,
|
|
/* 2150 */ 's', 'b', 'c', 's', 9, 0,
|
|
/* 2156 */ 'a', 'd', 'c', 's', 9, 0,
|
|
/* 2162 */ 'b', 'i', 'c', 's', 9, 0,
|
|
/* 2168 */ 'a', 'd', 'd', 's', 9, 0,
|
|
/* 2174 */ 'a', 'n', 'd', 's', 9, 0,
|
|
/* 2180 */ 'c', 'm', 'h', 's', 9, 0,
|
|
/* 2186 */ 'c', 'l', 's', 9, 0,
|
|
/* 2191 */ 'f', 'm', 'l', 's', 9, 0,
|
|
/* 2197 */ 'f', 'c', 'v', 't', 'm', 's', 9, 0,
|
|
/* 2205 */ 'i', 'n', 's', 9, 0,
|
|
/* 2210 */ 'f', 'c', 'v', 't', 'n', 's', 9, 0,
|
|
/* 2218 */ 'f', 'r', 'e', 'c', 'p', 's', 9, 0,
|
|
/* 2226 */ 'f', 'c', 'v', 't', 'p', 's', 9, 0,
|
|
/* 2234 */ 'm', 'r', 's', 9, 0,
|
|
/* 2239 */ 'f', 'r', 's', 'q', 'r', 't', 's', 9, 0,
|
|
/* 2248 */ 's', 'y', 's', 9, 0,
|
|
/* 2253 */ 'f', 'c', 'v', 't', 'z', 's', 9, 0,
|
|
/* 2261 */ 'a', 't', 9, 0,
|
|
/* 2265 */ 'r', 'e', 't', 9, 0,
|
|
/* 2270 */ 'f', 'a', 'c', 'g', 't', 9, 0,
|
|
/* 2277 */ 'f', 'c', 'm', 'g', 't', 9, 0,
|
|
/* 2284 */ 'r', 'b', 'i', 't', 9, 0,
|
|
/* 2290 */ 'h', 'l', 't', 9, 0,
|
|
/* 2295 */ 'f', 'c', 'm', 'l', 't', 9, 0,
|
|
/* 2302 */ 'c', 'n', 't', 9, 0,
|
|
/* 2307 */ 'h', 'i', 'n', 't', 9, 0,
|
|
/* 2313 */ 'n', 'o', 't', 9, 0,
|
|
/* 2318 */ 'f', 's', 'q', 'r', 't', 9, 0,
|
|
/* 2325 */ 'c', 'm', 't', 's', 't', 9, 0,
|
|
/* 2332 */ 'f', 'c', 'v', 't', 9, 0,
|
|
/* 2338 */ 'e', 'x', 't', 9, 0,
|
|
/* 2343 */ 'f', 'c', 'v', 't', 'a', 'u', 9, 0,
|
|
/* 2351 */ 's', 'q', 's', 'h', 'l', 'u', 9, 0,
|
|
/* 2359 */ 'f', 'c', 'v', 't', 'm', 'u', 9, 0,
|
|
/* 2367 */ 'f', 'c', 'v', 't', 'n', 'u', 9, 0,
|
|
/* 2375 */ 'f', 'c', 'v', 't', 'p', 'u', 9, 0,
|
|
/* 2383 */ 'f', 'c', 'v', 't', 'z', 'u', 9, 0,
|
|
/* 2391 */ 'a', 'd', 'd', 'v', 9, 0,
|
|
/* 2397 */ 'r', 'e', 'v', 9, 0,
|
|
/* 2402 */ 'f', 'd', 'i', 'v', 9, 0,
|
|
/* 2408 */ 's', 'd', 'i', 'v', 9, 0,
|
|
/* 2414 */ 'u', 'd', 'i', 'v', 9, 0,
|
|
/* 2420 */ 's', 'a', 'd', 'd', 'l', 'v', 9, 0,
|
|
/* 2428 */ 'u', 'a', 'd', 'd', 'l', 'v', 9, 0,
|
|
/* 2436 */ 'f', 'm', 'i', 'n', 'n', 'm', 'v', 9, 0,
|
|
/* 2445 */ 'f', 'm', 'a', 'x', 'n', 'm', 'v', 9, 0,
|
|
/* 2454 */ 'f', 'm', 'i', 'n', 'v', 9, 0,
|
|
/* 2461 */ 's', 'm', 'i', 'n', 'v', 9, 0,
|
|
/* 2468 */ 'u', 'm', 'i', 'n', 'v', 9, 0,
|
|
/* 2475 */ 'c', 's', 'i', 'n', 'v', 9, 0,
|
|
/* 2482 */ 'f', 'm', 'o', 'v', 9, 0,
|
|
/* 2488 */ 's', 'm', 'o', 'v', 9, 0,
|
|
/* 2494 */ 'u', 'm', 'o', 'v', 9, 0,
|
|
/* 2500 */ 'f', 'm', 'a', 'x', 'v', 9, 0,
|
|
/* 2507 */ 's', 'm', 'a', 'x', 'v', 9, 0,
|
|
/* 2514 */ 'u', 'm', 'a', 'x', 'v', 9, 0,
|
|
/* 2521 */ 'c', 'r', 'c', '3', '2', 'w', 9, 0,
|
|
/* 2529 */ 's', 's', 'u', 'b', 'w', 9, 0,
|
|
/* 2536 */ 'u', 's', 'u', 'b', 'w', 9, 0,
|
|
/* 2543 */ 'c', 'r', 'c', '3', '2', 'c', 'w', 9, 0,
|
|
/* 2552 */ 's', 'a', 'd', 'd', 'w', 9, 0,
|
|
/* 2559 */ 'u', 'a', 'd', 'd', 'w', 9, 0,
|
|
/* 2566 */ 'l', 'd', 'p', 's', 'w', 9, 0,
|
|
/* 2573 */ 'l', 'd', 'r', 's', 'w', 9, 0,
|
|
/* 2580 */ 'l', 'd', 't', 'r', 's', 'w', 9, 0,
|
|
/* 2588 */ 'l', 'd', 'u', 'r', 's', 'w', 9, 0,
|
|
/* 2596 */ 's', 'x', 't', 'w', 9, 0,
|
|
/* 2602 */ 'c', 'r', 'c', '3', '2', 'x', 9, 0,
|
|
/* 2610 */ 'f', 'm', 'a', 'x', 9, 0,
|
|
/* 2616 */ 's', 'm', 'a', 'x', 9, 0,
|
|
/* 2622 */ 'u', 'm', 'a', 'x', 9, 0,
|
|
/* 2628 */ 't', 'b', 'x', 9, 0,
|
|
/* 2633 */ 'c', 'r', 'c', '3', '2', 'c', 'x', 9, 0,
|
|
/* 2642 */ 'c', 'l', 'r', 'e', 'x', 9, 0,
|
|
/* 2649 */ 's', 'b', 'f', 'x', 9, 0,
|
|
/* 2655 */ 'u', 'b', 'f', 'x', 9, 0,
|
|
/* 2661 */ 'f', 'm', 'u', 'l', 'x', 9, 0,
|
|
/* 2668 */ 'f', 'r', 'e', 'c', 'p', 'x', 9, 0,
|
|
/* 2676 */ 'f', 'r', 'i', 'n', 't', 'x', 9, 0,
|
|
/* 2684 */ 'c', 'b', 'z', 9, 0,
|
|
/* 2689 */ 't', 'b', 'z', 9, 0,
|
|
/* 2694 */ 's', 'b', 'f', 'i', 'z', 9, 0,
|
|
/* 2701 */ 'u', 'b', 'f', 'i', 'z', 9, 0,
|
|
/* 2708 */ 'c', 'l', 'z', 9, 0,
|
|
/* 2713 */ 'c', 'b', 'n', 'z', 9, 0,
|
|
/* 2719 */ 't', 'b', 'n', 'z', 9, 0,
|
|
/* 2725 */ 'f', 'r', 'i', 'n', 't', 'z', 9, 0,
|
|
/* 2733 */ 'm', 'o', 'v', 'z', 9, 0,
|
|
/* 2739 */ 'm', 'o', 'v', 'i', 9, 32, 0,
|
|
/* 2746 */ 'c', 'm', 'n', 32, 0,
|
|
/* 2751 */ 'c', 'm', 'p', 32, 0,
|
|
/* 2756 */ 'b', '.', 0,
|
|
/* 2759 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
|
|
/* 2772 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
|
|
/* 2779 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
|
|
/* 2789 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
|
|
/* 2804 */ 'd', 'r', 'p', 's', 0,
|
|
/* 2809 */ 'e', 'r', 'e', 't', 0,
|
|
};
|
|
#endif
|
|
|
|
// Emit the opcode for the instruction.
|
|
uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)];
|
|
uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)];
|
|
uint64_t Bits = (Bits2 << 32) | Bits1;
|
|
// assert(Bits != 0 && "Cannot print this instruction.");
|
|
#ifndef CAPSTONE_DIET
|
|
SStream_concat(O, "%s", AsmStrs+(Bits & 4095)-1);
|
|
#endif
|
|
|
|
|
|
// Fragment 0 encoded into 8 bits for 159 unique commands.
|
|
//printf("Frag-0: %"PRIu64"\n", (Bits >> 12) & 255);
|
|
switch ((Bits >> 12) & 255) {
|
|
default: // unreachable.
|
|
case 0:
|
|
// DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, DRPS, ERET
|
|
return;
|
|
break;
|
|
case 1:
|
|
// ABS16b, ABS2d, ABS2s, ABS4h, ABS4s, ABS8b, ABS8h, ADDHN2vvv_16b8h, ADD...
|
|
printVPRRegister(MI, 0, O);
|
|
break;
|
|
case 2:
|
|
// ABSdd, ADCSwww, ADCSxxx, ADCwww, ADCxxx, ADDPvv_D_2D, ADDSwww_asr, ADD...
|
|
printOperand(MI, 0, O);
|
|
break;
|
|
case 3:
|
|
// ATix
|
|
printNamedImmOperand(MI, 0, O, &A64AT_ATMapper);
|
|
SStream_concat(O, ", ");
|
|
printOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 4:
|
|
// BLimm, Bimm
|
|
printLabelOperand(MI, 0, O, 26, 4);
|
|
return;
|
|
break;
|
|
case 5:
|
|
// Bcc
|
|
printCondCodeOperand(MI, 0, O);
|
|
SStream_concat(O, " ");
|
|
printLabelOperand(MI, 1, O, 19, 4);
|
|
return;
|
|
break;
|
|
case 6:
|
|
// DCix
|
|
printNamedImmOperand(MI, 0, O, &A64DC_DCMapper);
|
|
SStream_concat(O, ", ");
|
|
printOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 7:
|
|
// DMBi, DSBi
|
|
printNamedImmOperand(MI, 0, O, &A64DB_DBarrierMapper);
|
|
return;
|
|
break;
|
|
case 8:
|
|
// ICi, ICix
|
|
printNamedImmOperand(MI, 0, O, &A64IC_ICMapper);
|
|
break;
|
|
case 9:
|
|
// ISBi
|
|
printNamedImmOperand(MI, 0, O, &A64ISB_ISBMapper);
|
|
return;
|
|
break;
|
|
case 10:
|
|
// LD1LN_B, LD1LN_WB_B_fixed, LD1LN_WB_B_register
|
|
printVectorList(MI, 0, O, A64Layout_VL_B, 1, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 11:
|
|
// LD1LN_D, LD1LN_WB_D_fixed, LD1LN_WB_D_register
|
|
printVectorList(MI, 0, O, A64Layout_VL_D, 1, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 12:
|
|
// LD1LN_H, LD1LN_WB_H_fixed, LD1LN_WB_H_register
|
|
printVectorList(MI, 0, O, A64Layout_VL_H, 1, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 13:
|
|
// LD1LN_S, LD1LN_WB_S_fixed, LD1LN_WB_S_register
|
|
printVectorList(MI, 0, O, A64Layout_VL_S, 1, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 14:
|
|
// LD1R_16B, LD1R_WB_16B_fixed, LD1R_WB_16B_register, LD1WB_16B_fixed, LD...
|
|
printVectorList(MI, 0, O, A64Layout_VL_16B, 1, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 15:
|
|
// LD1R_1D, LD1R_WB_1D_fixed, LD1R_WB_1D_register, LD1WB_1D_fixed, LD1WB_...
|
|
printVectorList(MI, 0, O, A64Layout_VL_1D, 1, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 16:
|
|
// LD1R_2D, LD1R_WB_2D_fixed, LD1R_WB_2D_register, LD1WB_2D_fixed, LD1WB_...
|
|
printVectorList(MI, 0, O, A64Layout_VL_2D, 1, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 17:
|
|
// LD1R_2S, LD1R_WB_2S_fixed, LD1R_WB_2S_register, LD1WB_2S_fixed, LD1WB_...
|
|
printVectorList(MI, 0, O, A64Layout_VL_2S, 1, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 18:
|
|
// LD1R_4H, LD1R_WB_4H_fixed, LD1R_WB_4H_register, LD1WB_4H_fixed, LD1WB_...
|
|
printVectorList(MI, 0, O, A64Layout_VL_4H, 1, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 19:
|
|
// LD1R_4S, LD1R_WB_4S_fixed, LD1R_WB_4S_register, LD1WB_4S_fixed, LD1WB_...
|
|
printVectorList(MI, 0, O, A64Layout_VL_4S, 1, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 20:
|
|
// LD1R_8B, LD1R_WB_8B_fixed, LD1R_WB_8B_register, LD1WB_8B_fixed, LD1WB_...
|
|
printVectorList(MI, 0, O, A64Layout_VL_8B, 1, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 21:
|
|
// LD1R_8H, LD1R_WB_8H_fixed, LD1R_WB_8H_register, LD1WB_8H_fixed, LD1WB_...
|
|
printVectorList(MI, 0, O, A64Layout_VL_8H, 1, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 22:
|
|
// LD1x2WB_16B_fixed, LD1x2WB_16B_register, LD1x2_16B, LD2R_16B, LD2R_WB_...
|
|
printVectorList(MI, 0, O, A64Layout_VL_16B, 2, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 23:
|
|
// LD1x2WB_1D_fixed, LD1x2WB_1D_register, LD1x2_1D, LD2R_1D, LD2R_WB_1D_f...
|
|
printVectorList(MI, 0, O, A64Layout_VL_1D, 2, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 24:
|
|
// LD1x2WB_2D_fixed, LD1x2WB_2D_register, LD1x2_2D, LD2R_2D, LD2R_WB_2D_f...
|
|
printVectorList(MI, 0, O, A64Layout_VL_2D, 2, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 25:
|
|
// LD1x2WB_2S_fixed, LD1x2WB_2S_register, LD1x2_2S, LD2R_2S, LD2R_WB_2S_f...
|
|
printVectorList(MI, 0, O, A64Layout_VL_2S, 2, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 26:
|
|
// LD1x2WB_4H_fixed, LD1x2WB_4H_register, LD1x2_4H, LD2R_4H, LD2R_WB_4H_f...
|
|
printVectorList(MI, 0, O, A64Layout_VL_4H, 2, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 27:
|
|
// LD1x2WB_4S_fixed, LD1x2WB_4S_register, LD1x2_4S, LD2R_4S, LD2R_WB_4S_f...
|
|
printVectorList(MI, 0, O, A64Layout_VL_4S, 2, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 28:
|
|
// LD1x2WB_8B_fixed, LD1x2WB_8B_register, LD1x2_8B, LD2R_8B, LD2R_WB_8B_f...
|
|
printVectorList(MI, 0, O, A64Layout_VL_8B, 2, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 29:
|
|
// LD1x2WB_8H_fixed, LD1x2WB_8H_register, LD1x2_8H, LD2R_8H, LD2R_WB_8H_f...
|
|
printVectorList(MI, 0, O, A64Layout_VL_8H, 2, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 30:
|
|
// LD1x3WB_16B_fixed, LD1x3WB_16B_register, LD1x3_16B, LD3R_16B, LD3R_WB_...
|
|
printVectorList(MI, 0, O, A64Layout_VL_16B, 3, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 31:
|
|
// LD1x3WB_1D_fixed, LD1x3WB_1D_register, LD1x3_1D, LD3R_1D, LD3R_WB_1D_f...
|
|
printVectorList(MI, 0, O, A64Layout_VL_1D, 3, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 32:
|
|
// LD1x3WB_2D_fixed, LD1x3WB_2D_register, LD1x3_2D, LD3R_2D, LD3R_WB_2D_f...
|
|
printVectorList(MI, 0, O, A64Layout_VL_2D, 3, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 33:
|
|
// LD1x3WB_2S_fixed, LD1x3WB_2S_register, LD1x3_2S, LD3R_2S, LD3R_WB_2S_f...
|
|
printVectorList(MI, 0, O, A64Layout_VL_2S, 3, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 34:
|
|
// LD1x3WB_4H_fixed, LD1x3WB_4H_register, LD1x3_4H, LD3R_4H, LD3R_WB_4H_f...
|
|
printVectorList(MI, 0, O, A64Layout_VL_4H, 3, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 35:
|
|
// LD1x3WB_4S_fixed, LD1x3WB_4S_register, LD1x3_4S, LD3R_4S, LD3R_WB_4S_f...
|
|
printVectorList(MI, 0, O, A64Layout_VL_4S, 3, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 36:
|
|
// LD1x3WB_8B_fixed, LD1x3WB_8B_register, LD1x3_8B, LD3R_8B, LD3R_WB_8B_f...
|
|
printVectorList(MI, 0, O, A64Layout_VL_8B, 3, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 37:
|
|
// LD1x3WB_8H_fixed, LD1x3WB_8H_register, LD1x3_8H, LD3R_8H, LD3R_WB_8H_f...
|
|
printVectorList(MI, 0, O, A64Layout_VL_8H, 3, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 38:
|
|
// LD1x4WB_16B_fixed, LD1x4WB_16B_register, LD1x4_16B, LD4R_16B, LD4R_WB_...
|
|
printVectorList(MI, 0, O, A64Layout_VL_16B, 4, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 39:
|
|
// LD1x4WB_1D_fixed, LD1x4WB_1D_register, LD1x4_1D, LD4R_1D, LD4R_WB_1D_f...
|
|
printVectorList(MI, 0, O, A64Layout_VL_1D, 4, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 40:
|
|
// LD1x4WB_2D_fixed, LD1x4WB_2D_register, LD1x4_2D, LD4R_2D, LD4R_WB_2D_f...
|
|
printVectorList(MI, 0, O, A64Layout_VL_2D, 4, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 41:
|
|
// LD1x4WB_2S_fixed, LD1x4WB_2S_register, LD1x4_2S, LD4R_2S, LD4R_WB_2S_f...
|
|
printVectorList(MI, 0, O, A64Layout_VL_2S, 4, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 42:
|
|
// LD1x4WB_4H_fixed, LD1x4WB_4H_register, LD1x4_4H, LD4R_4H, LD4R_WB_4H_f...
|
|
printVectorList(MI, 0, O, A64Layout_VL_4H, 4, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 43:
|
|
// LD1x4WB_4S_fixed, LD1x4WB_4S_register, LD1x4_4S, LD4R_4S, LD4R_WB_4S_f...
|
|
printVectorList(MI, 0, O, A64Layout_VL_4S, 4, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 44:
|
|
// LD1x4WB_8B_fixed, LD1x4WB_8B_register, LD1x4_8B, LD4R_8B, LD4R_WB_8B_f...
|
|
printVectorList(MI, 0, O, A64Layout_VL_8B, 4, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 45:
|
|
// LD1x4WB_8H_fixed, LD1x4WB_8H_register, LD1x4_8H, LD4R_8H, LD4R_WB_8H_f...
|
|
printVectorList(MI, 0, O, A64Layout_VL_8H, 4, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 46:
|
|
// LD2LN_B, LD2LN_WB_B_fixed, LD2LN_WB_B_register
|
|
printVectorList(MI, 0, O, A64Layout_VL_B, 2, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 47:
|
|
// LD2LN_D, LD2LN_WB_D_fixed, LD2LN_WB_D_register
|
|
printVectorList(MI, 0, O, A64Layout_VL_D, 2, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 48:
|
|
// LD2LN_H, LD2LN_WB_H_fixed, LD2LN_WB_H_register
|
|
printVectorList(MI, 0, O, A64Layout_VL_H, 2, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 49:
|
|
// LD2LN_S, LD2LN_WB_S_fixed, LD2LN_WB_S_register
|
|
printVectorList(MI, 0, O, A64Layout_VL_S, 2, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 50:
|
|
// LD3LN_B, LD3LN_WB_B_fixed, LD3LN_WB_B_register
|
|
printVectorList(MI, 0, O, A64Layout_VL_B, 3, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 51:
|
|
// LD3LN_D, LD3LN_WB_D_fixed, LD3LN_WB_D_register
|
|
printVectorList(MI, 0, O, A64Layout_VL_D, 3, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 52:
|
|
// LD3LN_H, LD3LN_WB_H_fixed, LD3LN_WB_H_register
|
|
printVectorList(MI, 0, O, A64Layout_VL_H, 3, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 53:
|
|
// LD3LN_S, LD3LN_WB_S_fixed, LD3LN_WB_S_register
|
|
printVectorList(MI, 0, O, A64Layout_VL_S, 3, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 54:
|
|
// LD4LN_B, LD4LN_WB_B_fixed, LD4LN_WB_B_register
|
|
printVectorList(MI, 0, O, A64Layout_VL_B, 4, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 55:
|
|
// LD4LN_D, LD4LN_WB_D_fixed, LD4LN_WB_D_register
|
|
printVectorList(MI, 0, O, A64Layout_VL_D, 4, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 56:
|
|
// LD4LN_H, LD4LN_WB_H_fixed, LD4LN_WB_H_register
|
|
printVectorList(MI, 0, O, A64Layout_VL_H, 4, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 57:
|
|
// LD4LN_S, LD4LN_WB_S_fixed, LD4LN_WB_S_register
|
|
printVectorList(MI, 0, O, A64Layout_VL_S, 4, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 58:
|
|
// LS16_PostInd_STR, LS16_PreInd_STR, LS32_PostInd_STR, LS32_PreInd_STR, ...
|
|
printOperand(MI, 1, O);
|
|
break;
|
|
case 59:
|
|
// MSRii
|
|
printNamedImmOperand(MI, 0, O, &A64PState_PStateMapper);
|
|
SStream_concat(O, ", ");
|
|
printOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 60:
|
|
// MSRix
|
|
printMSROperand(MI, 0, O);
|
|
SStream_concat(O, ", ");
|
|
printOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 61:
|
|
// PRFM, PRFM_Wm_RegOffset, PRFM_Xm_RegOffset, PRFM_lit, PRFUM
|
|
printNamedImmOperand(MI, 0, O, &A64PRFM_PRFMMapper);
|
|
break;
|
|
case 62:
|
|
// ST1LN_B
|
|
printVectorList(MI, 1, O, A64Layout_VL_B, 1, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 2, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 63:
|
|
// ST1LN_D
|
|
printVectorList(MI, 1, O, A64Layout_VL_D, 1, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 2, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 64:
|
|
// ST1LN_H
|
|
printVectorList(MI, 1, O, A64Layout_VL_H, 1, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 2, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 65:
|
|
// ST1LN_S
|
|
printVectorList(MI, 1, O, A64Layout_VL_S, 1, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 2, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 66:
|
|
// ST1LN_WB_B_fixed, ST1LN_WB_B_register
|
|
printVectorList(MI, 3, O, A64Layout_VL_B, 1, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 4, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 67:
|
|
// ST1LN_WB_D_fixed, ST1LN_WB_D_register
|
|
printVectorList(MI, 3, O, A64Layout_VL_D, 1, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 4, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 68:
|
|
// ST1LN_WB_H_fixed, ST1LN_WB_H_register
|
|
printVectorList(MI, 3, O, A64Layout_VL_H, 1, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 4, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 69:
|
|
// ST1LN_WB_S_fixed, ST1LN_WB_S_register
|
|
printVectorList(MI, 3, O, A64Layout_VL_S, 1, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 4, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 70:
|
|
// ST1WB_16B_fixed, ST1WB_16B_register
|
|
printVectorList(MI, 3, O, A64Layout_VL_16B, 1, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 71:
|
|
// ST1WB_1D_fixed, ST1WB_1D_register
|
|
printVectorList(MI, 3, O, A64Layout_VL_1D, 1, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 72:
|
|
// ST1WB_2D_fixed, ST1WB_2D_register
|
|
printVectorList(MI, 3, O, A64Layout_VL_2D, 1, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 73:
|
|
// ST1WB_2S_fixed, ST1WB_2S_register
|
|
printVectorList(MI, 3, O, A64Layout_VL_2S, 1, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 74:
|
|
// ST1WB_4H_fixed, ST1WB_4H_register
|
|
printVectorList(MI, 3, O, A64Layout_VL_4H, 1, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 75:
|
|
// ST1WB_4S_fixed, ST1WB_4S_register
|
|
printVectorList(MI, 3, O, A64Layout_VL_4S, 1, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 76:
|
|
// ST1WB_8B_fixed, ST1WB_8B_register
|
|
printVectorList(MI, 3, O, A64Layout_VL_8B, 1, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 77:
|
|
// ST1WB_8H_fixed, ST1WB_8H_register
|
|
printVectorList(MI, 3, O, A64Layout_VL_8H, 1, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 78:
|
|
// ST1_16B
|
|
printVectorList(MI, 1, O, A64Layout_VL_16B, 1, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 79:
|
|
// ST1_1D
|
|
printVectorList(MI, 1, O, A64Layout_VL_1D, 1, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 80:
|
|
// ST1_2D
|
|
printVectorList(MI, 1, O, A64Layout_VL_2D, 1, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 81:
|
|
// ST1_2S
|
|
printVectorList(MI, 1, O, A64Layout_VL_2S, 1, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 82:
|
|
// ST1_4H
|
|
printVectorList(MI, 1, O, A64Layout_VL_4H, 1, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 83:
|
|
// ST1_4S
|
|
printVectorList(MI, 1, O, A64Layout_VL_4S, 1, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 84:
|
|
// ST1_8B
|
|
printVectorList(MI, 1, O, A64Layout_VL_8B, 1, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 85:
|
|
// ST1_8H
|
|
printVectorList(MI, 1, O, A64Layout_VL_8H, 1, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 86:
|
|
// ST1x2WB_16B_fixed, ST1x2WB_16B_register, ST2WB_16B_fixed, ST2WB_16B_re...
|
|
printVectorList(MI, 3, O, A64Layout_VL_16B, 2, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 87:
|
|
// ST1x2WB_1D_fixed, ST1x2WB_1D_register
|
|
printVectorList(MI, 3, O, A64Layout_VL_1D, 2, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 88:
|
|
// ST1x2WB_2D_fixed, ST1x2WB_2D_register, ST2WB_2D_fixed, ST2WB_2D_regist...
|
|
printVectorList(MI, 3, O, A64Layout_VL_2D, 2, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 89:
|
|
// ST1x2WB_2S_fixed, ST1x2WB_2S_register, ST2WB_2S_fixed, ST2WB_2S_regist...
|
|
printVectorList(MI, 3, O, A64Layout_VL_2S, 2, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 90:
|
|
// ST1x2WB_4H_fixed, ST1x2WB_4H_register, ST2WB_4H_fixed, ST2WB_4H_regist...
|
|
printVectorList(MI, 3, O, A64Layout_VL_4H, 2, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 91:
|
|
// ST1x2WB_4S_fixed, ST1x2WB_4S_register, ST2WB_4S_fixed, ST2WB_4S_regist...
|
|
printVectorList(MI, 3, O, A64Layout_VL_4S, 2, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 92:
|
|
// ST1x2WB_8B_fixed, ST1x2WB_8B_register, ST2WB_8B_fixed, ST2WB_8B_regist...
|
|
printVectorList(MI, 3, O, A64Layout_VL_8B, 2, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 93:
|
|
// ST1x2WB_8H_fixed, ST1x2WB_8H_register, ST2WB_8H_fixed, ST2WB_8H_regist...
|
|
printVectorList(MI, 3, O, A64Layout_VL_8H, 2, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 94:
|
|
// ST1x2_16B, ST2_16B
|
|
printVectorList(MI, 1, O, A64Layout_VL_16B, 2, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 95:
|
|
// ST1x2_1D
|
|
printVectorList(MI, 1, O, A64Layout_VL_1D, 2, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 96:
|
|
// ST1x2_2D, ST2_2D
|
|
printVectorList(MI, 1, O, A64Layout_VL_2D, 2, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 97:
|
|
// ST1x2_2S, ST2_2S
|
|
printVectorList(MI, 1, O, A64Layout_VL_2S, 2, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 98:
|
|
// ST1x2_4H, ST2_4H
|
|
printVectorList(MI, 1, O, A64Layout_VL_4H, 2, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 99:
|
|
// ST1x2_4S, ST2_4S
|
|
printVectorList(MI, 1, O, A64Layout_VL_4S, 2, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 100:
|
|
// ST1x2_8B, ST2_8B
|
|
printVectorList(MI, 1, O, A64Layout_VL_8B, 2, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 101:
|
|
// ST1x2_8H, ST2_8H
|
|
printVectorList(MI, 1, O, A64Layout_VL_8H, 2, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 102:
|
|
// ST1x3WB_16B_fixed, ST1x3WB_16B_register, ST3WB_16B_fixed, ST3WB_16B_re...
|
|
printVectorList(MI, 3, O, A64Layout_VL_16B, 3, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 103:
|
|
// ST1x3WB_1D_fixed, ST1x3WB_1D_register
|
|
printVectorList(MI, 3, O, A64Layout_VL_1D, 3, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 104:
|
|
// ST1x3WB_2D_fixed, ST1x3WB_2D_register, ST3WB_2D_fixed, ST3WB_2D_regist...
|
|
printVectorList(MI, 3, O, A64Layout_VL_2D, 3, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 105:
|
|
// ST1x3WB_2S_fixed, ST1x3WB_2S_register, ST3WB_2S_fixed, ST3WB_2S_regist...
|
|
printVectorList(MI, 3, O, A64Layout_VL_2S, 3, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 106:
|
|
// ST1x3WB_4H_fixed, ST1x3WB_4H_register, ST3WB_4H_fixed, ST3WB_4H_regist...
|
|
printVectorList(MI, 3, O, A64Layout_VL_4H, 3, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 107:
|
|
// ST1x3WB_4S_fixed, ST1x3WB_4S_register, ST3WB_4S_fixed, ST3WB_4S_regist...
|
|
printVectorList(MI, 3, O, A64Layout_VL_4S, 3, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 108:
|
|
// ST1x3WB_8B_fixed, ST1x3WB_8B_register, ST3WB_8B_fixed, ST3WB_8B_regist...
|
|
printVectorList(MI, 3, O, A64Layout_VL_8B, 3, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 109:
|
|
// ST1x3WB_8H_fixed, ST1x3WB_8H_register, ST3WB_8H_fixed, ST3WB_8H_regist...
|
|
printVectorList(MI, 3, O, A64Layout_VL_8H, 3, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 110:
|
|
// ST1x3_16B, ST3_16B
|
|
printVectorList(MI, 1, O, A64Layout_VL_16B, 3, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 111:
|
|
// ST1x3_1D
|
|
printVectorList(MI, 1, O, A64Layout_VL_1D, 3, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 112:
|
|
// ST1x3_2D, ST3_2D
|
|
printVectorList(MI, 1, O, A64Layout_VL_2D, 3, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 113:
|
|
// ST1x3_2S, ST3_2S
|
|
printVectorList(MI, 1, O, A64Layout_VL_2S, 3, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 114:
|
|
// ST1x3_4H, ST3_4H
|
|
printVectorList(MI, 1, O, A64Layout_VL_4H, 3, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 115:
|
|
// ST1x3_4S, ST3_4S
|
|
printVectorList(MI, 1, O, A64Layout_VL_4S, 3, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 116:
|
|
// ST1x3_8B, ST3_8B
|
|
printVectorList(MI, 1, O, A64Layout_VL_8B, 3, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 117:
|
|
// ST1x3_8H, ST3_8H
|
|
printVectorList(MI, 1, O, A64Layout_VL_8H, 3, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 118:
|
|
// ST1x4WB_16B_fixed, ST1x4WB_16B_register, ST4WB_16B_fixed, ST4WB_16B_re...
|
|
printVectorList(MI, 3, O, A64Layout_VL_16B, 4, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 119:
|
|
// ST1x4WB_1D_fixed, ST1x4WB_1D_register
|
|
printVectorList(MI, 3, O, A64Layout_VL_1D, 4, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 120:
|
|
// ST1x4WB_2D_fixed, ST1x4WB_2D_register, ST4WB_2D_fixed, ST4WB_2D_regist...
|
|
printVectorList(MI, 3, O, A64Layout_VL_2D, 4, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 121:
|
|
// ST1x4WB_2S_fixed, ST1x4WB_2S_register, ST4WB_2S_fixed, ST4WB_2S_regist...
|
|
printVectorList(MI, 3, O, A64Layout_VL_2S, 4, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 122:
|
|
// ST1x4WB_4H_fixed, ST1x4WB_4H_register, ST4WB_4H_fixed, ST4WB_4H_regist...
|
|
printVectorList(MI, 3, O, A64Layout_VL_4H, 4, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 123:
|
|
// ST1x4WB_4S_fixed, ST1x4WB_4S_register, ST4WB_4S_fixed, ST4WB_4S_regist...
|
|
printVectorList(MI, 3, O, A64Layout_VL_4S, 4, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 124:
|
|
// ST1x4WB_8B_fixed, ST1x4WB_8B_register, ST4WB_8B_fixed, ST4WB_8B_regist...
|
|
printVectorList(MI, 3, O, A64Layout_VL_8B, 4, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 125:
|
|
// ST1x4WB_8H_fixed, ST1x4WB_8H_register, ST4WB_8H_fixed, ST4WB_8H_regist...
|
|
printVectorList(MI, 3, O, A64Layout_VL_8H, 4, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 126:
|
|
// ST1x4_16B, ST4_16B
|
|
printVectorList(MI, 1, O, A64Layout_VL_16B, 4, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 127:
|
|
// ST1x4_1D
|
|
printVectorList(MI, 1, O, A64Layout_VL_1D, 4, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 128:
|
|
// ST1x4_2D, ST4_2D
|
|
printVectorList(MI, 1, O, A64Layout_VL_2D, 4, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 129:
|
|
// ST1x4_2S, ST4_2S
|
|
printVectorList(MI, 1, O, A64Layout_VL_2S, 4, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 130:
|
|
// ST1x4_4H, ST4_4H
|
|
printVectorList(MI, 1, O, A64Layout_VL_4H, 4, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 131:
|
|
// ST1x4_4S, ST4_4S
|
|
printVectorList(MI, 1, O, A64Layout_VL_4S, 4, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 132:
|
|
// ST1x4_8B, ST4_8B
|
|
printVectorList(MI, 1, O, A64Layout_VL_8B, 4, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 133:
|
|
// ST1x4_8H, ST4_8H
|
|
printVectorList(MI, 1, O, A64Layout_VL_8H, 4, MRI);
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 134:
|
|
// ST2LN_B
|
|
printVectorList(MI, 1, O, A64Layout_VL_B, 2, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 2, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 135:
|
|
// ST2LN_D
|
|
printVectorList(MI, 1, O, A64Layout_VL_D, 2, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 2, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 136:
|
|
// ST2LN_H
|
|
printVectorList(MI, 1, O, A64Layout_VL_H, 2, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 2, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 137:
|
|
// ST2LN_S
|
|
printVectorList(MI, 1, O, A64Layout_VL_S, 2, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 2, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 138:
|
|
// ST2LN_WB_B_fixed, ST2LN_WB_B_register
|
|
printVectorList(MI, 3, O, A64Layout_VL_B, 2, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 4, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 139:
|
|
// ST2LN_WB_D_fixed, ST2LN_WB_D_register
|
|
printVectorList(MI, 3, O, A64Layout_VL_D, 2, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 4, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 140:
|
|
// ST2LN_WB_H_fixed, ST2LN_WB_H_register
|
|
printVectorList(MI, 3, O, A64Layout_VL_H, 2, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 4, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 141:
|
|
// ST2LN_WB_S_fixed, ST2LN_WB_S_register
|
|
printVectorList(MI, 3, O, A64Layout_VL_S, 2, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 4, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 142:
|
|
// ST3LN_B
|
|
printVectorList(MI, 1, O, A64Layout_VL_B, 3, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 2, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 143:
|
|
// ST3LN_D
|
|
printVectorList(MI, 1, O, A64Layout_VL_D, 3, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 2, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 144:
|
|
// ST3LN_H
|
|
printVectorList(MI, 1, O, A64Layout_VL_H, 3, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 2, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 145:
|
|
// ST3LN_S
|
|
printVectorList(MI, 1, O, A64Layout_VL_S, 3, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 2, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 146:
|
|
// ST3LN_WB_B_fixed, ST3LN_WB_B_register
|
|
printVectorList(MI, 3, O, A64Layout_VL_B, 3, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 4, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 147:
|
|
// ST3LN_WB_D_fixed, ST3LN_WB_D_register
|
|
printVectorList(MI, 3, O, A64Layout_VL_D, 3, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 4, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 148:
|
|
// ST3LN_WB_H_fixed, ST3LN_WB_H_register
|
|
printVectorList(MI, 3, O, A64Layout_VL_H, 3, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 4, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 149:
|
|
// ST3LN_WB_S_fixed, ST3LN_WB_S_register
|
|
printVectorList(MI, 3, O, A64Layout_VL_S, 3, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 4, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 150:
|
|
// ST4LN_B
|
|
printVectorList(MI, 1, O, A64Layout_VL_B, 4, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 2, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 151:
|
|
// ST4LN_D
|
|
printVectorList(MI, 1, O, A64Layout_VL_D, 4, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 2, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 152:
|
|
// ST4LN_H
|
|
printVectorList(MI, 1, O, A64Layout_VL_H, 4, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 2, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 153:
|
|
// ST4LN_S
|
|
printVectorList(MI, 1, O, A64Layout_VL_S, 4, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 2, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 0, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 154:
|
|
// ST4LN_WB_B_fixed, ST4LN_WB_B_register
|
|
printVectorList(MI, 3, O, A64Layout_VL_B, 4, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 4, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 155:
|
|
// ST4LN_WB_D_fixed, ST4LN_WB_D_register
|
|
printVectorList(MI, 3, O, A64Layout_VL_D, 4, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 4, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 156:
|
|
// ST4LN_WB_H_fixed, ST4LN_WB_H_register
|
|
printVectorList(MI, 3, O, A64Layout_VL_H, 4, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 4, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 157:
|
|
// ST4LN_WB_S_fixed, ST4LN_WB_S_register
|
|
printVectorList(MI, 3, O, A64Layout_VL_S, 4, MRI);
|
|
SStream_concat(O, "[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 4, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 158:
|
|
// TLBIi, TLBIix
|
|
printNamedImmOperand(MI, 0, O, &A64TLBI_TLBIMapper);
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 1 encoded into 5 bits for 20 unique commands.
|
|
//printf("Frag-1: %"PRIu64"\n", (Bits >> 20) & 31);
|
|
switch ((Bits >> 20) & 31) {
|
|
default: // unreachable.
|
|
case 0:
|
|
// ABS16b, ADDHN2vvv_16b8h, ADDP_16B, ADDvvv_16B, AESD, AESE, AESIMC, AES...
|
|
SStream_concat(O, ".16b, ");
|
|
break;
|
|
case 1:
|
|
// ABS2d, ADDP_2D, ADDvvv_2D, CMEQvvi_2D, CMEQvvv_2D, CMGEvvi_2D, CMGEvvv...
|
|
SStream_concat(O, ".2d, ");
|
|
break;
|
|
case 2:
|
|
// ABS2s, ADDHNvvv_2s2d, ADDP_2S, ADDvvv_2S, BICvi_lsl_2S, CLS2s, CLZ2s, ...
|
|
SStream_concat(O, ".2s, ");
|
|
break;
|
|
case 3:
|
|
// ABS4h, ADDHNvvv_4h4s, ADDP_4H, ADDvvv_4H, BICvi_lsl_4H, CLS4h, CLZ4h, ...
|
|
SStream_concat(O, ".4h, ");
|
|
break;
|
|
case 4:
|
|
// ABS4s, ADDHN2vvv_4s2d, ADDP_4S, ADDvvv_4S, BICvi_lsl_4S, CLS4s, CLZ4s,...
|
|
SStream_concat(O, ".4s, ");
|
|
break;
|
|
case 5:
|
|
// ABS8b, ADDHNvvv_8b8h, ADDP_8B, ADDvvv_8B, ANDvvv_8B, BICvvv_8B, BIFvvv...
|
|
SStream_concat(O, ".8b, ");
|
|
break;
|
|
case 6:
|
|
// ABS8h, ADDHN2vvv_8h4s, ADDP_8H, ADDvvv_8H, BICvi_lsl_8H, CLS8h, CLZ8h,...
|
|
SStream_concat(O, ".8h, ");
|
|
break;
|
|
case 7:
|
|
// ABSdd, ADCSwww, ADCSxxx, ADCwww, ADCxxx, ADDPvv_D_2D, ADDSwww_asr, ADD...
|
|
SStream_concat(O, ", ");
|
|
break;
|
|
case 8:
|
|
// BLRx, BRKi, BRx, CLREXi, DCPS1i, DCPS2i, DCPS3i, HINTi, HLTi, HVCi, IC...
|
|
return;
|
|
break;
|
|
case 9:
|
|
// FMOVvx, INSELd, INSdx
|
|
SStream_concat(O, ".d[");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 10:
|
|
// INSELb, INSbw
|
|
SStream_concat(O, ".b[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 3, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
break;
|
|
case 11:
|
|
// INSELh, INShw
|
|
SStream_concat(O, ".h[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 3, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
break;
|
|
case 12:
|
|
// INSELs, INSsw
|
|
SStream_concat(O, ".s[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 3, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
break;
|
|
case 13:
|
|
// LD1LN_B, LD1LN_D, LD1LN_H, LD1LN_S, LD2LN_B, LD2LN_D, LD2LN_H, LD2LN_S...
|
|
printUImmBareOperand(MI, 3, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 14:
|
|
// LD1LN_WB_B_fixed, LD1LN_WB_B_register, LD1LN_WB_D_fixed, LD1LN_WB_D_re...
|
|
printUImmBareOperand(MI, 5, O);
|
|
set_mem_access(MI, false);
|
|
SStream_concat(O, "], [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 2, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 15:
|
|
// LD1R_16B, LD1R_1D, LD1R_2D, LD1R_2S, LD1R_4H, LD1R_4S, LD1R_8B, LD1R_8...
|
|
printOperand(MI, 1, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 16:
|
|
// LD1R_WB_16B_fixed, LD1R_WB_16B_register, LD1R_WB_1D_fixed, LD1R_WB_1D_...
|
|
printOperand(MI, 2, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 17:
|
|
// LDAR_byte, LDAR_dword, LDAR_hword, LDAR_word, LDAXR_byte, LDAXR_dword,...
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 18:
|
|
// PMULL2vvv_1q2d, PMULLvvv_1q1d
|
|
SStream_concat(O, ".1q, ");
|
|
printVPRRegister(MI, 1, O);
|
|
break;
|
|
case 19:
|
|
// SADALP2s1d, SADDLP2s1d, UADALP2s1d, UADDLP2s1d
|
|
SStream_concat(O, ".1d, ");
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 2 encoded into 5 bits for 30 unique commands.
|
|
//printf("Frag-2: %"PRIu64"\n", (Bits >> 25) & 31);
|
|
switch ((Bits >> 25) & 31) {
|
|
default: // unreachable.
|
|
case 0:
|
|
// ABS16b, ABS2d, ABS2s, ABS4h, ABS4s, ABS8b, ABS8h, ADDHNvvv_2s2d, ADDHN...
|
|
printVPRRegister(MI, 1, O);
|
|
break;
|
|
case 1:
|
|
// ABSdd, ADCSwww, ADCSxxx, ADCwww, ADCxxx, ADDSwww_asr, ADDSwww_lsl, ADD...
|
|
printOperand(MI, 1, O);
|
|
break;
|
|
case 2:
|
|
// ADDHN2vvv_16b8h, ADDHN2vvv_4s2d, ADDHN2vvv_8h4s, AESD, AESE, BIFvvv_16...
|
|
printVPRRegister(MI, 2, O);
|
|
break;
|
|
case 3:
|
|
// ADDwwi_lsl0_cmp, ADDxxi_lsl0_cmp, SUBwwi_lsl0_cmp, SUBxxi_lsl0_cmp
|
|
printAddSubImmLSL0Operand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 4:
|
|
// ADDwwi_lsl12_cmp, ADDxxi_lsl12_cmp, SUBwwi_lsl12_cmp, SUBxxi_lsl12_cmp
|
|
printAddSubImmLSL12Operand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 5:
|
|
// ADRPxi
|
|
printLabelOperand(MI, 1, O, 21, 4096);
|
|
return;
|
|
break;
|
|
case 6:
|
|
// ADRxi
|
|
printLabelOperand(MI, 1, O, 21, 1);
|
|
return;
|
|
break;
|
|
case 7:
|
|
// BFIwwii, BFIxxii, BFMwwii, BFMxxii, BFXILwwii, BFXILxxii, FMLAddv_2D, ...
|
|
printOperand(MI, 2, O);
|
|
break;
|
|
case 8:
|
|
// BICvi_lsl_2S, BICvi_lsl_4H, BICvi_lsl_4S, BICvi_lsl_8H, ORRvi_lsl_2S, ...
|
|
printUImmHexOperand(MI, 2, O);
|
|
break;
|
|
case 9:
|
|
// CBNZw, CBNZx, CBZw, CBZx, LDRSWx_lit, LDRd_lit, LDRq_lit, LDRs_lit, LD...
|
|
printLabelOperand(MI, 1, O, 19, 4);
|
|
return;
|
|
break;
|
|
case 10:
|
|
// FCMPdi_quiet, FCMPdi_sig, FCMPsi_quiet, FCMPsi_sig
|
|
printFPZeroOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 11:
|
|
// FMOVdi, FMOVsi, FMOVvi_2D, FMOVvi_2S, FMOVvi_4S
|
|
printFPImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 12:
|
|
// FMOVvx
|
|
printBareImmOperand(MI, 2, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 13:
|
|
// INSELd, INSdx
|
|
printUImmBareOperand(MI, 3, O);
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
break;
|
|
case 14:
|
|
// MOVIdi, MOVIvi_2D
|
|
printNeonUImm64MaskOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 15:
|
|
// MOVIvi_16B, MOVIvi_8B, MOVIvi_lsl_2S, MOVIvi_lsl_4H, MOVIvi_lsl_4S, MO...
|
|
printUImmHexOperand(MI, 1, O);
|
|
break;
|
|
case 16:
|
|
// MOVKwii, MOVKxii
|
|
printMoveWideImmOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 17:
|
|
// MOVNwii, MOVNxii, MOVZwii, MOVZxii
|
|
printMoveWideImmOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 18:
|
|
// MRSxi
|
|
printMRSOperand(MI, 1, O);
|
|
return;
|
|
break;
|
|
case 19:
|
|
// PMULL2vvv_1q2d
|
|
SStream_concat(O, ".2d, ");
|
|
printVPRRegister(MI, 2, O);
|
|
SStream_concat(O, ".2d");
|
|
return;
|
|
break;
|
|
case 20:
|
|
// PMULLvvv_1q1d
|
|
SStream_concat(O, ".1d, ");
|
|
printVPRRegister(MI, 2, O);
|
|
SStream_concat(O, ".1d");
|
|
return;
|
|
break;
|
|
case 21:
|
|
// SYSiccix
|
|
printCRxOperand(MI, 1, O);
|
|
SStream_concat(O, ", ");
|
|
printCRxOperand(MI, 2, O);
|
|
SStream_concat(O, ", ");
|
|
printOperand(MI, 3, O);
|
|
SStream_concat(O, ", ");
|
|
printOperand(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 22:
|
|
// TBL1_16b, TBL1_8b
|
|
printVectorList(MI, 1, O, A64Layout_VL_16B, 1, MRI);
|
|
SStream_concat(O, ", ");
|
|
printVPRRegister(MI, 2, O);
|
|
break;
|
|
case 23:
|
|
// TBL2_16b, TBL2_8b
|
|
printVectorList(MI, 1, O, A64Layout_VL_16B, 2, MRI);
|
|
SStream_concat(O, ", ");
|
|
printVPRRegister(MI, 2, O);
|
|
break;
|
|
case 24:
|
|
// TBL3_16b, TBL3_8b
|
|
printVectorList(MI, 1, O, A64Layout_VL_16B, 3, MRI);
|
|
SStream_concat(O, ", ");
|
|
printVPRRegister(MI, 2, O);
|
|
break;
|
|
case 25:
|
|
// TBL4_16b, TBL4_8b
|
|
printVectorList(MI, 1, O, A64Layout_VL_16B, 4, MRI);
|
|
SStream_concat(O, ", ");
|
|
printVPRRegister(MI, 2, O);
|
|
break;
|
|
case 26:
|
|
// TBX1_16b, TBX1_8b
|
|
printVectorList(MI, 2, O, A64Layout_VL_16B, 1, MRI);
|
|
SStream_concat(O, ", ");
|
|
printVPRRegister(MI, 3, O);
|
|
break;
|
|
case 27:
|
|
// TBX2_16b, TBX2_8b
|
|
printVectorList(MI, 2, O, A64Layout_VL_16B, 2, MRI);
|
|
SStream_concat(O, ", ");
|
|
printVPRRegister(MI, 3, O);
|
|
break;
|
|
case 28:
|
|
// TBX3_16b, TBX3_8b
|
|
printVectorList(MI, 2, O, A64Layout_VL_16B, 3, MRI);
|
|
SStream_concat(O, ", ");
|
|
printVPRRegister(MI, 3, O);
|
|
break;
|
|
case 29:
|
|
// TBX4_16b, TBX4_8b
|
|
printVectorList(MI, 2, O, A64Layout_VL_16B, 4, MRI);
|
|
SStream_concat(O, ", ");
|
|
printVPRRegister(MI, 3, O);
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 3 encoded into 5 bits for 30 unique commands.
|
|
//printf("Frag-3: %"PRIu64"\n", (Bits >> 30) & 31);
|
|
switch ((Bits >> 30) & 31) {
|
|
default: // unreachable.
|
|
case 0:
|
|
// ABS16b, ADDV_1b16b, AESD, AESE, AESIMC, AESMC, CLS16b, CLZ16b, CNT16b,...
|
|
SStream_concat(O, ".16b");
|
|
return;
|
|
break;
|
|
case 1:
|
|
// ABS2d, ADDPvv_D_2D, FABS2d, FADDPvv_D_2D, FCVTAS_2d, FCVTAU_2d, FCVTMS...
|
|
SStream_concat(O, ".2d");
|
|
return;
|
|
break;
|
|
case 2:
|
|
// ABS2s, CLS2s, CLZ2s, FABS2s, FADDPvv_S_2S, FCVTAS_2s, FCVTAU_2s, FCVTL...
|
|
SStream_concat(O, ".2s");
|
|
return;
|
|
break;
|
|
case 3:
|
|
// ABS4h, ADDV_1h4h, CLS4h, CLZ4h, FCVTL4h4s, NEG4h, REV32_4h, REV64_4h, ...
|
|
SStream_concat(O, ".4h");
|
|
return;
|
|
break;
|
|
case 4:
|
|
// ABS4s, ADDV_1s4s, CLS4s, CLZ4s, FABS4s, FCVTAS_4s, FCVTAU_4s, FCVTL4s2...
|
|
SStream_concat(O, ".4s");
|
|
return;
|
|
break;
|
|
case 5:
|
|
// ABS8b, ADDV_1b8b, CLS8b, CLZ8b, CNT8b, NEG8b, NOT8b, RBIT8b, REV16_8b,...
|
|
SStream_concat(O, ".8b");
|
|
return;
|
|
break;
|
|
case 6:
|
|
// ABS8h, ADDV_1h8h, CLS8h, CLZ8h, FCVTL8h4s, NEG8h, REV32_8h, REV64_8h, ...
|
|
SStream_concat(O, ".8h");
|
|
return;
|
|
break;
|
|
case 7:
|
|
// ABSdd, CLSww, CLSxx, CLZww, CLZxx, DUP16b, DUP2d, DUP2s, DUP4h, DUP4s,...
|
|
return;
|
|
break;
|
|
case 8:
|
|
// ADCSwww, ADCSxxx, ADCwww, ADCxxx, ADDSwww_asr, ADDSwww_lsl, ADDSwww_ls...
|
|
SStream_concat(O, ", ");
|
|
break;
|
|
case 9:
|
|
// ADDHN2vvv_16b8h, ADDHNvvv_8b8h, ADDP_8H, ADDvvv_8H, CMEQvvi_8H, CMEQvv...
|
|
SStream_concat(O, ".8h, ");
|
|
break;
|
|
case 10:
|
|
// ADDHN2vvv_4s2d, ADDHNvvv_2s2d, ADDP_2D, ADDvvv_2D, CMEQvvi_2D, CMEQvvv...
|
|
SStream_concat(O, ".2d, ");
|
|
break;
|
|
case 11:
|
|
// ADDHN2vvv_8h4s, ADDHNvvv_4h4s, ADDP_4S, ADDvvv_4S, CMEQvvi_4S, CMEQvvv...
|
|
SStream_concat(O, ".4s, ");
|
|
break;
|
|
case 12:
|
|
// ADDP_16B, ADDvvv_16B, ANDvvv_16B, BICvvv_16B, BIFvvv_16B, BITvvv_16B, ...
|
|
SStream_concat(O, ".16b, ");
|
|
break;
|
|
case 13:
|
|
// ADDP_2S, ADDvvv_2S, CMEQvvi_2S, CMEQvvv_2S, CMGEvvi_2S, CMGEvvv_2S, CM...
|
|
SStream_concat(O, ".2s, ");
|
|
break;
|
|
case 14:
|
|
// ADDP_4H, ADDvvv_4H, CMEQvvi_4H, CMEQvvv_4H, CMGEvvi_4H, CMGEvvv_4H, CM...
|
|
SStream_concat(O, ".4h, ");
|
|
break;
|
|
case 15:
|
|
// ADDP_8B, ADDvvv_8B, ANDvvv_8B, BICvvv_8B, BIFvvv_8B, BITvvv_8B, BSLvvv...
|
|
SStream_concat(O, ".8b, ");
|
|
break;
|
|
case 16:
|
|
// BICvi_lsl_2S, BICvi_lsl_4S, ORRvi_lsl_2S, ORRvi_lsl_4S
|
|
printNeonMovImmShiftOperand(MI, 3, O, A64SE_LSL, false);
|
|
return;
|
|
break;
|
|
case 17:
|
|
// BICvi_lsl_4H, BICvi_lsl_8H, ORRvi_lsl_4H, ORRvi_lsl_8H
|
|
printNeonMovImmShiftOperand(MI, 3, O, A64SE_LSL, true);
|
|
return;
|
|
break;
|
|
case 18:
|
|
// DUPELT16b, DUPELT8b, DUPbv_B, INSELb, SMOVwb, SMOVxb, UMOVwb
|
|
SStream_concat(O, ".b[");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 19:
|
|
// DUPELT2d, DUPdv_D, FMOVxv, UMOVxd
|
|
SStream_concat(O, ".d[");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 20:
|
|
// DUPELT2s, DUPELT4s, DUPsv_S, INSELs, SMOVxs, UMOVws
|
|
SStream_concat(O, ".s[");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 21:
|
|
// DUPELT4h, DUPELT8h, DUPhv_H, INSELh, SMOVwh, SMOVxh, UMOVwh
|
|
SStream_concat(O, ".h[");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 22:
|
|
// INSELd
|
|
printVPRRegister(MI, 2, O);
|
|
SStream_concat(O, ".d[");
|
|
set_mem_access(MI, true);
|
|
printUImmBareOperand(MI, 4, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 23:
|
|
// INSdx
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 24:
|
|
// LDAR_byte, LDAR_dword, LDAR_hword, LDAR_word, LDAXR_byte, LDAXR_dword,...
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 25:
|
|
// LDAXP_dword, LDAXP_word, LDPSWx, LDPSWx_PostInd, LDPSWx_PreInd, LDXP_d...
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 26:
|
|
// LDRSBw_PostInd, LDRSBx_PostInd, LDRSHw_PostInd, LDRSHx_PostInd, LDRSWx...
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
printOffsetSImm9Operand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 27:
|
|
// MOVIvi_lsl_2S, MOVIvi_lsl_4S, MVNIvi_lsl_2S, MVNIvi_lsl_4S
|
|
printNeonMovImmShiftOperand(MI, 2, O, A64SE_LSL, false);
|
|
return;
|
|
break;
|
|
case 28:
|
|
// MOVIvi_lsl_4H, MOVIvi_lsl_8H, MVNIvi_lsl_4H, MVNIvi_lsl_8H
|
|
printNeonMovImmShiftOperand(MI, 2, O, A64SE_LSL, true);
|
|
return;
|
|
break;
|
|
case 29:
|
|
// MOVIvi_msl_2S, MOVIvi_msl_4S, MVNIvi_msl_2S, MVNIvi_msl_4S
|
|
printNeonMovImmShiftOperand(MI, 2, O, A64SE_MSL, false);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 4 encoded into 6 bits for 39 unique commands.
|
|
//printf("Frag-4: %"PRIu64"\n", (Bits >> 35) & 63);
|
|
switch ((Bits >> 35) & 63) {
|
|
default: // unreachable.
|
|
case 0:
|
|
// ADCSwww, ADCSxxx, ADCwww, ADCxxx, ADDSwww_asr, ADDSwww_lsl, ADDSwww_ls...
|
|
printOperand(MI, 2, O);
|
|
break;
|
|
case 1:
|
|
// ADDHN2vvv_16b8h, ADDHN2vvv_4s2d, ADDHN2vvv_8h4s, BIFvvv_16B, BIFvvv_8B...
|
|
printVPRRegister(MI, 3, O);
|
|
break;
|
|
case 2:
|
|
// ADDHNvvv_2s2d, ADDHNvvv_4h4s, ADDHNvvv_8b8h, ADDP_16B, ADDP_2D, ADDP_2...
|
|
printVPRRegister(MI, 2, O);
|
|
break;
|
|
case 3:
|
|
// ADDwwi_lsl0_S, ADDwwi_lsl0_s, ADDxxi_lsl0_S, ADDxxi_lsl0_s, SUBwwi_lsl...
|
|
printAddSubImmLSL0Operand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 4:
|
|
// ADDwwi_lsl12_S, ADDwwi_lsl12_s, ADDxxi_lsl12_S, ADDxxi_lsl12_s, SUBwwi...
|
|
printAddSubImmLSL12Operand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 5:
|
|
// ANDSwwi, ANDwwi, EORwwi, ORRwwi
|
|
printLogicalImmOperand(MI, 2, O, 32);
|
|
return;
|
|
break;
|
|
case 6:
|
|
// ANDSxxi, ANDxxi, EORxxi, ORRxxi
|
|
printLogicalImmOperand(MI, 2, O, 64);
|
|
return;
|
|
break;
|
|
case 7:
|
|
// BFIwwii
|
|
printBFILSBOperand(MI, 3, O, 32);
|
|
SStream_concat(O, ", ");
|
|
printBFIWidthOperand(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 8:
|
|
// BFIxxii
|
|
printBFILSBOperand(MI, 3, O, 64);
|
|
SStream_concat(O, ", ");
|
|
printBFIWidthOperand(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 9:
|
|
// BFMwwii, BFMxxii, BFXILwwii, BFXILxxii, LDPSWx_PostInd, LDPSWx_PreInd,...
|
|
printOperand(MI, 3, O);
|
|
break;
|
|
case 10:
|
|
// CMEQddi, CMEQvvi_16B, CMEQvvi_2D, CMEQvvi_2S, CMEQvvi_4H, CMEQvvi_4S, ...
|
|
printNeonUImm0Operand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 11:
|
|
// CMNww_asr, CMNxx_asr, CMPww_asr, CMPxx_asr, MVNww_asr, MVNxx_asr, TSTw...
|
|
printShiftOperand(MI, 2, O, A64SE_ASR);
|
|
return;
|
|
break;
|
|
case 12:
|
|
// CMNww_lsl, CMNxx_lsl, CMPww_lsl, CMPxx_lsl, MVNww_lsl, MVNxx_lsl, TSTw...
|
|
printShiftOperand(MI, 2, O, A64SE_LSL);
|
|
return;
|
|
break;
|
|
case 13:
|
|
// CMNww_lsr, CMNxx_lsr, CMPww_lsr, CMPxx_lsr, MVNww_lsr, MVNxx_lsr, TSTw...
|
|
printShiftOperand(MI, 2, O, A64SE_LSR);
|
|
return;
|
|
break;
|
|
case 14:
|
|
// CMNww_sxtb, CMNxw_sxtb, CMPww_sxtb, CMPxw_sxtb
|
|
printRegExtendOperand(MI, 2, O, A64SE_SXTB);
|
|
return;
|
|
break;
|
|
case 15:
|
|
// CMNww_sxth, CMNxw_sxth, CMPww_sxth, CMPxw_sxth
|
|
printRegExtendOperand(MI, 2, O, A64SE_SXTH);
|
|
return;
|
|
break;
|
|
case 16:
|
|
// CMNww_sxtw, CMNxw_sxtw, CMPww_sxtw, CMPxw_sxtw
|
|
printRegExtendOperand(MI, 2, O, A64SE_SXTW);
|
|
return;
|
|
break;
|
|
case 17:
|
|
// CMNww_sxtx, CMNxx_sxtx, CMPww_sxtx, CMPxx_sxtx
|
|
printRegExtendOperand(MI, 2, O, A64SE_SXTX);
|
|
return;
|
|
break;
|
|
case 18:
|
|
// CMNww_uxtb, CMNxw_uxtb, CMPww_uxtb, CMPxw_uxtb
|
|
printRegExtendOperand(MI, 2, O, A64SE_UXTB);
|
|
return;
|
|
break;
|
|
case 19:
|
|
// CMNww_uxth, CMNxw_uxth, CMPww_uxth, CMPxw_uxth
|
|
printRegExtendOperand(MI, 2, O, A64SE_UXTH);
|
|
return;
|
|
break;
|
|
case 20:
|
|
// CMNww_uxtw, CMNxw_uxtw, CMPww_uxtw, CMPxw_uxtw
|
|
printRegExtendOperand(MI, 2, O, A64SE_UXTW);
|
|
return;
|
|
break;
|
|
case 21:
|
|
// CMNww_uxtx, CMNxx_uxtx, CMPww_uxtx, CMPxx_uxtx
|
|
printRegExtendOperand(MI, 2, O, A64SE_UXTX);
|
|
return;
|
|
break;
|
|
case 22:
|
|
// DUPELT16b, DUPELT2d, DUPELT2s, DUPELT4h, DUPELT4s, DUPELT8b, DUPELT8h,...
|
|
printUImmBareOperand(MI, 2, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 23:
|
|
// FCMEQZddi, FCMEQZssi, FCMEQvvi_2D, FCMEQvvi_2S, FCMEQvvi_4S, FCMGEZddi...
|
|
printFPZeroOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 24:
|
|
// FCVTZSwdi, FCVTZSwsi, FCVTZSxdi, FCVTZSxsi, FCVTZUwdi, FCVTZUwsi, FCVT...
|
|
printCVTFixedPosOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 25:
|
|
// FMOVxv
|
|
printBareImmOperand(MI, 2, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 26:
|
|
// INSELb, INSELh, INSELs
|
|
printUImmBareOperand(MI, 4, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 27:
|
|
// LDRSBw, LDRSBx, LS8_LDR, LS8_STR, LSFP8_LDR, LSFP8_STR
|
|
printOffsetUImm12Operand(MI, 2, O, 1);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 28:
|
|
// LDRSBw_PreInd, LDRSBx_PreInd, LDRSHw_PreInd, LDRSHx_PreInd, LDRSWx_Pre...
|
|
printOffsetSImm9Operand(MI, 3, O);
|
|
SStream_concat(O, "]!");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 29:
|
|
// LDRSBw_U, LDRSBx_U, LDRSHw_U, LDRSHx_U, LDTRSBw, LDTRSBx, LDTRSHw, LDT...
|
|
printOffsetSImm9Operand(MI, 2, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 30:
|
|
// LDRSHw, LDRSHx, LS16_LDR, LS16_STR, LSFP16_LDR, LSFP16_STR
|
|
printOffsetUImm12Operand(MI, 2, O, 2);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 31:
|
|
// LDRSWx, LS32_LDR, LS32_STR, LSFP32_LDR, LSFP32_STR
|
|
printOffsetUImm12Operand(MI, 2, O, 4);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 32:
|
|
// LS64_LDR, LS64_STR, LSFP64_LDR, LSFP64_STR, PRFM
|
|
printOffsetUImm12Operand(MI, 2, O, 8);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 33:
|
|
// LSFP128_LDR, LSFP128_STR
|
|
printOffsetUImm12Operand(MI, 2, O, 16);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 34:
|
|
// MVNww_ror, MVNxx_ror, TSTww_ror, TSTxx_ror
|
|
printShiftOperand(MI, 2, O, A64SE_ROR);
|
|
return;
|
|
break;
|
|
case 35:
|
|
// SBFIZwwii, UBFIZwwii
|
|
printBFILSBOperand(MI, 2, O, 32);
|
|
SStream_concat(O, ", ");
|
|
printBFIWidthOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 36:
|
|
// SBFIZxxii, UBFIZxxii
|
|
printBFILSBOperand(MI, 2, O, 64);
|
|
SStream_concat(O, ", ");
|
|
printBFIWidthOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 37:
|
|
// SYSLxicci
|
|
printCRxOperand(MI, 2, O);
|
|
SStream_concat(O, ", ");
|
|
printCRxOperand(MI, 3, O);
|
|
SStream_concat(O, ", ");
|
|
printOperand(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 38:
|
|
// TBNZwii, TBNZxii, TBZwii, TBZxii
|
|
printLabelOperand(MI, 2, O, 14, 4);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 5 encoded into 5 bits for 17 unique commands.
|
|
//printf("Frag-5: %"PRIu64"\n", (Bits >> 41) & 31);
|
|
switch ((Bits >> 41) & 31) {
|
|
default: // unreachable.
|
|
case 0:
|
|
// ADCSwww, ADCSxxx, ADCwww, ADCxxx, ADDddd, ASRVwww, ASRVxxx, ASRwwi, AS...
|
|
return;
|
|
break;
|
|
case 1:
|
|
// ADDHN2vvv_16b8h, ADDHNvvv_8b8h, ADDP_8H, ADDvvv_8H, CMEQvvv_8H, CMGEvv...
|
|
SStream_concat(O, ".8h");
|
|
return;
|
|
break;
|
|
case 2:
|
|
// ADDHN2vvv_4s2d, ADDHNvvv_2s2d, ADDP_2D, ADDvvv_2D, CMEQvvv_2D, CMGEvvv...
|
|
SStream_concat(O, ".2d");
|
|
return;
|
|
break;
|
|
case 3:
|
|
// ADDHN2vvv_8h4s, ADDHNvvv_4h4s, ADDP_4S, ADDvvv_4S, CMEQvvv_4S, CMGEvvv...
|
|
SStream_concat(O, ".4s");
|
|
return;
|
|
break;
|
|
case 4:
|
|
// ADDP_16B, ADDvvv_16B, ANDvvv_16B, BICvvv_16B, BIFvvv_16B, BITvvv_16B, ...
|
|
SStream_concat(O, ".16b");
|
|
return;
|
|
break;
|
|
case 5:
|
|
// ADDP_2S, ADDvvv_2S, CMEQvvv_2S, CMGEvvv_2S, CMGTvvv_2S, CMHIvvv_2S, CM...
|
|
SStream_concat(O, ".2s");
|
|
return;
|
|
break;
|
|
case 6:
|
|
// ADDP_4H, ADDvvv_4H, CMEQvvv_4H, CMGEvvv_4H, CMGTvvv_4H, CMHIvvv_4H, CM...
|
|
SStream_concat(O, ".4h");
|
|
return;
|
|
break;
|
|
case 7:
|
|
// ADDP_8B, ADDvvv_8B, ANDvvv_8B, BICvvv_8B, BIFvvv_8B, BITvvv_8B, BSLvvv...
|
|
SStream_concat(O, ".8b");
|
|
return;
|
|
break;
|
|
case 8:
|
|
// ADDSwww_asr, ADDSwww_lsl, ADDSwww_lsr, ADDSwww_sxtb, ADDSwww_sxth, ADD...
|
|
SStream_concat(O, ", ");
|
|
break;
|
|
case 9:
|
|
// EXTvvvi_16b
|
|
SStream_concat(O, ".16b, ");
|
|
printUImmHexOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 10:
|
|
// EXTvvvi_8b
|
|
SStream_concat(O, ".8b, ");
|
|
printUImmHexOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 11:
|
|
// FMLAddv_2D, FMLAvve_2d2d, FMLSddv_2D, FMLSvve_2d2d, FMULXddv_2D, FMULX...
|
|
SStream_concat(O, ".d[");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 12:
|
|
// FMLAssv_4S, FMLAvve_2s4s, FMLAvve_4s4s, FMLSssv_4S, FMLSvve_2s4s, FMLS...
|
|
SStream_concat(O, ".s[");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 13:
|
|
// LDAXP_dword, LDAXP_word, LDXP_dword, LDXP_word, STLXR_byte, STLXR_dwor...
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 14:
|
|
// LDPSWx_PostInd, LSFPPair128_PostInd_LDR, LSFPPair128_PostInd_STR, LSFP...
|
|
SStream_concat(O, "], ");
|
|
set_mem_access(MI, false);
|
|
break;
|
|
case 15:
|
|
// MLAvve_4h8h, MLAvve_8h8h, MLSvve_4h8h, MLSvve_8h8h, MULve_4h8h, MULve_...
|
|
SStream_concat(O, ".h[");
|
|
set_mem_access(MI, true);
|
|
break;
|
|
case 16:
|
|
// STLXP_dword, STLXP_word, STXP_dword, STXP_word
|
|
SStream_concat(O, ", [");
|
|
set_mem_access(MI, true);
|
|
printOperand(MI, 3, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 6 encoded into 6 bits for 35 unique commands.
|
|
//printf("Frag-6: %"PRIu64"\n", (Bits >> 46) & 63);
|
|
switch ((Bits >> 46) & 63) {
|
|
default: // unreachable.
|
|
case 0:
|
|
// ADDSwww_asr, ADDSxxx_asr, ADDwww_asr, ADDxxx_asr, ANDSwww_asr, ANDSxxx...
|
|
printShiftOperand(MI, 3, O, A64SE_ASR);
|
|
return;
|
|
break;
|
|
case 1:
|
|
// ADDSwww_lsl, ADDSxxx_lsl, ADDwww_lsl, ADDxxx_lsl, ANDSwww_lsl, ANDSxxx...
|
|
printShiftOperand(MI, 3, O, A64SE_LSL);
|
|
return;
|
|
break;
|
|
case 2:
|
|
// ADDSwww_lsr, ADDSxxx_lsr, ADDwww_lsr, ADDxxx_lsr, ANDSwww_lsr, ANDSxxx...
|
|
printShiftOperand(MI, 3, O, A64SE_LSR);
|
|
return;
|
|
break;
|
|
case 3:
|
|
// ADDSwww_sxtb, ADDSxxw_sxtb, ADDwww_sxtb, ADDxxw_sxtb, SUBSwww_sxtb, SU...
|
|
printRegExtendOperand(MI, 3, O, A64SE_SXTB);
|
|
return;
|
|
break;
|
|
case 4:
|
|
// ADDSwww_sxth, ADDSxxw_sxth, ADDwww_sxth, ADDxxw_sxth, SUBSwww_sxth, SU...
|
|
printRegExtendOperand(MI, 3, O, A64SE_SXTH);
|
|
return;
|
|
break;
|
|
case 5:
|
|
// ADDSwww_sxtw, ADDSxxw_sxtw, ADDwww_sxtw, ADDxxw_sxtw, SUBSwww_sxtw, SU...
|
|
printRegExtendOperand(MI, 3, O, A64SE_SXTW);
|
|
return;
|
|
break;
|
|
case 6:
|
|
// ADDSwww_sxtx, ADDSxxx_sxtx, ADDwww_sxtx, ADDxxx_sxtx, SUBSwww_sxtx, SU...
|
|
printRegExtendOperand(MI, 3, O, A64SE_SXTX);
|
|
return;
|
|
break;
|
|
case 7:
|
|
// ADDSwww_uxtb, ADDSxxw_uxtb, ADDwww_uxtb, ADDxxw_uxtb, SUBSwww_uxtb, SU...
|
|
printRegExtendOperand(MI, 3, O, A64SE_UXTB);
|
|
return;
|
|
break;
|
|
case 8:
|
|
// ADDSwww_uxth, ADDSxxw_uxth, ADDwww_uxth, ADDxxw_uxth, SUBSwww_uxth, SU...
|
|
printRegExtendOperand(MI, 3, O, A64SE_UXTH);
|
|
return;
|
|
break;
|
|
case 9:
|
|
// ADDSwww_uxtw, ADDSxxw_uxtw, ADDwww_uxtw, ADDxxw_uxtw, SUBSwww_uxtw, SU...
|
|
printRegExtendOperand(MI, 3, O, A64SE_UXTW);
|
|
return;
|
|
break;
|
|
case 10:
|
|
// ADDSwww_uxtx, ADDSxxx_uxtx, ADDwww_uxtx, ADDxxx_uxtx, SUBSwww_uxtx, SU...
|
|
printRegExtendOperand(MI, 3, O, A64SE_UXTX);
|
|
return;
|
|
break;
|
|
case 11:
|
|
// ANDSwww_ror, ANDSxxx_ror, ANDwww_ror, ANDxxx_ror, BICSwww_ror, BICSxxx...
|
|
printShiftOperand(MI, 3, O, A64SE_ROR);
|
|
return;
|
|
break;
|
|
case 12:
|
|
// BFMwwii, BFMxxii
|
|
printOperand(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 13:
|
|
// BFXILwwii, BFXILxxii
|
|
printBFXWidthOperand(MI, 4, O);
|
|
return;
|
|
break;
|
|
case 14:
|
|
// CCMNwi, CCMNww, CCMNxi, CCMNxx, CCMPwi, CCMPww, CCMPxi, CCMPxx, CSELww...
|
|
printCondCodeOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 15:
|
|
// EXTRwwwi, EXTRxxxi, FMADDdddd, FMADDssss, FMSUBdddd, FMSUBssss, FNMADD...
|
|
printOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
case 16:
|
|
// FMLAddv_2D, FMLAssv_4S, FMLAvve_2d2d, FMLAvve_2s4s, FMLAvve_4s4s, FMLS...
|
|
printUImmBareOperand(MI, 4, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 17:
|
|
// FMULXddv_2D, FMULXssv_4S, FMULXve_2d2d, FMULXve_2s4s, FMULXve_4s4s, FM...
|
|
printUImmBareOperand(MI, 3, O);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 18:
|
|
// LDPSWx, LSFPPair32_LDR, LSFPPair32_NonTemp_LDR, LSFPPair32_NonTemp_STR...
|
|
printSImm7ScaledOperand(MI, 3, O, 4);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 19:
|
|
// LDPSWx_PostInd, LDPSWx_PreInd, LSFPPair32_PostInd_LDR, LSFPPair32_Post...
|
|
printSImm7ScaledOperand(MI, 4, O, 4);
|
|
break;
|
|
case 20:
|
|
// LDRSBw_Wm_RegOffset, LDRSBx_Wm_RegOffset, LS8_Wm_RegOffset_LDR, LS8_Wm...
|
|
printAddrRegExtendOperand(MI, 3, O, 1, 32);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 21:
|
|
// LDRSBw_Xm_RegOffset, LDRSBx_Xm_RegOffset, LS8_Xm_RegOffset_LDR, LS8_Xm...
|
|
printAddrRegExtendOperand(MI, 3, O, 1, 64);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 22:
|
|
// LDRSHw_Wm_RegOffset, LDRSHx_Wm_RegOffset, LS16_Wm_RegOffset_LDR, LS16_...
|
|
printAddrRegExtendOperand(MI, 3, O, 2, 32);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 23:
|
|
// LDRSHw_Xm_RegOffset, LDRSHx_Xm_RegOffset, LS16_Xm_RegOffset_LDR, LS16_...
|
|
printAddrRegExtendOperand(MI, 3, O, 2, 64);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 24:
|
|
// LDRSWx_Wm_RegOffset, LS32_Wm_RegOffset_LDR, LS32_Wm_RegOffset_STR, LSF...
|
|
printAddrRegExtendOperand(MI, 3, O, 4, 32);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 25:
|
|
// LDRSWx_Xm_RegOffset, LS32_Xm_RegOffset_LDR, LS32_Xm_RegOffset_STR, LSF...
|
|
printAddrRegExtendOperand(MI, 3, O, 4, 64);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 26:
|
|
// LS64_Wm_RegOffset_LDR, LS64_Wm_RegOffset_STR, LSFP64_Wm_RegOffset_LDR,...
|
|
printAddrRegExtendOperand(MI, 3, O, 8, 32);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 27:
|
|
// LS64_Xm_RegOffset_LDR, LS64_Xm_RegOffset_STR, LSFP64_Xm_RegOffset_LDR,...
|
|
printAddrRegExtendOperand(MI, 3, O, 8, 64);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 28:
|
|
// LSFP128_Wm_RegOffset_LDR, LSFP128_Wm_RegOffset_STR
|
|
printAddrRegExtendOperand(MI, 3, O, 16, 32);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 29:
|
|
// LSFP128_Xm_RegOffset_LDR, LSFP128_Xm_RegOffset_STR
|
|
printAddrRegExtendOperand(MI, 3, O, 16, 64);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 30:
|
|
// LSFPPair128_LDR, LSFPPair128_NonTemp_LDR, LSFPPair128_NonTemp_STR, LSF...
|
|
printSImm7ScaledOperand(MI, 3, O, 16);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 31:
|
|
// LSFPPair128_PostInd_LDR, LSFPPair128_PostInd_STR, LSFPPair128_PreInd_L...
|
|
printSImm7ScaledOperand(MI, 4, O, 16);
|
|
break;
|
|
case 32:
|
|
// LSFPPair64_LDR, LSFPPair64_NonTemp_LDR, LSFPPair64_NonTemp_STR, LSFPPa...
|
|
printSImm7ScaledOperand(MI, 3, O, 8);
|
|
SStream_concat(O, "]");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
break;
|
|
case 33:
|
|
// LSFPPair64_PostInd_LDR, LSFPPair64_PostInd_STR, LSFPPair64_PreInd_LDR,...
|
|
printSImm7ScaledOperand(MI, 4, O, 8);
|
|
break;
|
|
case 34:
|
|
// SBFXwwii, SBFXxxii, UBFXwwii, UBFXxxii
|
|
printBFXWidthOperand(MI, 3, O);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 7 encoded into 1 bits for 2 unique commands.
|
|
//printf("Frag-7: %"PRIu64"\n", (Bits >> 52) & 1);
|
|
if ((Bits >> 52) & 1) {
|
|
// LDPSWx_PreInd, LSFPPair128_PreInd_LDR, LSFPPair128_PreInd_STR, LSFPPai...
|
|
SStream_concat(O, "]!");
|
|
set_mem_access(MI, false);
|
|
return;
|
|
} else {
|
|
// LDPSWx_PostInd, LSFPPair128_PostInd_LDR, LSFPPair128_PostInd_STR, LSFP...
|
|
return;
|
|
}
|
|
|
|
}
|
|
|
|
|
|
/// getRegisterName - This method is automatically generated by tblgen
|
|
/// from the register set description. This returns the assembler name
|
|
/// for the specified register.
|
|
static char *getRegisterName(unsigned RegNo)
|
|
{
|
|
// assert(RegNo && RegNo < 420 && "Invalid register number!");
|
|
|
|
#ifndef CAPSTONE_DIET
|
|
static char AsmStrs[] = {
|
|
/* 0 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
|
|
/* 13 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
|
|
/* 26 */ 'b', '1', '0', 0,
|
|
/* 30 */ 'd', '1', '0', 0,
|
|
/* 34 */ 'h', '1', '0', 0,
|
|
/* 38 */ 'q', '1', '0', 0,
|
|
/* 42 */ 's', '1', '0', 0,
|
|
/* 46 */ 'w', '1', '0', 0,
|
|
/* 50 */ 'x', '1', '0', 0,
|
|
/* 54 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0,
|
|
/* 70 */ 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', 0,
|
|
/* 86 */ 'b', '2', '0', 0,
|
|
/* 90 */ 'd', '2', '0', 0,
|
|
/* 94 */ 'h', '2', '0', 0,
|
|
/* 98 */ 'q', '2', '0', 0,
|
|
/* 102 */ 's', '2', '0', 0,
|
|
/* 106 */ 'w', '2', '0', 0,
|
|
/* 110 */ 'x', '2', '0', 0,
|
|
/* 114 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0,
|
|
/* 130 */ 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', 0,
|
|
/* 146 */ 'b', '3', '0', 0,
|
|
/* 150 */ 'd', '3', '0', 0,
|
|
/* 154 */ 'h', '3', '0', 0,
|
|
/* 158 */ 'q', '3', '0', 0,
|
|
/* 162 */ 's', '3', '0', 0,
|
|
/* 166 */ 'w', '3', '0', 0,
|
|
/* 170 */ 'x', '3', '0', 0,
|
|
/* 174 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', 0,
|
|
/* 189 */ 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', 0,
|
|
/* 204 */ 'b', '0', 0,
|
|
/* 207 */ 'd', '0', 0,
|
|
/* 210 */ 'h', '0', 0,
|
|
/* 213 */ 'q', '0', 0,
|
|
/* 216 */ 's', '0', 0,
|
|
/* 219 */ 'w', '0', 0,
|
|
/* 222 */ 'x', '0', 0,
|
|
/* 225 */ 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0,
|
|
/* 239 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0,
|
|
/* 253 */ 'b', '1', '1', 0,
|
|
/* 257 */ 'd', '1', '1', 0,
|
|
/* 261 */ 'h', '1', '1', 0,
|
|
/* 265 */ 'q', '1', '1', 0,
|
|
/* 269 */ 's', '1', '1', 0,
|
|
/* 273 */ 'w', '1', '1', 0,
|
|
/* 277 */ 'x', '1', '1', 0,
|
|
/* 281 */ 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0,
|
|
/* 297 */ 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', 0,
|
|
/* 313 */ 'b', '2', '1', 0,
|
|
/* 317 */ 'd', '2', '1', 0,
|
|
/* 321 */ 'h', '2', '1', 0,
|
|
/* 325 */ 'q', '2', '1', 0,
|
|
/* 329 */ 's', '2', '1', 0,
|
|
/* 333 */ 'w', '2', '1', 0,
|
|
/* 337 */ 'x', '2', '1', 0,
|
|
/* 341 */ 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0,
|
|
/* 357 */ 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', 0,
|
|
/* 373 */ 'b', '3', '1', 0,
|
|
/* 377 */ 'd', '3', '1', 0,
|
|
/* 381 */ 'h', '3', '1', 0,
|
|
/* 385 */ 'q', '3', '1', 0,
|
|
/* 389 */ 's', '3', '1', 0,
|
|
/* 393 */ 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', 0,
|
|
/* 407 */ 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', 0,
|
|
/* 421 */ 'b', '1', 0,
|
|
/* 424 */ 'd', '1', 0,
|
|
/* 427 */ 'h', '1', 0,
|
|
/* 430 */ 'q', '1', 0,
|
|
/* 433 */ 's', '1', 0,
|
|
/* 436 */ 'w', '1', 0,
|
|
/* 439 */ 'x', '1', 0,
|
|
/* 442 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0,
|
|
/* 457 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0,
|
|
/* 472 */ 'b', '1', '2', 0,
|
|
/* 476 */ 'd', '1', '2', 0,
|
|
/* 480 */ 'h', '1', '2', 0,
|
|
/* 484 */ 'q', '1', '2', 0,
|
|
/* 488 */ 's', '1', '2', 0,
|
|
/* 492 */ 'w', '1', '2', 0,
|
|
/* 496 */ 'x', '1', '2', 0,
|
|
/* 500 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0,
|
|
/* 516 */ 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', 0,
|
|
/* 532 */ 'b', '2', '2', 0,
|
|
/* 536 */ 'd', '2', '2', 0,
|
|
/* 540 */ 'h', '2', '2', 0,
|
|
/* 544 */ 'q', '2', '2', 0,
|
|
/* 548 */ 's', '2', '2', 0,
|
|
/* 552 */ 'w', '2', '2', 0,
|
|
/* 556 */ 'x', '2', '2', 0,
|
|
/* 560 */ 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', '_', 'D', '2', 0,
|
|
/* 573 */ 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', 0,
|
|
/* 586 */ 'b', '2', 0,
|
|
/* 589 */ 'd', '2', 0,
|
|
/* 592 */ 'h', '2', 0,
|
|
/* 595 */ 'q', '2', 0,
|
|
/* 598 */ 's', '2', 0,
|
|
/* 601 */ 'w', '2', 0,
|
|
/* 604 */ 'x', '2', 0,
|
|
/* 607 */ 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0,
|
|
/* 623 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0,
|
|
/* 639 */ 'b', '1', '3', 0,
|
|
/* 643 */ 'd', '1', '3', 0,
|
|
/* 647 */ 'h', '1', '3', 0,
|
|
/* 651 */ 'q', '1', '3', 0,
|
|
/* 655 */ 's', '1', '3', 0,
|
|
/* 659 */ 'w', '1', '3', 0,
|
|
/* 663 */ 'x', '1', '3', 0,
|
|
/* 667 */ 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0,
|
|
/* 683 */ 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', 0,
|
|
/* 699 */ 'b', '2', '3', 0,
|
|
/* 703 */ 'd', '2', '3', 0,
|
|
/* 707 */ 'h', '2', '3', 0,
|
|
/* 711 */ 'q', '2', '3', 0,
|
|
/* 715 */ 's', '2', '3', 0,
|
|
/* 719 */ 'w', '2', '3', 0,
|
|
/* 723 */ 'x', '2', '3', 0,
|
|
/* 727 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', '_', 'D', '3', 0,
|
|
/* 739 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0,
|
|
/* 751 */ 'b', '3', 0,
|
|
/* 754 */ 'd', '3', 0,
|
|
/* 757 */ 'h', '3', 0,
|
|
/* 760 */ 'q', '3', 0,
|
|
/* 763 */ 's', '3', 0,
|
|
/* 766 */ 'w', '3', 0,
|
|
/* 769 */ 'x', '3', 0,
|
|
/* 772 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0,
|
|
/* 788 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0,
|
|
/* 804 */ 'b', '1', '4', 0,
|
|
/* 808 */ 'd', '1', '4', 0,
|
|
/* 812 */ 'h', '1', '4', 0,
|
|
/* 816 */ 'q', '1', '4', 0,
|
|
/* 820 */ 's', '1', '4', 0,
|
|
/* 824 */ 'w', '1', '4', 0,
|
|
/* 828 */ 'x', '1', '4', 0,
|
|
/* 832 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0,
|
|
/* 848 */ 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', 0,
|
|
/* 864 */ 'b', '2', '4', 0,
|
|
/* 868 */ 'd', '2', '4', 0,
|
|
/* 872 */ 'h', '2', '4', 0,
|
|
/* 876 */ 'q', '2', '4', 0,
|
|
/* 880 */ 's', '2', '4', 0,
|
|
/* 884 */ 'w', '2', '4', 0,
|
|
/* 888 */ 'x', '2', '4', 0,
|
|
/* 892 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0,
|
|
/* 904 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0,
|
|
/* 916 */ 'b', '4', 0,
|
|
/* 919 */ 'd', '4', 0,
|
|
/* 922 */ 'h', '4', 0,
|
|
/* 925 */ 'q', '4', 0,
|
|
/* 928 */ 's', '4', 0,
|
|
/* 931 */ 'w', '4', 0,
|
|
/* 934 */ 'x', '4', 0,
|
|
/* 937 */ 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0,
|
|
/* 953 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0,
|
|
/* 969 */ 'b', '1', '5', 0,
|
|
/* 973 */ 'd', '1', '5', 0,
|
|
/* 977 */ 'h', '1', '5', 0,
|
|
/* 981 */ 'q', '1', '5', 0,
|
|
/* 985 */ 's', '1', '5', 0,
|
|
/* 989 */ 'w', '1', '5', 0,
|
|
/* 993 */ 'x', '1', '5', 0,
|
|
/* 997 */ 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0,
|
|
/* 1013 */ 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', 0,
|
|
/* 1029 */ 'b', '2', '5', 0,
|
|
/* 1033 */ 'd', '2', '5', 0,
|
|
/* 1037 */ 'h', '2', '5', 0,
|
|
/* 1041 */ 'q', '2', '5', 0,
|
|
/* 1045 */ 's', '2', '5', 0,
|
|
/* 1049 */ 'w', '2', '5', 0,
|
|
/* 1053 */ 'x', '2', '5', 0,
|
|
/* 1057 */ 'D', '2', '_', 'D', '3', '_', 'D', '4', '_', 'D', '5', 0,
|
|
/* 1069 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0,
|
|
/* 1081 */ 'b', '5', 0,
|
|
/* 1084 */ 'd', '5', 0,
|
|
/* 1087 */ 'h', '5', 0,
|
|
/* 1090 */ 'q', '5', 0,
|
|
/* 1093 */ 's', '5', 0,
|
|
/* 1096 */ 'w', '5', 0,
|
|
/* 1099 */ 'x', '5', 0,
|
|
/* 1102 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0,
|
|
/* 1118 */ 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', 0,
|
|
/* 1134 */ 'b', '1', '6', 0,
|
|
/* 1138 */ 'd', '1', '6', 0,
|
|
/* 1142 */ 'h', '1', '6', 0,
|
|
/* 1146 */ 'q', '1', '6', 0,
|
|
/* 1150 */ 's', '1', '6', 0,
|
|
/* 1154 */ 'w', '1', '6', 0,
|
|
/* 1158 */ 'x', '1', '6', 0,
|
|
/* 1162 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0,
|
|
/* 1178 */ 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', 0,
|
|
/* 1194 */ 'b', '2', '6', 0,
|
|
/* 1198 */ 'd', '2', '6', 0,
|
|
/* 1202 */ 'h', '2', '6', 0,
|
|
/* 1206 */ 'q', '2', '6', 0,
|
|
/* 1210 */ 's', '2', '6', 0,
|
|
/* 1214 */ 'w', '2', '6', 0,
|
|
/* 1218 */ 'x', '2', '6', 0,
|
|
/* 1222 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0,
|
|
/* 1234 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0,
|
|
/* 1246 */ 'b', '6', 0,
|
|
/* 1249 */ 'd', '6', 0,
|
|
/* 1252 */ 'h', '6', 0,
|
|
/* 1255 */ 'q', '6', 0,
|
|
/* 1258 */ 's', '6', 0,
|
|
/* 1261 */ 'w', '6', 0,
|
|
/* 1264 */ 'x', '6', 0,
|
|
/* 1267 */ 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0,
|
|
/* 1283 */ 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', 0,
|
|
/* 1299 */ 'b', '1', '7', 0,
|
|
/* 1303 */ 'd', '1', '7', 0,
|
|
/* 1307 */ 'h', '1', '7', 0,
|
|
/* 1311 */ 'q', '1', '7', 0,
|
|
/* 1315 */ 's', '1', '7', 0,
|
|
/* 1319 */ 'w', '1', '7', 0,
|
|
/* 1323 */ 'x', '1', '7', 0,
|
|
/* 1327 */ 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0,
|
|
/* 1343 */ 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', 0,
|
|
/* 1359 */ 'b', '2', '7', 0,
|
|
/* 1363 */ 'd', '2', '7', 0,
|
|
/* 1367 */ 'h', '2', '7', 0,
|
|
/* 1371 */ 'q', '2', '7', 0,
|
|
/* 1375 */ 's', '2', '7', 0,
|
|
/* 1379 */ 'w', '2', '7', 0,
|
|
/* 1383 */ 'x', '2', '7', 0,
|
|
/* 1387 */ 'D', '4', '_', 'D', '5', '_', 'D', '6', '_', 'D', '7', 0,
|
|
/* 1399 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0,
|
|
/* 1411 */ 'b', '7', 0,
|
|
/* 1414 */ 'd', '7', 0,
|
|
/* 1417 */ 'h', '7', 0,
|
|
/* 1420 */ 'q', '7', 0,
|
|
/* 1423 */ 's', '7', 0,
|
|
/* 1426 */ 'w', '7', 0,
|
|
/* 1429 */ 'x', '7', 0,
|
|
/* 1432 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0,
|
|
/* 1448 */ 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', 0,
|
|
/* 1464 */ 'b', '1', '8', 0,
|
|
/* 1468 */ 'd', '1', '8', 0,
|
|
/* 1472 */ 'h', '1', '8', 0,
|
|
/* 1476 */ 'q', '1', '8', 0,
|
|
/* 1480 */ 's', '1', '8', 0,
|
|
/* 1484 */ 'w', '1', '8', 0,
|
|
/* 1488 */ 'x', '1', '8', 0,
|
|
/* 1492 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0,
|
|
/* 1508 */ 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', 0,
|
|
/* 1524 */ 'b', '2', '8', 0,
|
|
/* 1528 */ 'd', '2', '8', 0,
|
|
/* 1532 */ 'h', '2', '8', 0,
|
|
/* 1536 */ 'q', '2', '8', 0,
|
|
/* 1540 */ 's', '2', '8', 0,
|
|
/* 1544 */ 'w', '2', '8', 0,
|
|
/* 1548 */ 'x', '2', '8', 0,
|
|
/* 1552 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0,
|
|
/* 1564 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0,
|
|
/* 1576 */ 'b', '8', 0,
|
|
/* 1579 */ 'd', '8', 0,
|
|
/* 1582 */ 'h', '8', 0,
|
|
/* 1585 */ 'q', '8', 0,
|
|
/* 1588 */ 's', '8', 0,
|
|
/* 1591 */ 'w', '8', 0,
|
|
/* 1594 */ 'x', '8', 0,
|
|
/* 1597 */ 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0,
|
|
/* 1613 */ 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', 0,
|
|
/* 1629 */ 'b', '1', '9', 0,
|
|
/* 1633 */ 'd', '1', '9', 0,
|
|
/* 1637 */ 'h', '1', '9', 0,
|
|
/* 1641 */ 'q', '1', '9', 0,
|
|
/* 1645 */ 's', '1', '9', 0,
|
|
/* 1649 */ 'w', '1', '9', 0,
|
|
/* 1653 */ 'x', '1', '9', 0,
|
|
/* 1657 */ 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0,
|
|
/* 1673 */ 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', 0,
|
|
/* 1689 */ 'b', '2', '9', 0,
|
|
/* 1693 */ 'd', '2', '9', 0,
|
|
/* 1697 */ 'h', '2', '9', 0,
|
|
/* 1701 */ 'q', '2', '9', 0,
|
|
/* 1705 */ 's', '2', '9', 0,
|
|
/* 1709 */ 'w', '2', '9', 0,
|
|
/* 1713 */ 'x', '2', '9', 0,
|
|
/* 1717 */ 'D', '6', '_', 'D', '7', '_', 'D', '8', '_', 'D', '9', 0,
|
|
/* 1729 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0,
|
|
/* 1741 */ 'b', '9', 0,
|
|
/* 1744 */ 'd', '9', 0,
|
|
/* 1747 */ 'h', '9', 0,
|
|
/* 1750 */ 'q', '9', 0,
|
|
/* 1753 */ 's', '9', 0,
|
|
/* 1756 */ 'w', '9', 0,
|
|
/* 1759 */ 'x', '9', 0,
|
|
/* 1762 */ 'w', 's', 'p', 0,
|
|
/* 1766 */ 'w', 'z', 'r', 0,
|
|
/* 1770 */ 'x', 'z', 'r', 0,
|
|
/* 1774 */ 'n', 'z', 'c', 'v', 0,
|
|
};
|
|
|
|
static const uint32_t RegAsmOffset[] = {
|
|
1774, 1762, 1766, 1763, 1770, 204, 421, 586, 751, 916, 1081, 1246, 1411, 1576,
|
|
1741, 26, 253, 472, 639, 804, 969, 1134, 1299, 1464, 1629, 86, 313, 532,
|
|
699, 864, 1029, 1194, 1359, 1524, 1689, 146, 373, 207, 424, 589, 754, 919,
|
|
1084, 1249, 1414, 1579, 1744, 30, 257, 476, 643, 808, 973, 1138, 1303, 1468,
|
|
1633, 90, 317, 536, 703, 868, 1033, 1198, 1363, 1528, 1693, 150, 377, 210,
|
|
427, 592, 757, 922, 1087, 1252, 1417, 1582, 1747, 34, 261, 480, 647, 812,
|
|
977, 1142, 1307, 1472, 1637, 94, 321, 540, 707, 872, 1037, 1202, 1367, 1532,
|
|
1697, 154, 381, 213, 430, 595, 760, 925, 1090, 1255, 1420, 1585, 1750, 38,
|
|
265, 484, 651, 816, 981, 1146, 1311, 1476, 1641, 98, 325, 544, 711, 876,
|
|
1041, 1206, 1371, 1536, 1701, 158, 385, 216, 433, 598, 763, 928, 1093, 1258,
|
|
1423, 1588, 1753, 42, 269, 488, 655, 820, 985, 1150, 1315, 1480, 1645, 102,
|
|
329, 548, 715, 880, 1045, 1210, 1375, 1540, 1705, 162, 389, 219, 436, 601,
|
|
766, 931, 1096, 1261, 1426, 1591, 1756, 46, 273, 492, 659, 824, 989, 1154,
|
|
1319, 1484, 1649, 106, 333, 552, 719, 884, 1049, 1214, 1379, 1544, 1709, 166,
|
|
222, 439, 604, 769, 934, 1099, 1264, 1429, 1594, 1759, 50, 277, 496, 663,
|
|
828, 993, 1158, 1323, 1488, 1653, 110, 337, 556, 723, 888, 1053, 1218, 1383,
|
|
1548, 1713, 170, 401, 567, 733, 898, 1063, 1228, 1393, 1558, 1723, 6, 231,
|
|
449, 615, 780, 945, 1110, 1275, 1440, 1605, 62, 289, 508, 675, 840, 1005,
|
|
1170, 1335, 1500, 1665, 122, 349, 182, 415, 580, 745, 910, 1075, 1240, 1405,
|
|
1570, 1735, 19, 245, 464, 631, 796, 961, 1126, 1291, 1456, 1621, 78, 305,
|
|
524, 691, 856, 1021, 1186, 1351, 1516, 1681, 138, 365, 197, 564, 730, 895,
|
|
1060, 1225, 1390, 1555, 1720, 3, 228, 445, 611, 776, 941, 1106, 1271, 1436,
|
|
1601, 58, 285, 504, 671, 836, 1001, 1166, 1331, 1496, 1661, 118, 345, 178,
|
|
397, 577, 742, 907, 1072, 1237, 1402, 1567, 1732, 16, 242, 460, 627, 792,
|
|
957, 1122, 1287, 1452, 1617, 74, 301, 520, 687, 852, 1017, 1182, 1347, 1512,
|
|
1677, 134, 361, 193, 411, 727, 892, 1057, 1222, 1387, 1552, 1717, 0, 225,
|
|
442, 607, 772, 937, 1102, 1267, 1432, 1597, 54, 281, 500, 667, 832, 997,
|
|
1162, 1327, 1492, 1657, 114, 341, 174, 393, 560, 739, 904, 1069, 1234, 1399,
|
|
1564, 1729, 13, 239, 457, 623, 788, 953, 1118, 1283, 1448, 1613, 70, 297,
|
|
516, 683, 848, 1013, 1178, 1343, 1508, 1673, 130, 357, 189, 407, 573,
|
|
};
|
|
|
|
//int i;
|
|
//for (i = 0; i < sizeof(RegAsmOffset)/4; i++)
|
|
// printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
|
|
//printf("*************************\n");
|
|
return AsmStrs+RegAsmOffset[RegNo-1];
|
|
#else
|
|
return NULL;
|
|
#endif
|
|
}
|
|
|
|
#ifdef PRINT_ALIAS_INSTR
|
|
#undef PRINT_ALIAS_INSTR
|
|
|
|
static char *printAliasInstr(MCInst *MI, SStream *OS, void *info)
|
|
{
|
|
#define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
|
|
const char *AsmString;
|
|
MCRegisterInfo *MRI = (MCRegisterInfo *)info;
|
|
switch (MCInst_getOpcode(MI)) {
|
|
default: return NULL;
|
|
case AArch64_ADDSwww_lsl:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (ADDSwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0)
|
|
AsmString = "adds $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_ADDSwww_uxtw:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (ADDSwww_uxtw GPR32:$Rd, Rwsp:$Rn, GPR32:$Rm, 0)
|
|
AsmString = "adds $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_ADDSxxx_lsl:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (ADDSxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0)
|
|
AsmString = "adds $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_ADDSxxx_uxtx:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (ADDSxxx_uxtx GPR64:$Rd, Rxsp:$Rn, GPR64:$Rm, 0)
|
|
AsmString = "adds $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_ADDwwi_lsl0_s:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32wspRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (ADDwwi_lsl0_s GPR32wsp:$Rd, Rwsp:$Rn, 0)
|
|
AsmString = "mov $\x01, $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32wspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (ADDwwi_lsl0_s Rwsp:$Rd, GPR32wsp:$Rn, 0)
|
|
AsmString = "mov $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_ADDwww_lsl:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (ADDwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0)
|
|
AsmString = "add $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_ADDwww_uxtw:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32wspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (ADDwww_uxtw Rwsp:$Rd, GPR32wsp:$Rn, GPR32:$Rm, 0)
|
|
AsmString = "add $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32wspRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (ADDwww_uxtw GPR32wsp:$Rd, Rwsp:$Rn, GPR32:$Rm, 0)
|
|
AsmString = "add $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_ADDxxi_lsl0_s:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (ADDxxi_lsl0_s GPR64xsp:$Rd, Rxsp:$Rn, 0)
|
|
AsmString = "mov $\x01, $\x02";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (ADDxxi_lsl0_s Rxsp:$Rd, GPR64xsp:$Rn, 0)
|
|
AsmString = "mov $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_ADDxxx_lsl:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (ADDxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0)
|
|
AsmString = "add $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_ADDxxx_uxtx:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (ADDxxx_uxtx Rxsp:$Rd, GPR64xsp:$Rn, GPR64:$Rm, 0)
|
|
AsmString = "add $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (ADDxxx_uxtx GPR64xsp:$Rd, Rxsp:$Rn, GPR64:$Rm, 0)
|
|
AsmString = "add $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_ANDSwww_lsl:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (ANDSwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0)
|
|
AsmString = "ands $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_ANDSxxx_lsl:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (ANDSxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0)
|
|
AsmString = "ands $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_ANDwww_lsl:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (ANDwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0)
|
|
AsmString = "and $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_ANDxxx_lsl:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (ANDxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0)
|
|
AsmString = "and $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_BICSwww_lsl:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (BICSwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0)
|
|
AsmString = "bics $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_BICSxxx_lsl:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (BICSxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0)
|
|
AsmString = "bics $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_BICwww_lsl:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (BICwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0)
|
|
AsmString = "bic $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_BICxxx_lsl:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (BICxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0)
|
|
AsmString = "bic $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_CLREXi:
|
|
if (MCInst_getNumOperands(MI) == 1 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) {
|
|
// (CLREXi 15)
|
|
AsmString = "clrex";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_CMNww_lsl:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (CMNww_lsl GPR32:$Rn, GPR32:$Rm, 0)
|
|
AsmString = "cmn $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_CMNww_uxtw:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (CMNww_uxtw Rwsp:$Rn, GPR32:$Rm, 0)
|
|
AsmString = "cmn $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_CMNxx_lsl:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (CMNxx_lsl GPR64:$Rn, GPR64:$Rm, 0)
|
|
AsmString = "cmn $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_CMNxx_uxtx:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (CMNxx_uxtx Rxsp:$Rn, GPR64:$Rm, 0)
|
|
AsmString = "cmn $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_CMPww_lsl:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (CMPww_lsl GPR32:$Rn, GPR32:$Rm, 0)
|
|
AsmString = "cmp $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_CMPww_uxtw:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (CMPww_uxtw Rwsp:$Rn, GPR32:$Rm, 0)
|
|
AsmString = "cmp $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_CMPxx_lsl:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (CMPxx_lsl GPR64:$Rn, GPR64:$Rm, 0)
|
|
AsmString = "cmp $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_CMPxx_uxtx:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (CMPxx_uxtx Rxsp:$Rn, GPR64:$Rm, 0)
|
|
AsmString = "cmp $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_DCPS1i:
|
|
if (MCInst_getNumOperands(MI) == 1 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) {
|
|
// (DCPS1i 0)
|
|
AsmString = "dcps1";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_DCPS2i:
|
|
if (MCInst_getNumOperands(MI) == 1 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) {
|
|
// (DCPS2i 0)
|
|
AsmString = "dcps2";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_DCPS3i:
|
|
if (MCInst_getNumOperands(MI) == 1 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) {
|
|
// (DCPS3i 0)
|
|
AsmString = "dcps3";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_EONwww_lsl:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (EONwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0)
|
|
AsmString = "eon $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_EONxxx_lsl:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (EONxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0)
|
|
AsmString = "eon $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_EORwww_lsl:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (EORwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0)
|
|
AsmString = "eor $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_EORxxx_lsl:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (EORxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0)
|
|
AsmString = "eor $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_HINTi:
|
|
if (MCInst_getNumOperands(MI) == 1 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) {
|
|
// (HINTi 0)
|
|
AsmString = "nop";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 1 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1) {
|
|
// (HINTi 1)
|
|
AsmString = "yield";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 1 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2) {
|
|
// (HINTi 2)
|
|
AsmString = "wfe";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 1 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 3) {
|
|
// (HINTi 3)
|
|
AsmString = "wfi";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 1 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4) {
|
|
// (HINTi 4)
|
|
AsmString = "sev";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 1 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 5) {
|
|
// (HINTi 5)
|
|
AsmString = "sevl";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_ISBi:
|
|
if (MCInst_getNumOperands(MI) == 1 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) {
|
|
// (ISBi 15)
|
|
AsmString = "isb";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LDPSWx:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (LDPSWx GPR64:$Rt, GPR64:$Rt2, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldpsw $\x01, $\x02, [$\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LDRSBw:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LDRSBw GPR32:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldrsb $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LDRSBw_Xm_RegOffset:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
|
|
// (LDRSBw_Xm_RegOffset GPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
|
|
AsmString = "ldrsb $\x01, [$\x02, $\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LDRSBx:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LDRSBx GPR64:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldrsb $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LDRSBx_Xm_RegOffset:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
|
|
// (LDRSBx_Xm_RegOffset GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
|
|
AsmString = "ldrsb $\x01, [$\x02, $\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LDRSHw:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LDRSHw GPR32:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldrsh $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LDRSHw_Xm_RegOffset:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
|
|
// (LDRSHw_Xm_RegOffset GPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
|
|
AsmString = "ldrsh $\x01, [$\x02, $\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LDRSHx:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LDRSHx GPR64:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldrsh $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LDRSHx_Xm_RegOffset:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
|
|
// (LDRSHx_Xm_RegOffset GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
|
|
AsmString = "ldrsh $\x01, [$\x02, $\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LDRSWx:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LDRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldrsw $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LDRSWx_Xm_RegOffset:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
|
|
// (LDRSWx_Xm_RegOffset GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
|
|
AsmString = "ldrsw $\x01, [$\x02, $\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LDTRSBw:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LDTRSBw GPR32:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldtrsb $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LDTRSBx:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LDTRSBx GPR64:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldtrsb $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LDTRSHw:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LDTRSHw GPR32:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldtrsh $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LDTRSHx:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LDTRSHx GPR64:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldtrsh $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LDTRSWx:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LDTRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldtrsw $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LDURSWx:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LDURSWx GPR64:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldursw $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS16_LDR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LS16_LDR GPR32:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldrh $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS16_LDUR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LS16_LDUR GPR32:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldurh $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS16_STR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LS16_STR GPR32:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "strh $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS16_STUR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LS16_STUR GPR32:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "sturh $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS16_UnPriv_LDR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LS16_UnPriv_LDR GPR32:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldtrh $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS16_UnPriv_STR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LS16_UnPriv_STR GPR32:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "sttrh $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS16_Xm_RegOffset_LDR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
|
|
// (LS16_Xm_RegOffset_LDR GPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
|
|
AsmString = "ldrh $\x01, [$\x02, $\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS16_Xm_RegOffset_STR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
|
|
// (LS16_Xm_RegOffset_STR GPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
|
|
AsmString = "strh $\x01, [$\x02, $\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS32_LDR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LS32_LDR GPR32:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldr $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS32_LDUR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LS32_LDUR GPR32:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldur $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS32_STR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LS32_STR GPR32:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "str $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS32_STUR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LS32_STUR GPR32:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "stur $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS32_UnPriv_LDR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LS32_UnPriv_LDR GPR32:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldtr $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS32_UnPriv_STR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LS32_UnPriv_STR GPR32:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "sttr $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS32_Xm_RegOffset_LDR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
|
|
// (LS32_Xm_RegOffset_LDR GPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
|
|
AsmString = "ldr $\x01, [$\x02, $\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS32_Xm_RegOffset_STR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
|
|
// (LS32_Xm_RegOffset_STR GPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
|
|
AsmString = "str $\x01, [$\x02, $\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS64_LDR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LS64_LDR GPR64:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldr $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS64_LDUR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LS64_LDUR GPR64:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldur $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS64_STR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LS64_STR GPR64:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "str $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS64_STUR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LS64_STUR GPR64:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "stur $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS64_UnPriv_LDR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LS64_UnPriv_LDR GPR64:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldtr $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS64_UnPriv_STR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LS64_UnPriv_STR GPR64:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "sttr $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS64_Xm_RegOffset_LDR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
|
|
// (LS64_Xm_RegOffset_LDR GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
|
|
AsmString = "ldr $\x01, [$\x02, $\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS64_Xm_RegOffset_STR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
|
|
// (LS64_Xm_RegOffset_STR GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
|
|
AsmString = "str $\x01, [$\x02, $\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS8_LDR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LS8_LDR GPR32:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldrb $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS8_LDUR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LS8_LDUR GPR32:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldurb $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS8_STR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LS8_STR GPR32:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "strb $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS8_STUR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LS8_STUR GPR32:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "sturb $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS8_UnPriv_LDR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LS8_UnPriv_LDR GPR32:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldtrb $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS8_UnPriv_STR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LS8_UnPriv_STR GPR32:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "sttrb $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS8_Xm_RegOffset_LDR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
|
|
// (LS8_Xm_RegOffset_LDR GPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
|
|
AsmString = "ldrb $\x01, [$\x02, $\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LS8_Xm_RegOffset_STR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
|
|
// (LS8_Xm_RegOffset_STR GPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
|
|
AsmString = "strb $\x01, [$\x02, $\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP128_LDR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LSFP128_LDR FPR128:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldr $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP128_LDUR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LSFP128_LDUR FPR128:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldur $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP128_STR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LSFP128_STR FPR128:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "str $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP128_STUR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LSFP128_STUR FPR128:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "stur $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP128_Xm_RegOffset_LDR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
|
|
// (LSFP128_Xm_RegOffset_LDR FPR128:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
|
|
AsmString = "ldr $\x01, [$\x02, $\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP128_Xm_RegOffset_STR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
|
|
// (LSFP128_Xm_RegOffset_STR FPR128:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
|
|
AsmString = "str $\x01, [$\x02, $\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP16_LDR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LSFP16_LDR FPR16:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldr $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP16_LDUR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LSFP16_LDUR FPR16:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldur $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP16_STR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LSFP16_STR FPR16:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "str $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP16_STUR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LSFP16_STUR FPR16:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "stur $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP16_Xm_RegOffset_LDR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
|
|
// (LSFP16_Xm_RegOffset_LDR FPR16:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
|
|
AsmString = "ldr $\x01, [$\x02, $\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP16_Xm_RegOffset_STR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
|
|
// (LSFP16_Xm_RegOffset_STR FPR16:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
|
|
AsmString = "str $\x01, [$\x02, $\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP32_LDR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LSFP32_LDR FPR32:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldr $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP32_LDUR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LSFP32_LDUR FPR32:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldur $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP32_STR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LSFP32_STR FPR32:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "str $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP32_STUR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LSFP32_STUR FPR32:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "stur $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP32_Xm_RegOffset_LDR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
|
|
// (LSFP32_Xm_RegOffset_LDR FPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
|
|
AsmString = "ldr $\x01, [$\x02, $\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP32_Xm_RegOffset_STR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
|
|
// (LSFP32_Xm_RegOffset_STR FPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
|
|
AsmString = "str $\x01, [$\x02, $\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP64_LDR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LSFP64_LDR FPR64:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldr $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP64_LDUR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LSFP64_LDUR FPR64:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldur $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP64_STR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LSFP64_STR FPR64:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "str $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP64_STUR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LSFP64_STUR FPR64:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "stur $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP64_Xm_RegOffset_LDR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
|
|
// (LSFP64_Xm_RegOffset_LDR FPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
|
|
AsmString = "ldr $\x01, [$\x02, $\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP64_Xm_RegOffset_STR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
|
|
// (LSFP64_Xm_RegOffset_STR FPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
|
|
AsmString = "str $\x01, [$\x02, $\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP8_LDR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LSFP8_LDR FPR8:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldr $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP8_LDUR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LSFP8_LDUR FPR8:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldur $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP8_STR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LSFP8_STR FPR8:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "str $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP8_STUR:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (LSFP8_STUR FPR8:$Rt, GPR64xsp:$Rn, 0)
|
|
AsmString = "stur $\x01, [$\x02]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP8_Xm_RegOffset_LDR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
|
|
// (LSFP8_Xm_RegOffset_LDR FPR8:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
|
|
AsmString = "ldr $\x01, [$\x02, $\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFP8_Xm_RegOffset_STR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
|
|
// (LSFP8_Xm_RegOffset_STR FPR8:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
|
|
AsmString = "str $\x01, [$\x02, $\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFPPair128_LDR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (LSFPPair128_LDR FPR128:$Rt, FPR128:$Rt2, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldp $\x01, $\x02, [$\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFPPair128_NonTemp_LDR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (LSFPPair128_NonTemp_LDR FPR128:$Rt, FPR128:$Rt2, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldnp $\x01, $\x02, [$\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFPPair128_NonTemp_STR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (LSFPPair128_NonTemp_STR FPR128:$Rt, FPR128:$Rt2, GPR64xsp:$Rn, 0)
|
|
AsmString = "stnp $\x01, $\x02, [$\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFPPair128_STR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (LSFPPair128_STR FPR128:$Rt, FPR128:$Rt2, GPR64xsp:$Rn, 0)
|
|
AsmString = "stp $\x01, $\x02, [$\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFPPair32_LDR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (LSFPPair32_LDR FPR32:$Rt, FPR32:$Rt2, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldp $\x01, $\x02, [$\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFPPair32_NonTemp_LDR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (LSFPPair32_NonTemp_LDR FPR32:$Rt, FPR32:$Rt2, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldnp $\x01, $\x02, [$\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFPPair32_NonTemp_STR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (LSFPPair32_NonTemp_STR FPR32:$Rt, FPR32:$Rt2, GPR64xsp:$Rn, 0)
|
|
AsmString = "stnp $\x01, $\x02, [$\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFPPair32_STR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (LSFPPair32_STR FPR32:$Rt, FPR32:$Rt2, GPR64xsp:$Rn, 0)
|
|
AsmString = "stp $\x01, $\x02, [$\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFPPair64_LDR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (LSFPPair64_LDR FPR64:$Rt, FPR64:$Rt2, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldp $\x01, $\x02, [$\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFPPair64_NonTemp_LDR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (LSFPPair64_NonTemp_LDR FPR64:$Rt, FPR64:$Rt2, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldnp $\x01, $\x02, [$\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFPPair64_NonTemp_STR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (LSFPPair64_NonTemp_STR FPR64:$Rt, FPR64:$Rt2, GPR64xsp:$Rn, 0)
|
|
AsmString = "stnp $\x01, $\x02, [$\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSFPPair64_STR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (LSFPPair64_STR FPR64:$Rt, FPR64:$Rt2, GPR64xsp:$Rn, 0)
|
|
AsmString = "stp $\x01, $\x02, [$\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSPair32_LDR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (LSPair32_LDR GPR32:$Rt, GPR32:$Rt2, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldp $\x01, $\x02, [$\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSPair32_NonTemp_LDR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (LSPair32_NonTemp_LDR GPR32:$Rt, GPR32:$Rt2, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldnp $\x01, $\x02, [$\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSPair32_NonTemp_STR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (LSPair32_NonTemp_STR GPR32:$Rt, GPR32:$Rt2, GPR64xsp:$Rn, 0)
|
|
AsmString = "stnp $\x01, $\x02, [$\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSPair32_STR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (LSPair32_STR GPR32:$Rt, GPR32:$Rt2, GPR64xsp:$Rn, 0)
|
|
AsmString = "stp $\x01, $\x02, [$\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSPair64_LDR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (LSPair64_LDR GPR64:$Rt, GPR64:$Rt2, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldp $\x01, $\x02, [$\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSPair64_NonTemp_LDR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (LSPair64_NonTemp_LDR GPR64:$Rt, GPR64:$Rt2, GPR64xsp:$Rn, 0)
|
|
AsmString = "ldnp $\x01, $\x02, [$\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSPair64_NonTemp_STR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (LSPair64_NonTemp_STR GPR64:$Rt, GPR64:$Rt2, GPR64xsp:$Rn, 0)
|
|
AsmString = "stnp $\x01, $\x02, [$\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_LSPair64_STR:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (LSPair64_STR GPR64:$Rt, GPR64:$Rt2, GPR64xsp:$Rn, 0)
|
|
AsmString = "stp $\x01, $\x02, [$\x03]";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_MADDwwww:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_WZR) {
|
|
// (MADDwwww GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, WZR)
|
|
AsmString = "mul $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_MADDxxxx:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
|
|
// (MADDxxxx GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, XZR)
|
|
AsmString = "mul $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_MSUBwwww:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_WZR) {
|
|
// (MSUBwwww GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, WZR)
|
|
AsmString = "mneg $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_MSUBxxxx:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
|
|
// (MSUBxxxx GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, XZR)
|
|
AsmString = "mneg $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_MVNww_lsl:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (MVNww_lsl GPR32:$Rn, GPR32:$Rm, 0)
|
|
AsmString = "mvn $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_MVNxx_lsl:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (MVNxx_lsl GPR64:$Rn, GPR64:$Rm, 0)
|
|
AsmString = "mvn $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_ORNwww_lsl:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (ORNwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0)
|
|
AsmString = "orn $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_ORNxxx_lsl:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (ORNxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0)
|
|
AsmString = "orn $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_ORRwww_lsl:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (ORRwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)
|
|
AsmString = "mov $\x01, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (ORRwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0)
|
|
AsmString = "orr $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_ORRxxx_lsl:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (ORRxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)
|
|
AsmString = "mov $\x01, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (ORRxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0)
|
|
AsmString = "orr $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_RETx:
|
|
if (MCInst_getNumOperands(MI) == 1 &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_X30) {
|
|
// (RETx X30)
|
|
AsmString = "ret";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_SBCSwww:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) {
|
|
// (SBCSwww GPR32:$Rd, WZR, GPR32:$Rm)
|
|
AsmString = "ngcs $\x01, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_SBCSxxx:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) {
|
|
// (SBCSxxx GPR64:$Rd, XZR, GPR64:$Rm)
|
|
AsmString = "ngcs $\x01, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_SBCwww:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) {
|
|
// (SBCwww GPR32:$Rd, WZR, GPR32:$Rm)
|
|
AsmString = "ngc $\x01, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_SBCxxx:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) {
|
|
// (SBCxxx GPR64:$Rd, XZR, GPR64:$Rm)
|
|
AsmString = "ngc $\x01, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_SMADDLxwwx:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
|
|
// (SMADDLxwwx GPR64:$Rd, GPR32:$Rn, GPR32:$Rm, XZR)
|
|
AsmString = "smull $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_SMSUBLxwwx:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
|
|
// (SMSUBLxwwx GPR64:$Rd, GPR32:$Rn, GPR32:$Rm, XZR)
|
|
AsmString = "smnegl $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_SUBSwww_lsl:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (SUBSwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0)
|
|
AsmString = "subs $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (SUBSwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)
|
|
AsmString = "negs $\x01, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_SUBSwww_uxtw:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (SUBSwww_uxtw GPR32:$Rd, Rwsp:$Rn, GPR32:$Rm, 0)
|
|
AsmString = "subs $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_SUBSxxx_lsl:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (SUBSxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0)
|
|
AsmString = "subs $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (SUBSxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)
|
|
AsmString = "negs $\x01, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_SUBSxxx_uxtx:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (SUBSxxx_uxtx GPR64:$Rd, Rxsp:$Rn, GPR64:$Rm, 0)
|
|
AsmString = "subs $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_SUBwww_lsl:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (SUBwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0)
|
|
AsmString = "sub $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (SUBwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)
|
|
AsmString = "neg $\x01, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_SUBwww_uxtw:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32wspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (SUBwww_uxtw Rwsp:$Rd, GPR32wsp:$Rn, GPR32:$Rm, 0)
|
|
AsmString = "sub $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32wspRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (SUBwww_uxtw GPR32wsp:$Rd, Rwsp:$Rn, GPR32:$Rm, 0)
|
|
AsmString = "sub $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_SUBxxx_lsl:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (SUBxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0)
|
|
AsmString = "sub $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (SUBxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)
|
|
AsmString = "neg $\x01, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_SUBxxx_uxtx:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (SUBxxx_uxtx Rxsp:$Rd, GPR64xsp:$Rn, GPR64:$Rm, 0)
|
|
AsmString = "sub $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
|
|
// (SUBxxx_uxtx GPR64xsp:$Rd, Rxsp:$Rn, GPR64:$Rm, 0)
|
|
AsmString = "sub $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_TSTww_lsl:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (TSTww_lsl GPR32:$Rn, GPR32:$Rm, 0)
|
|
AsmString = "tst $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_TSTxx_lsl:
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
|
|
// (TSTxx_lsl GPR64:$Rn, GPR64:$Rm, 0)
|
|
AsmString = "tst $\x01, $\x02";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_UMADDLxwwx:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
|
|
// (UMADDLxwwx GPR64:$Rd, GPR32:$Rn, GPR32:$Rm, XZR)
|
|
AsmString = "umull $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
case AArch64_UMSUBLxwwx:
|
|
if (MCInst_getNumOperands(MI) == 4 &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
|
|
GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
|
|
MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
|
|
// (UMSUBLxwwx GPR64:$Rd, GPR32:$Rn, GPR32:$Rm, XZR)
|
|
AsmString = "umnegl $\x01, $\x02, $\x03";
|
|
break;
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
char *tmp = cs_strdup(AsmString), *AsmMnem, *AsmOps;
|
|
AsmMnem = tmp;
|
|
AsmOps = strchr(tmp, ' ');
|
|
if (AsmOps) {
|
|
*AsmOps = '\0';
|
|
AsmOps += 1;
|
|
}
|
|
SStream_concat(OS, "%s", AsmMnem);
|
|
if (AsmOps) {
|
|
SStream_concat(OS, "\t");
|
|
char *c;
|
|
for (c = AsmOps; *c; c++) {
|
|
if (*c == '$') {
|
|
c += 1;
|
|
printOperand(MI, *c - 1, OS);
|
|
} else {
|
|
SStream_concat(OS, "%c", *c);
|
|
}
|
|
}
|
|
}
|
|
return tmp;
|
|
}
|
|
|
|
#endif // PRINT_ALIAS_INSTR
|