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Page: ChangeLog 3.0.1 RC2
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Binding changes for binding authors version 2.1 Branching Model Capstone 4.0 New API to provide explicit registers ChangeLog 2.0 ChangeLog 2.1.1 ChangeLog 2.1.2 ChangeLog 2.1 ChangeLog 3.0.1 RC1 ChangeLog 3.0.1 RC2 ChangeLog 3.0.1 ChangeLog 3.0.2 ChangeLog 3.0.3 RC1 ChangeLog 3.0.3 ChangeLog 3.0.4 ChangeLog 3.0.5 ChangeLog 3.0 ChangeLog 4.0 alpha1 ChangeLog from 2.1.2 to 3.0 rc1 ChangeLog since 3.0 rc1 ChangeLog since 3.0 rc2 ChangeLog since 3.0 rc3 ChangeLog Changes from "next" to "v3" for binding authors Home Ideas for next version(s) . Feel free to add yours! Installing on Cygwin & Python3 New APIs: cs_disasm_alloc() & cs_disasm_buf() Next branch Release Guide
3 ChangeLog 3.0.1 RC2
Nguyen Anh Quynh edited this page 2015-01-20 14:37:08 +08:00

This is the changelog for version 3.0.1-rc2. (Look here for the detailed changelog of v3.0.1-rc1)

NOTE: changes are listed in time order: newer changes are at the top, older changes are at the bottom.

Arm64:

  • BL & BLR instructions do not read SP register.

Arm:

  • Instructions ADC & SBC do not update flags.

X86:

  • Properly handle LOCK, REP, REPE & REPNE prefixes.

Python:

  • Fix a Cython bug when CsInsn.bytes returns a shorten array of bytes.
  • Fixed a memory leak for Cython disasm functions when we immaturely quit the enumeration of disassembled instructions.