From 02b6e39ab16cdc920a835cb183be111199523e11 Mon Sep 17 00:00:00 2001 From: Sean Stangl Date: Fri, 30 Nov 2018 11:21:00 +0200 Subject: [PATCH] Bug 1510749 - The AArch64 ISR explicitly allows CSINC to accept ZR. r=nbp --HG-- extra : rebase_source : 66b7a76d979bd2aa8c8b228cba39db9310287944 --- js/src/jit/arm64/vixl/MacroAssembler-vixl.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/js/src/jit/arm64/vixl/MacroAssembler-vixl.h b/js/src/jit/arm64/vixl/MacroAssembler-vixl.h index f5e94f1714f8..25d14fef8aef 100644 --- a/js/src/jit/arm64/vixl/MacroAssembler-vixl.h +++ b/js/src/jit/arm64/vixl/MacroAssembler-vixl.h @@ -656,8 +656,12 @@ class MacroAssembler : public js::jit::Assembler { const Register& rm, Condition cond) { VIXL_ASSERT(!rd.IsZero()); - VIXL_ASSERT(!rn.IsZero()); - VIXL_ASSERT(!rm.IsZero()); + // The VIXL source code contains these assertions, but the AArch64 ISR + // explicitly permits the use of zero registers. CSET itself is defined + // in terms of CSINC with WZR/XZR. + // + // VIXL_ASSERT(!rn.IsZero()); + // VIXL_ASSERT(!rm.IsZero()); VIXL_ASSERT((cond != al) && (cond != nv)); SingleEmissionCheckScope guard(this); csinc(rd, rn, rm, cond);