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Bug 1050291 - ARM Simulator: Fix vmovl quad register encoding. r=nbp

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This commit is contained in:
Douglas Crosher 2014-08-08 09:49:30 +10:00
parent 46562a3c3a
commit 085bd57620
1 changed files with 6 additions and 2 deletions
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8
js/src/jit/arm/Simulator-arm.cpp
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@ -3862,7 +3862,9 @@ Simulator::decodeSpecialCondition(SimInstruction *instr)
case 5: case 5:
if (instr->bits(18, 16) == 0 && instr->bits(11, 6) == 0x28 && instr->bit(4) == 1) { if (instr->bits(18, 16) == 0 && instr->bits(11, 6) == 0x28 && instr->bit(4) == 1) {
// vmovl signed // vmovl signed
int Vd = (instr->bit(22) << 4) | instr->vdValue(); if ((instr->vdValue() & 1) != 0)
MOZ_CRASH("Undefined behavior");
int Vd = (instr->bit(22) << 3) | (instr->vdValue() >> 1);
int Vm = (instr->bit(5) << 4) | instr->vmValue(); int Vm = (instr->bit(5) << 4) | instr->vmValue();
int imm3 = instr->bits(21, 19); int imm3 = instr->bits(21, 19);
if (imm3 != 1 && imm3 != 2 && imm3 != 4) if (imm3 != 1 && imm3 != 2 && imm3 != 4)
@ -3885,7 +3887,9 @@ Simulator::decodeSpecialCondition(SimInstruction *instr)
case 7: case 7:
if (instr->bits(18, 16) == 0 && instr->bits(11, 6) == 0x28 && instr->bit(4) == 1) { if (instr->bits(18, 16) == 0 && instr->bits(11, 6) == 0x28 && instr->bit(4) == 1) {
// vmovl unsigned. // vmovl unsigned.
int Vd = (instr->bit(22) << 4) | instr->vdValue(); if ((instr->vdValue() & 1) != 0)
MOZ_CRASH("Undefined behavior");
int Vd = (instr->bit(22) << 3) | (instr->vdValue() >> 1);
int Vm = (instr->bit(5) << 4) | instr->vmValue(); int Vm = (instr->bit(5) << 4) | instr->vmValue();
int imm3 = instr->bits(21, 19); int imm3 = instr->bits(21, 19);
if (imm3 != 1 && imm3 != 2 && imm3 != 4) if (imm3 != 1 && imm3 != 2 && imm3 != 4)