Make TM fragment entry- and exit-profiling work on X64 (bug 517857, r=dvander).

--HG--
extra : convert_revision : a7dc90cf8f8c7d121cc9d786742e690897d5ddc8

js/src/nanojit/NativeX64.cpp

@@ -1787,6 +1787,13 @@ namespace nanojit
             }
         }
 
+        // profiling for the exit
+        verbose_only(
+           if (_logc->lcbits & LC_FragProfile) {
+              asm_inc_m32( &guard->record()->profCount );
+           }
+        )
+
         MR(RSP, RBP);
 
         // return value is GuardRecord*
@@ -1861,9 +1868,17 @@ namespace nanojit
     // Increment the 32-bit profiling counter at pCtr, without
     // changing any registers.
     verbose_only(
-    void Assembler::asm_inc_m32(uint32_t* /*pCtr*/)
+    void Assembler::asm_inc_m32(uint32_t* pCtr)
     {
-        // todo: implement this
+        // Not as simple as on x86.  We need to temporarily free up a
+        // register into which to generate the address, so just push
+        // it on the stack.  This assumes that the scratch area at
+        // -8(%rsp) .. -1(%esp) isn't being used for anything else
+        // at this point.
+        emitr(X64_popr, RAX);             // popq    %rax
+        emit(X64_inclmRAX);               // incl    (%rax)
+        asm_quad(RAX, (uint64_t)pCtr);    // movabsq $pCtr, %rax
+        emitr(X64_pushr, RAX);            // pushq   %rax
     }
     )
 

js/src/nanojit/NativeX64.h

@@ -307,6 +307,7 @@ namespace nanojit
         X64_xorps   = 0xC0570F4000000004LL, // 128bit xor xmm (four packed singles), one byte shorter
         X64_xorpsm  = 0x05570F4000000004LL, // 128bit xor xmm, [rip+disp32]
         X64_xorpsa  = 0x2504570F40000005LL, // 128bit xor xmm, [disp32]
+        X64_inclmRAX= 0x00FF000000000002LL, // incl (%rax)
         X64_jmpx    = 0xC524ff4000000004LL, // jmp [d32+x*8]
         X64_jmpxb   = 0xC024ff4000000004LL, // jmp [b+x*8]