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Bug 580515 - TM: LIR_cmovd mishandled with X86_FORCE_SSE2=no. r=edwsmith.
--HG-- extra : convert_revision : 4effe362e918583ec7b98b08da24f02c0833d306
This commit is contained in:
Nicholas Nethercote
parent
884504296d
commit
18402713d9
@ -1173,20 +1173,24 @@ namespace nanojit
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Register rf = findRegFor(iffalse, allow & ~rmask(rr));
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if (ins->isop(LIR_cmovd)) {
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// See Nativei386.cpp:asm_cmov() for an explanation of the subtleties here.
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NIns* target = _nIns;
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asm_nongp_copy(rr, rf);
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asm_branch(false, cond, target);
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asm_branch_helper(false, cond, target);
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// If 'iftrue' isn't in a register, it can be clobbered by 'ins'.
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Register rt = iftrue->isInReg() ? iftrue->getReg() : rr;
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if (rr != rt)
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asm_nongp_copy(rr, rt);
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freeResourcesOf(ins);
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if (!iftrue->isInReg()) {
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NanoAssert(rt == rr);
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findSpecificRegForUnallocated(iftrue, rr);
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}
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asm_cmp(cond);
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return;
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}
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@ -1194,8 +1198,8 @@ namespace nanojit
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Register rt = iftrue->isInReg() ? iftrue->getReg() : rr;
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// WARNING: We cannot generate any code that affects the condition
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// codes between the MRcc generation here and the asm_cmp() call
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// below. See asm_cmp() for more details.
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// codes between the MRcc generation here and the asm_cmpi() call
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// below. See asm_cmpi() for more details.
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LOpcode condop = cond->opcode();
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if (ins->isop(LIR_cmovi)) {
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switch (condop) {
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@ -1234,30 +1238,36 @@ namespace nanojit
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findSpecificRegForUnallocated(iftrue, rr);
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}
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asm_cmp(cond);
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asm_cmpi(cond);
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}
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NIns* Assembler::asm_branch(bool onFalse, LIns *cond, NIns *target) {
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NanoAssert(cond->isCmp());
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LOpcode condop = cond->opcode();
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NIns* Assembler::asm_branch(bool onFalse, LIns* cond, NIns* target) {
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NIns* patch = asm_branch_helper(onFalse, cond, target);
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asm_cmp(cond);
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return patch;
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}
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NIns* Assembler::asm_branch_helper(bool onFalse, LIns *cond, NIns *target) {
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if (target && !isTargetWithinS32(target)) {
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// conditional jumps beyond 32bit range, so invert the branch/compare
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// and emit an unconditional jump to the target
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// A conditional jump beyond 32-bit range, so invert the
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// branch/compare and emit an unconditional jump to the target:
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// j(inverted) B1
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// jmp target
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// B1:
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NIns* shortTarget = _nIns;
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JMP(target);
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target = shortTarget;
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onFalse = !onFalse;
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}
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if (isCmpDOpcode(condop))
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return asm_branchd(onFalse, cond, target);
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return isCmpDOpcode(cond->opcode())
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? asm_branchd_helper(onFalse, cond, target)
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: asm_branchi_helper(onFalse, cond, target);
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}
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NIns* Assembler::asm_branchi_helper(bool onFalse, LIns *cond, NIns *target) {
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// We must ensure there's room for the instruction before calculating
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// the offset. And the offset determines the opcode (8bit or 32bit).
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LOpcode condop = cond->opcode();
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if (target && isTargetWithinS8(target)) {
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if (onFalse) {
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switch (condop) {
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@ -1315,9 +1325,7 @@ namespace nanojit
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}
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}
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}
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NIns *patch = _nIns; // address of instruction to patch
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asm_cmp(cond);
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return patch;
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return _nIns; // address of instruction to patch
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}
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NIns* Assembler::asm_branch_ov(LOpcode, NIns* target) {
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@ -1334,13 +1342,17 @@ namespace nanojit
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return _nIns;
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}
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void Assembler::asm_cmp(LIns *cond) {
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isCmpDOpcode(cond->opcode()) ? asm_cmpd(cond) : asm_cmpi(cond);
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}
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// WARNING: this function cannot generate code that will affect the
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// condition codes prior to the generation of the test/cmp. See
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// Nativei386.cpp:asm_cmp() for details.
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void Assembler::asm_cmp(LIns *cond) {
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// Nativei386.cpp:asm_cmpi() for details.
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void Assembler::asm_cmpi(LIns *cond) {
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LIns *b = cond->oprnd2();
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if (isImm32(b)) {
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asm_cmp_imm(cond);
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asm_cmpi_imm(cond);
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return;
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}
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LIns *a = cond->oprnd1();
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@ -1361,7 +1373,7 @@ namespace nanojit
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}
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}
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void Assembler::asm_cmp_imm(LIns *cond) {
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void Assembler::asm_cmpi_imm(LIns *cond) {
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LOpcode condop = cond->opcode();
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LIns *a = cond->oprnd1();
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LIns *b = cond->oprnd2();
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@ -1399,11 +1411,9 @@ namespace nanojit
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// LIR_jt jae ja swap+jae swap+ja jp over je
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// LIR_jf jb jbe swap+jb swap+jbe jne+jp
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NIns* Assembler::asm_branchd(bool onFalse, LIns *cond, NIns *target) {
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NIns* Assembler::asm_branchd_helper(bool onFalse, LIns *cond, NIns *target) {
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LOpcode condop = cond->opcode();
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NIns *patch;
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LIns *a = cond->oprnd1();
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LIns *b = cond->oprnd2();
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if (condop == LIR_eqd) {
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if (onFalse) {
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// branch if unordered or !=
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@ -1422,34 +1432,23 @@ namespace nanojit
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}
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}
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else {
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if (condop == LIR_ltd) {
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condop = LIR_gtd;
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LIns *t = a; a = b; b = t;
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} else if (condop == LIR_led) {
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condop = LIR_ged;
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LIns *t = a; a = b; b = t;
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}
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if (condop == LIR_gtd) {
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if (onFalse)
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JBE(8, target);
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else
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JA(8, target);
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} else { // LIR_ged
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if (onFalse)
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JB(8, target);
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else
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JAE(8, target);
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// LIR_ltd and LIR_gtd are handled by the same case because
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// asm_cmpd() converts LIR_ltd(a,b) to LIR_gtd(b,a). Likewise for
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// LIR_led/LIR_ged.
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switch (condop) {
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case LIR_ltd:
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case LIR_gtd: if (onFalse) JBE(8, target); else JA(8, target); break;
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case LIR_led:
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case LIR_ged: if (onFalse) JB(8, target); else JAE(8, target); break;
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default: NanoAssert(0); break;
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}
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patch = _nIns;
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}
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asm_cmpd(a, b);
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return patch;
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}
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void Assembler::asm_condd(LIns *ins) {
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LOpcode op = ins->opcode();
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LIns *a = ins->oprnd1();
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LIns *b = ins->oprnd2();
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if (op == LIR_eqd) {
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// result = ZF & !PF, must do logic on flags
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// r = al|bl|cl|dl, can only use rh without rex prefix
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@ -1460,30 +1459,40 @@ namespace nanojit
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X86_SETNP(r); // setnp rh rh = !PF
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X86_SETE(r); // sete rl rl = ZF
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} else {
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if (op == LIR_ltd) {
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op = LIR_gtd;
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LIns *t = a; a = b; b = t;
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} else if (op == LIR_led) {
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op = LIR_ged;
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LIns *t = a; a = b; b = t;
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}
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// LIR_ltd and LIR_gtd are handled by the same case because
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// asm_cmpd() converts LIR_ltd(a,b) to LIR_gtd(b,a). Likewise for
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// LIR_led/LIR_ged.
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Register r = prepareResultReg(ins, GpRegs); // x64 can use any GPR as setcc target
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MOVZX8(r, r);
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if (op == LIR_gtd)
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SETA(r);
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else
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SETAE(r);
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switch (op) {
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case LIR_ltd:
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case LIR_gtd: SETA(r); break;
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case LIR_led:
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case LIR_ged: SETAE(r); break;
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default: NanoAssert(0); break;
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}
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}
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freeResourcesOf(ins);
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asm_cmpd(a, b);
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asm_cmpd(ins);
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}
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// WARNING: This function cannot generate any code that will affect the
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// condition codes prior to the generation of the ucomisd. See asm_cmp()
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// condition codes prior to the generation of the ucomisd. See asm_cmpi()
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// for more details.
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void Assembler::asm_cmpd(LIns *a, LIns *b) {
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void Assembler::asm_cmpd(LIns *cond) {
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LOpcode opcode = cond->opcode();
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LIns* a = cond->oprnd1();
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LIns* b = cond->oprnd2();
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// First, we convert (a < b) into (b > a), and (a <= b) into (b >= a).
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if (opcode == LIR_ltd) {
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opcode = LIR_gtd;
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LIns* t = a; a = b; b = t;
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} else if (opcode == LIR_led) {
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opcode = LIR_ged;
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LIns* t = a; a = b; b = t;
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}
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Register ra, rb;
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findRegFor2(FpRegs, a, ra, FpRegs, b, rb);
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UCOMISD(ra, rb);
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@ -1518,7 +1527,7 @@ namespace nanojit
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}
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// WARNING: the code generated by this function must not affect the
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// condition codes. See asm_cmp() for details.
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// condition codes. See asm_cmpi() for details.
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void Assembler::asm_restore(LIns *ins, Register r) {
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if (ins->isop(LIR_allocp)) {
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int d = arDisp(ins);
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@ -1587,7 +1596,7 @@ namespace nanojit
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}
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freeResourcesOf(ins);
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asm_cmp(ins);
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asm_cmpi(ins);
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}
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void Assembler::asm_ret(LIns *ins) {
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@ -423,9 +423,12 @@ namespace nanojit
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void endLoadRegs(LIns *ins);\
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void dis(NIns *p, int bytes);\
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void asm_cmp(LIns*);\
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void asm_cmp_imm(LIns*);\
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void asm_cmpd(LIns*, LIns*);\
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NIns* asm_branchd(bool, LIns*, NIns*);\
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void asm_cmpi(LIns*);\
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void asm_cmpi_imm(LIns*);\
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void asm_cmpd(LIns*);\
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NIns* asm_branch_helper(bool, LIns*, NIns*);\
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NIns* asm_branchi_helper(bool, LIns*, NIns*);\
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NIns* asm_branchd_helper(bool, LIns*, NIns*);\
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void asm_div(LIns *ins);\
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void asm_div_mod(LIns *ins);\
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int max_stk_used;\
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@ -854,8 +854,6 @@ namespace nanojit
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inline void Assembler::FLD1() { count_fpu(); FPUc(0xd9e8); asm_output("fld1"); fpu_push(); }
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inline void Assembler::FLDZ() { count_fpu(); FPUc(0xd9ee); asm_output("fldz"); fpu_push(); }
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inline void Assembler::FFREE(R r) { count_fpu(); FPU(0xddc0, r); asm_output("ffree %s",gpn(r)); }
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inline void Assembler::FST32(bool p, I32 d, R b){ count_stq(); FPUm(0xd902|(p?1:0), d, b); asm_output("fst%s32 %d(%s)", (p?"p":""), d, gpn(b)); if (p) fpu_pop(); }
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inline void Assembler::FSTQ(bool p, I32 d, R b) { count_stq(); FPUm(0xdd02|(p?1:0), d, b); asm_output("fst%sq %d(%s)", (p?"p":""), d, gpn(b)); if (p) fpu_pop(); }
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@ -894,8 +892,6 @@ namespace nanojit
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inline void Assembler::FMULdm( const double* dm) { count_ldq(); FPUdm(0xdc01, dm); asm_output("fmul (%p)", (void*)dm); }
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inline void Assembler::FDIVRdm(const double* dm) { count_ldq(); FPUdm(0xdc07, dm); asm_output("fdivr (%p)", (void*)dm); }
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inline void Assembler::FINCSTP() { count_fpu(); FPUc(0xd9f7); asm_output("fincstp"); fpu_pop(); }
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inline void Assembler::FCOMP() { count_fpu(); FPUc(0xD8D9); asm_output("fcomp"); fpu_pop();}
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inline void Assembler::FCOMPP() { count_fpu(); FPUc(0xDED9); asm_output("fcompp"); fpu_pop();fpu_pop();}
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inline void Assembler::FLDr(R r) { count_ldq(); FPU(0xd9c0, r); asm_output("fld %s", gpn(r)); fpu_push(); }
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@ -1208,7 +1204,7 @@ namespace nanojit
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}
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// WARNING: the code generated by this function must not affect the
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// condition codes. See asm_cmp().
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// condition codes. See asm_cmpi().
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void Assembler::asm_restore(LIns* ins, Register r)
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{
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NanoAssert(ins->getReg() == r);
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@ -1521,19 +1517,18 @@ namespace nanojit
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}
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}
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NIns* Assembler::asm_branch(bool branchOnFalse, LIns* cond, NIns* targ)
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NIns* Assembler::asm_branch_helper(bool branchOnFalse, LIns* cond, NIns* targ)
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{
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LOpcode condop = cond->opcode();
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NanoAssert(cond->isCmp());
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// Handle float conditions separately.
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if (isCmpDOpcode(condop)) {
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return asm_branchd(branchOnFalse, cond, targ);
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}
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return isCmpDOpcode(cond->opcode())
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? asm_branchd_helper(branchOnFalse, cond, targ)
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: asm_branchi_helper(branchOnFalse, cond, targ);
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}
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NIns* Assembler::asm_branchi_helper(bool branchOnFalse, LIns* cond, NIns* targ)
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{
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if (branchOnFalse) {
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// op == LIR_xf/LIR_jf
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switch (condop) {
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switch (cond->opcode()) {
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case LIR_eqi: JNE(targ); break;
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case LIR_lti: JNL(targ); break;
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case LIR_lei: JNLE(targ); break;
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@ -1547,7 +1542,7 @@ namespace nanojit
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}
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} else {
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// op == LIR_xt/LIR_jt
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switch (condop) {
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switch (cond->opcode()) {
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case LIR_eqi: JE(targ); break;
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case LIR_lti: JL(targ); break;
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case LIR_lei: JLE(targ); break;
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@ -1560,7 +1555,12 @@ namespace nanojit
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default: NanoAssert(0); break;
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}
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}
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NIns* at = _nIns;
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return _nIns;
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}
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NIns* Assembler::asm_branch(bool branchOnFalse, LIns* cond, NIns* targ)
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{
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NIns* at = asm_branch_helper(branchOnFalse, cond, targ);
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asm_cmp(cond);
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return at;
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}
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@ -1584,6 +1584,11 @@ namespace nanojit
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JMP_indexed(indexreg, 2, table);
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}
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void Assembler::asm_cmp(LIns *cond)
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{
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isCmpDOpcode(cond->opcode()) ? asm_cmpd(cond) : asm_cmpi(cond);
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}
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// This generates a 'test' or 'cmp' instruction for a condition, which
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// causes the condition codes to be set appropriately. It's used with
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// conditional branches, conditional moves, and when generating
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@ -1623,7 +1628,7 @@ namespace nanojit
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// asm_restore(), that means that asm_restore() cannot generate code which
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// affects the condition codes.
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//
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void Assembler::asm_cmp(LIns *cond)
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void Assembler::asm_cmpi(LIns *cond)
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{
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LIns* lhs = cond->oprnd1();
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LIns* rhs = cond->oprnd2();
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@ -1734,7 +1739,7 @@ namespace nanojit
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freeResourcesOf(ins);
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asm_cmp(ins);
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asm_cmpi(ins);
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}
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// Two example cases for "ins = add lhs, rhs". '*' lines are those
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@ -2051,11 +2056,10 @@ namespace nanojit
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(ins->isop(LIR_cmovd) && iftrue->isD() && iffalse->isD()));
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if (!_config.i386_sse2 && ins->isop(LIR_cmovd)) {
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// See the SSE2 case below for an explanation of the subtleties here.
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debug_only( Register rr = ) prepareResultReg(ins, x87Regs);
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NanoAssert(FST0 == rr);
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NanoAssert(!iftrue->isInReg() || iftrue->getReg() == FST0);
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NanoAssert(!iffalse->isInReg());
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NanoAssert(!iftrue->isInReg() && !iffalse->isInReg());
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NIns* target = _nIns;
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@ -2065,52 +2069,73 @@ namespace nanojit
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int df = findMemFor(iffalse);
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FLDQ(df, FP);
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}
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FSTP(FST0); // pop the stack
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asm_branch_helper(false, condval, target);
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FINCSTP();
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// Its not sufficient to merely decrement the FP stack pointer, we have to
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// also free FST0, otherwise the load above fails.
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FFREE(FST0);
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asm_branch(false, condval, target);
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NanoAssert(ins->getReg() == rr);
|
||||
freeResourcesOf(ins);
|
||||
if (!iftrue->isInReg())
|
||||
findSpecificRegForUnallocated(iftrue, FST0);
|
||||
|
||||
asm_cmp(condval);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
RegisterMask allow = ins->isD() ? XmmRegs : GpRegs;
|
||||
|
||||
Register rr = prepareResultReg(ins, allow);
|
||||
|
||||
Register rf = findRegFor(iffalse, allow & ~rmask(rr));
|
||||
|
||||
if (ins->isop(LIR_cmovd)) {
|
||||
// The obvious way to handle this is as follows:
|
||||
//
|
||||
// mov rr, rt # only needed if rt is live afterwards
|
||||
// do comparison
|
||||
// jt end
|
||||
// mov rr, rf
|
||||
// end:
|
||||
//
|
||||
// The problem with this is that doing the comparison can cause
|
||||
// registers to be evicted, possibly including 'rr', which holds
|
||||
// 'ins'. And that screws things up. So instead we do this:
|
||||
//
|
||||
// do comparison
|
||||
// mov rr, rt # only needed if rt is live afterwards
|
||||
// jt end
|
||||
// mov rr, rf
|
||||
// end:
|
||||
//
|
||||
// Putting the 'mov' between the comparison and the jump is ok
|
||||
// because move instructions don't modify the condition codes.
|
||||
//
|
||||
NIns* target = _nIns;
|
||||
asm_nongp_copy(rr, rf);
|
||||
asm_branch(false, condval, target);
|
||||
asm_branch_helper(false, condval, target);
|
||||
|
||||
// If 'iftrue' isn't in a register, it can be clobbered by 'ins'.
|
||||
Register rt = iftrue->isInReg() ? iftrue->getReg() : rr;
|
||||
|
||||
if (rr != rt)
|
||||
asm_nongp_copy(rr, rt);
|
||||
|
||||
NanoAssert(ins->getReg() == rr);
|
||||
freeResourcesOf(ins);
|
||||
if (!iftrue->isInReg()) {
|
||||
NanoAssert(rt == rr);
|
||||
findSpecificRegForUnallocated(iftrue, rr);
|
||||
}
|
||||
|
||||
asm_cmp(condval);
|
||||
return;
|
||||
}
|
||||
|
||||
// If 'iftrue' isn't in a register, it can be clobbered by 'ins'.
|
||||
Register rt = iftrue->isInReg() ? iftrue->getReg() : rr;
|
||||
|
||||
NanoAssert(ins->isop(LIR_cmovi));
|
||||
|
||||
// WARNING: We cannot generate any code that affects the condition
|
||||
// codes between the MRcc generation here and the asm_cmp() call
|
||||
// below. See asm_cmp() for more details.
|
||||
// codes between the MRcc generation here and the asm_cmpi() call
|
||||
// below. See asm_cmpi() for more details.
|
||||
switch (condval->opcode()) {
|
||||
// Note that these are all opposites...
|
||||
case LIR_eqi: MRNE(rr, rf); break;
|
||||
@ -2128,6 +2153,7 @@ namespace nanojit
|
||||
if (rr != rt)
|
||||
MR(rr, rt);
|
||||
|
||||
NanoAssert(ins->getReg() == rr);
|
||||
freeResourcesOf(ins);
|
||||
if (!iftrue->isInReg()) {
|
||||
NanoAssert(rt == rr);
|
||||
@ -2614,7 +2640,7 @@ namespace nanojit
|
||||
}
|
||||
}
|
||||
|
||||
NIns* Assembler::asm_branchd(bool branchOnFalse, LIns *cond, NIns *targ)
|
||||
NIns* Assembler::asm_branchd_helper(bool branchOnFalse, LIns* cond, NIns *targ)
|
||||
{
|
||||
NIns* at = 0;
|
||||
LOpcode opcode = cond->opcode();
|
||||
@ -2673,14 +2699,13 @@ namespace nanojit
|
||||
|
||||
if (!at)
|
||||
at = _nIns;
|
||||
asm_cmpd(cond);
|
||||
|
||||
return at;
|
||||
}
|
||||
|
||||
// WARNING: This function cannot generate any code that will affect the
|
||||
// condition codes prior to the generation of the
|
||||
// ucomisd/fcompp/fcmop/fcom. See asm_cmp() for more details.
|
||||
// ucomisd/fcompp/fcmop/fcom. See asm_cmpi() for more details.
|
||||
void Assembler::asm_cmpd(LIns *cond)
|
||||
{
|
||||
LOpcode condop = cond->opcode();
|
||||
@ -2699,14 +2724,13 @@ namespace nanojit
|
||||
LIns* t = lhs; lhs = rhs; rhs = t;
|
||||
}
|
||||
|
||||
|
||||
// LIR_eqd, if lhs == rhs:
|
||||
// ucomisd ZPC outcome (SETNP/JNP succeeds if P==0)
|
||||
// ------- --- -------
|
||||
// UNORDERED 111 SETNP/JNP fails
|
||||
// EQUAL 100 SETNP/JNP succeeds
|
||||
//
|
||||
// LIR_eqd, if lsh != rhs;
|
||||
// LIR_eqd, if lhs != rhs;
|
||||
// ucomisd ZPC outcome (SETP/JP succeeds if P==0,
|
||||
// SETE/JE succeeds if Z==0)
|
||||
// ------- --- -------
|
||||
@ -2810,13 +2834,10 @@ namespace nanojit
|
||||
} else {
|
||||
TEST_AH(mask);
|
||||
FNSTSW_AX(); // requires rEAX to be free
|
||||
if (rhs->isImmD())
|
||||
{
|
||||
if (rhs->isImmD()) {
|
||||
const uint64_t* p = findImmDFromPool(rhs->immDasQ());
|
||||
FCOMdm(pop, (const double*)p);
|
||||
}
|
||||
else
|
||||
{
|
||||
} else {
|
||||
int d = findMemFor(rhs);
|
||||
FCOM(pop, d, FP);
|
||||
}
|
||||
|
||||
@ -199,9 +199,12 @@ namespace nanojit
|
||||
void asm_farg(LIns*, int32_t& stkd);\
|
||||
void asm_arg(ArgType ty, LIns* p, Register r, int32_t& stkd);\
|
||||
void asm_pusharg(LIns*);\
|
||||
void asm_cmpd(LIns *cond);\
|
||||
NIns* asm_branchd(bool, LIns*, NIns*);\
|
||||
void asm_cmp(LIns *cond); \
|
||||
void asm_cmpi(LIns *cond); \
|
||||
void asm_cmpd(LIns *cond);\
|
||||
NIns* asm_branch_helper(bool, LIns* cond, NIns*);\
|
||||
NIns* asm_branchi_helper(bool, LIns* cond, NIns*);\
|
||||
NIns* asm_branchd_helper(bool, LIns* cond, NIns*);\
|
||||
void asm_div_mod(LIns *cond); \
|
||||
void asm_load(int d, Register r); \
|
||||
void asm_immd(Register r, uint64_t q, double d, bool canClobberCCs); \
|
||||
@ -429,7 +432,6 @@ namespace nanojit
|
||||
void FCHS(); \
|
||||
void FLD1(); \
|
||||
void FLDZ(); \
|
||||
void FFREE(Register r); \
|
||||
void FST32(bool p, int32_t d, Register b); \
|
||||
void FSTQ(bool p, int32_t d, Register b); \
|
||||
void FSTPQ(int32_t d, Register b); \
|
||||
@ -451,7 +453,6 @@ namespace nanojit
|
||||
void FSUBRdm(const double* dm); \
|
||||
void FMULdm( const double* dm); \
|
||||
void FDIVRdm(const double* dm); \
|
||||
void FINCSTP(); \
|
||||
void FSTP(Register r) { \
|
||||
count_fpu(); \
|
||||
FPU(0xddd8, r); \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user